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Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
Borislav Petkovb01aec92015-05-21 19:59:31 +02005
6config EDAC_ATOMIC_SCRUB
7 bool
Alan Coxda9bb1d2006-01-18 17:44:13 -08008
Borislav Petkov544516632012-12-18 22:02:56 +01009config EDAC_SUPPORT
10 bool
11
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070012menuconfig EDAC
Borislav Petkove3c4ff62017-02-03 18:18:05 +010013 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
Alan Coxda9bb1d2006-01-18 17:44:13 -080015 help
Borislav Petkova06b85f2017-02-04 16:32:27 +010016 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
Douglas Thompson8cb2a392007-07-19 01:50:12 -070019 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080021
Borislav Petkova06b85f2017-02-04 16:32:27 +010022 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
Tim Small57c432b2006-03-09 17:33:50 -080023
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070024if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080025
Mauro Carvalho Chehab19974712012-03-21 17:06:53 -030026config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
Alan Coxda9bb1d2006-01-18 17:44:13 -080034config EDAC_DEBUG
35 bool "Debugging"
Borislav Petkov1c5bf782017-03-18 18:25:05 +010036 select DEBUG_FS
Alan Coxda9bb1d2006-01-18 17:44:13 -080037 help
Borislav Petkov37929872012-09-10 16:50:54 +020038 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
Alan Coxda9bb1d2006-01-18 17:44:13 -080042
Borislav Petkov9cdeb402010-09-02 18:33:24 +020043config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020044 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -030045 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020046 default y
47 ---help---
48 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030049 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020050
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
Mauro Carvalho Chehab77c5f5d2013-02-15 06:11:57 -030055config EDAC_GHES
56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +010057 depends on ACPI_APEI_GHES && (EDAC=y)
Mauro Carvalho Chehab77c5f5d2013-02-15 06:11:57 -030058 help
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
61 APEI/GHES driver. By enabling this option, the error reports provided
62 by GHES are sent to userspace via the EDAC API.
63
64 When this option is enabled, it will disable the hardware-driven
65 mechanisms, if a GHES BIOS is detected, entering into the
66 "Firmware First" mode.
67
68 It should be noticed that keeping both GHES and a hardware-driven
69 error mechanism won't work well, as BIOS will race with OS, while
70 reading the error registers. So, if you want to not use "Firmware
71 first" GHES error mechanism, you should disable GHES either at
72 compilation time or by passing "ghes.disable=1" Kernel parameter
73 at boot time.
74
75 In doubt, say 'Y'.
76
Doug Thompson7d6034d2009-04-27 20:01:01 +020077config EDAC_AMD64
Tomasz Palaf5b10c42014-11-02 11:22:12 +010078 tristate "AMD64 (Opteron, Athlon64)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +010079 depends on AMD_NB && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020080 help
Borislav Petkov027dbd62010-10-13 22:12:15 +020081 Support for error detection and correction of DRAM ECC errors on
Tomasz Palaf5b10c42014-11-02 11:22:12 +010082 the AMD64 families (>= K8) of memory controllers.
Doug Thompson7d6034d2009-04-27 20:01:01 +020083
84config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +020085 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +020086 depends on EDAC_AMD64
87 help
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
91 errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800102
103config EDAC_AMD76X
104 tristate "AMD 76x (760, 762, 768)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100105 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800106 help
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
109
110config EDAC_E7XXX
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100112 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800113 help
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
116
117config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100119 depends on PCI && X86
Alan Coxda9bb1d2006-01-18 17:44:13 -0800120 help
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
123
Tim Small5a2c6752007-07-19 01:49:42 -0700124config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100126 depends on PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700127 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700128 help
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
131
Alan Coxda9bb1d2006-01-18 17:44:13 -0800132config EDAC_I82875P
133 tristate "Intel 82875p (D82875P, E7210)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100134 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800135 help
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
138
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700139config EDAC_I82975X
140 tristate "Intel 82975x (D82975x)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100141 depends on PCI && X86
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700142 help
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
145
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700146config EDAC_I3000
147 tristate "Intel 3000/3010"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100148 depends on PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700149 help
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
152
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700153config EDAC_I3200
154 tristate "Intel 3200"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100155 depends on PCI && X86
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700156 help
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
159
Jason Baron7ee40b82014-07-04 13:48:32 +0200160config EDAC_IE31200
161 tristate "Intel e312xx"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100162 depends on PCI && X86
Jason Baron7ee40b82014-07-04 13:48:32 +0200163 help
164 Support for error detection and correction on the Intel
165 E3-1200 based DRAM controllers.
166
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700167config EDAC_X38
168 tristate "Intel X38"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100169 depends on PCI && X86
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700170 help
171 Support for error detection and correction on the Intel
172 X38 server chipsets.
173
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800174config EDAC_I5400
175 tristate "Intel 5400 (Seaburg) chipsets"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100176 depends on PCI && X86
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800177 help
178 Support for error detection and correction the Intel
179 i5400 MCH chipset (Seaburg).
180
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300181config EDAC_I7CORE
182 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100183 depends on PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300184 help
185 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300186 i7 Core (Nehalem) Integrated Memory Controller that exists on
187 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
188 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300189
Alan Coxda9bb1d2006-01-18 17:44:13 -0800190config EDAC_I82860
191 tristate "Intel 82860"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100192 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800193 help
194 Support for error detection and correction on the Intel
195 82860 chipset.
196
197config EDAC_R82600
198 tristate "Radisys 82600 embedded chipset"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100199 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800200 help
201 Support for error detection and correction on the Radisys
202 82600 embedded chipset.
203
Eric Wolleseneb607052007-07-19 01:49:39 -0700204config EDAC_I5000
205 tristate "Intel Greencreek/Blackford chipset"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100206 depends on X86 && PCI
Eric Wolleseneb607052007-07-19 01:49:39 -0700207 help
208 Support for error detection and correction the Intel
209 Greekcreek/Blackford chipsets.
210
Arthur Jones8f421c592008-07-25 01:49:04 -0700211config EDAC_I5100
212 tristate "Intel San Clemente MCH"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100213 depends on X86 && PCI
Arthur Jones8f421c592008-07-25 01:49:04 -0700214 help
215 Support for error detection and correction the Intel
216 San Clemente MCH.
217
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300218config EDAC_I7300
219 tristate "Intel Clarksboro MCH"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100220 depends on X86 && PCI
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300221 help
222 Support for error detection and correction the Intel
223 Clarksboro MCH (Intel 7300 chipset).
224
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200225config EDAC_SBRIDGE
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300226 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100227 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200228 help
229 Support for error detection and correction the Intel
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300230 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200231
Tony Luck4ec656b2016-08-20 16:27:58 -0700232config EDAC_SKX
233 tristate "Intel Skylake server Integrated MC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
Tony Luck4ec656b2016-08-20 16:27:58 -0700235 help
236 Support for error detection and correction the Intel
237 Skylake server Integrated Memory Controllers.
238
Tony Luck5c71ad12017-03-09 01:45:39 +0800239config EDAC_PND2
240 tristate "Intel Pondicherry2"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100241 depends on PCI && X86_64 && X86_MCE_INTEL
Tony Luck5c71ad12017-03-09 01:45:39 +0800242 help
243 Support for error detection and correction on the Intel
244 Pondicherry2 Integrated Memory Controller. This SoC IP is
245 first used on the Apollo Lake platform and Denverton
246 micro-server but may appear on others in the future.
247
Dave Jianga9a753d2008-02-07 00:14:55 -0800248config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700249 tristate "Freescale MPC83xx / MPC85xx"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100250 depends on FSL_SOC
Dave Jianga9a753d2008-02-07 00:14:55 -0800251 help
252 Support for error detection and correction on the Freescale
York Sun74210262015-05-12 18:03:41 +0800253 MPC8349, MPC8560, MPC8540, MPC8548, T4240
Dave Jianga9a753d2008-02-07 00:14:55 -0800254
York Suneeb3d682016-08-23 15:14:03 -0700255config EDAC_LAYERSCAPE
256 tristate "Freescale Layerscape DDR"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100257 depends on ARCH_LAYERSCAPE
York Suneeb3d682016-08-23 15:14:03 -0700258 help
259 Support for error detection and correction on Freescale memory
260 controllers on Layerscape SoCs.
261
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800262config EDAC_MV64X60
263 tristate "Marvell MV64x60"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100264 depends on MV64X60
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800265 help
266 Support for error detection and correction on the Marvell
267 MV64360 and MV64460 chipsets.
268
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700269config EDAC_PASEMI
270 tristate "PA Semi PWRficient"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100271 depends on PPC_PASEMI && PCI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700272 help
273 Support for error detection and correction on PA Semi
274 PWRficient.
275
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800276config EDAC_CELL
277 tristate "Cell Broadband Engine memory controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100278 depends on PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800279 help
280 Support for error detection and correction on the
281 Cell Broadband Engine internal memory controller
282 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700283
Grant Ericksondba7a772009-04-02 16:58:45 -0700284config EDAC_PPC4XX
285 tristate "PPC4xx IBM DDR2 Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100286 depends on 4xx
Grant Ericksondba7a772009-04-02 16:58:45 -0700287 help
288 This enables support for EDAC on the ECC memory used
289 with the IBM DDR2 memory controller found in various
290 PowerPC 4xx embedded processors such as the 405EX[r],
291 440SP, 440SPe, 460EX, 460GT and 460SX.
292
Harry Ciaoe8765582009-04-02 16:58:51 -0700293config EDAC_AMD8131
294 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100295 depends on PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700296 help
297 Support for error detection and correction on the
298 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700299 Note, add more Kconfig dependency if it's adopted
300 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700301
Harry Ciao58b4ce62009-04-02 16:58:51 -0700302config EDAC_AMD8111
303 tristate "AMD8111 HyperTransport I/O Hub"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100304 depends on PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700305 help
306 Support for error detection and correction on the
307 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700308 Note, add more Kconfig dependency if it's adopted
309 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700310
Harry Ciao2a9036a2009-06-17 16:27:58 -0700311config EDAC_CPC925
312 tristate "IBM CPC925 Memory Controller (PPC970FX)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100313 depends on PPC64
Harry Ciao2a9036a2009-06-17 16:27:58 -0700314 help
315 Support for error detection and correction on the
316 IBM CPC925 Bridge and Memory Controller, which is
317 a companion chip to the PowerPC 970 family of
318 processors.
319
Chris Metcalf5c770752011-03-01 13:01:49 -0500320config EDAC_TILE
321 tristate "Tilera Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100322 depends on TILE
Chris Metcalf5c770752011-03-01 13:01:49 -0500323 default y
324 help
325 Support for error detection and correction on the
326 Tilera memory controller.
327
Rob Herringa1b01ed2012-06-13 12:01:55 -0500328config EDAC_HIGHBANK_MC
329 tristate "Highbank Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100330 depends on ARCH_HIGHBANK
Rob Herringa1b01ed2012-06-13 12:01:55 -0500331 help
332 Support for error detection and correction on the
333 Calxeda Highbank memory controller.
334
Rob Herring69154d02012-06-11 21:32:14 -0500335config EDAC_HIGHBANK_L2
336 tristate "Highbank L2 Cache"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100337 depends on ARCH_HIGHBANK
Rob Herring69154d02012-06-11 21:32:14 -0500338 help
339 Support for error detection and correction on the
340 Calxeda Highbank memory controller.
341
Ralf Baechlef65aad42012-10-17 00:39:09 +0200342config EDAC_OCTEON_PC
343 tristate "Cavium Octeon Primary Caches"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100344 depends on CPU_CAVIUM_OCTEON
Ralf Baechlef65aad42012-10-17 00:39:09 +0200345 help
346 Support for error detection and correction on the primary caches of
347 the cnMIPS cores of Cavium Octeon family SOCs.
348
349config EDAC_OCTEON_L2C
350 tristate "Cavium Octeon Secondary Caches (L2C)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100351 depends on CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200352 help
353 Support for error detection and correction on the
354 Cavium Octeon family of SOCs.
355
356config EDAC_OCTEON_LMC
357 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100358 depends on CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200359 help
360 Support for error detection and correction on the
361 Cavium Octeon family of SOCs.
362
363config EDAC_OCTEON_PCI
364 tristate "Cavium Octeon PCI Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100365 depends on PCI && CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200366 help
367 Support for error detection and correction on the
368 Cavium Octeon family of SOCs.
369
Sergey Temerkhanov41003392017-03-24 22:28:37 +0000370config EDAC_THUNDERX
371 tristate "Cavium ThunderX EDAC"
Sergey Temerkhanov41003392017-03-24 22:28:37 +0000372 depends on ARM64
373 depends on PCI
374 help
375 Support for error detection and correction on the
376 Cavium ThunderX memory controllers (LMC), Cache
377 Coherent Processor Interconnect (CCPI) and L2 cache
378 blocks (TAD, CBC, MCI).
379
Thor Thayerc3eea192016-02-10 13:26:21 -0600380config EDAC_ALTERA
381 bool "Altera SOCFPGA ECC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100382 depends on EDAC=y && ARCH_SOCFPGA
Thor Thayer71bcada2014-09-03 10:27:54 -0500383 help
384 Support for error detection and correction on the
Thor Thayerc3eea192016-02-10 13:26:21 -0600385 Altera SOCs. This must be selected for SDRAM ECC.
386 Note that the preloader must initialize the SDRAM
387 before loading the kernel.
388
389config EDAC_ALTERA_L2C
390 bool "Altera L2 Cache ECC"
Thor Thayer3a8f21f2016-03-21 11:01:38 -0500391 depends on EDAC_ALTERA=y && CACHE_L2X0
Thor Thayerc3eea192016-02-10 13:26:21 -0600392 help
393 Support for error detection and correction on the
394 Altera L2 cache Memory for Altera SoCs. This option
Thor Thayer3a8f21f2016-03-21 11:01:38 -0500395 requires L2 cache.
Thor Thayerc3eea192016-02-10 13:26:21 -0600396
397config EDAC_ALTERA_OCRAM
398 bool "Altera On-Chip RAM ECC"
399 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
400 help
401 Support for error detection and correction on the
402 Altera On-Chip RAM Memory for Altera SoCs.
Thor Thayer71bcada2014-09-03 10:27:54 -0500403
Thor Thayerab8c1e02016-06-22 08:58:58 -0500404config EDAC_ALTERA_ETHERNET
405 bool "Altera Ethernet FIFO ECC"
406 depends on EDAC_ALTERA=y
407 help
408 Support for error detection and correction on the
409 Altera Ethernet FIFO Memory for Altera SoCs.
410
Thor Thayerc6882fb2016-07-14 11:06:43 -0500411config EDAC_ALTERA_NAND
412 bool "Altera NAND FIFO ECC"
413 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
414 help
415 Support for error detection and correction on the
416 Altera NAND FIFO Memory for Altera SoCs.
417
Thor Thayere8263792016-07-28 10:03:57 +0200418config EDAC_ALTERA_DMA
419 bool "Altera DMA FIFO ECC"
420 depends on EDAC_ALTERA=y && PL330_DMA=y
421 help
422 Support for error detection and correction on the
423 Altera DMA FIFO Memory for Altera SoCs.
424
Thor Thayerc6095812016-07-14 11:06:45 -0500425config EDAC_ALTERA_USB
426 bool "Altera USB FIFO ECC"
427 depends on EDAC_ALTERA=y && USB_DWC2
428 help
429 Support for error detection and correction on the
430 Altera USB FIFO Memory for Altera SoCs.
431
Thor Thayer485fe9e2016-07-14 11:06:46 -0500432config EDAC_ALTERA_QSPI
433 bool "Altera QSPI FIFO ECC"
434 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
435 help
436 Support for error detection and correction on the
437 Altera QSPI FIFO Memory for Altera SoCs.
438
Thor Thayer91104982016-08-09 09:40:52 -0500439config EDAC_ALTERA_SDMMC
440 bool "Altera SDMMC FIFO ECC"
441 depends on EDAC_ALTERA=y && MMC_DW
442 help
443 Support for error detection and correction on the
444 Altera SDMMC FIFO Memory for Altera SoCs.
445
Punnaiah Choudary Kalluriae9b56e2015-01-06 23:13:47 +0530446config EDAC_SYNOPSYS
447 tristate "Synopsys DDR Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100448 depends on ARCH_ZYNQ
Punnaiah Choudary Kalluriae9b56e2015-01-06 23:13:47 +0530449 help
450 Support for error detection and correction on the Synopsys DDR
451 memory controller.
452
Loc Ho0d442932015-05-22 17:32:59 -0600453config EDAC_XGENE
454 tristate "APM X-Gene SoC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100455 depends on (ARM64 || COMPILE_TEST)
Loc Ho0d442932015-05-22 17:32:59 -0600456 help
457 Support for error detection and correction on the
458 APM X-Gene family of SOCs.
459
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700460endif # EDAC