Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 1 | # |
| 2 | # EDAC Kconfig |
Doug Thompson | 4577ca5 | 2009-04-02 16:58:43 -0700 | [diff] [blame] | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 4 | # Licensed and distributed under the GPL |
Borislav Petkov | b01aec9 | 2015-05-21 19:59:31 +0200 | [diff] [blame] | 5 | |
| 6 | config EDAC_ATOMIC_SCRUB |
| 7 | bool |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 8 | |
Borislav Petkov | 54451663 | 2012-12-18 22:02:56 +0100 | [diff] [blame] | 9 | config EDAC_SUPPORT |
| 10 | bool |
| 11 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 12 | menuconfig EDAC |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 13 | tristate "EDAC (Error Detection And Correction) reporting" |
| 14 | depends on HAS_IOMEM && EDAC_SUPPORT && RAS |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 15 | help |
Borislav Petkov | a06b85f | 2017-02-04 16:32:27 +0100 | [diff] [blame] | 16 | EDAC is a subsystem along with hardware-specific drivers designed to |
| 17 | report hardware errors. These are low-level errors that are reported |
| 18 | in the CPU or supporting chipset or other subsystems: |
Douglas Thompson | 8cb2a39 | 2007-07-19 01:50:12 -0700 | [diff] [blame] | 19 | memory errors, cache errors, PCI errors, thermal throttling, etc.. |
| 20 | If unsure, select 'Y'. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 21 | |
Borislav Petkov | a06b85f | 2017-02-04 16:32:27 +0100 | [diff] [blame] | 22 | The mailing list for the EDAC project is linux-edac@vger.kernel.org. |
Tim Small | 57c432b | 2006-03-09 17:33:50 -0800 | [diff] [blame] | 23 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 24 | if EDAC |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 25 | |
Mauro Carvalho Chehab | 1997471 | 2012-03-21 17:06:53 -0300 | [diff] [blame] | 26 | config EDAC_LEGACY_SYSFS |
| 27 | bool "EDAC legacy sysfs" |
| 28 | default y |
| 29 | help |
| 30 | Enable the compatibility sysfs nodes. |
| 31 | Use 'Y' if your edac utilities aren't ported to work with the newer |
| 32 | structures. |
| 33 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 34 | config EDAC_DEBUG |
| 35 | bool "Debugging" |
Borislav Petkov | 1c5bf78 | 2017-03-18 18:25:05 +0100 | [diff] [blame] | 36 | select DEBUG_FS |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 37 | help |
Borislav Petkov | 3792987 | 2012-09-10 16:50:54 +0200 | [diff] [blame] | 38 | This turns on debugging information for the entire EDAC subsystem. |
| 39 | You do so by inserting edac_module with "edac_debug_level=x." Valid |
| 40 | levels are 0-4 (from low to high) and by default it is set to 2. |
| 41 | Usually you should select 'N' here. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 42 | |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 43 | config EDAC_DECODE_MCE |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 44 | tristate "Decode MCEs in human-readable form (only on AMD for now)" |
Borislav Petkov | 168eb34 | 2011-08-10 09:43:30 -0300 | [diff] [blame] | 45 | depends on CPU_SUP_AMD && X86_MCE_AMD |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 46 | default y |
| 47 | ---help--- |
| 48 | Enable this option if you want to decode Machine Check Exceptions |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 49 | occurring on your machine in human-readable form. |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 50 | |
| 51 | You should definitely say Y here in case you want to decode MCEs |
| 52 | which occur really early upon boot, before the module infrastructure |
| 53 | has been initialized. |
| 54 | |
Mauro Carvalho Chehab | 77c5f5d | 2013-02-15 06:11:57 -0300 | [diff] [blame] | 55 | config EDAC_GHES |
| 56 | bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 57 | depends on ACPI_APEI_GHES && (EDAC=y) |
Mauro Carvalho Chehab | 77c5f5d | 2013-02-15 06:11:57 -0300 | [diff] [blame] | 58 | help |
| 59 | Not all machines support hardware-driven error report. Some of those |
| 60 | provide a BIOS-driven error report mechanism via ACPI, using the |
| 61 | APEI/GHES driver. By enabling this option, the error reports provided |
| 62 | by GHES are sent to userspace via the EDAC API. |
| 63 | |
| 64 | When this option is enabled, it will disable the hardware-driven |
| 65 | mechanisms, if a GHES BIOS is detected, entering into the |
| 66 | "Firmware First" mode. |
| 67 | |
| 68 | It should be noticed that keeping both GHES and a hardware-driven |
| 69 | error mechanism won't work well, as BIOS will race with OS, while |
| 70 | reading the error registers. So, if you want to not use "Firmware |
| 71 | first" GHES error mechanism, you should disable GHES either at |
| 72 | compilation time or by passing "ghes.disable=1" Kernel parameter |
| 73 | at boot time. |
| 74 | |
| 75 | In doubt, say 'Y'. |
| 76 | |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 77 | config EDAC_AMD64 |
Tomasz Pala | f5b10c4 | 2014-11-02 11:22:12 +0100 | [diff] [blame] | 78 | tristate "AMD64 (Opteron, Athlon64)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 79 | depends on AMD_NB && EDAC_DECODE_MCE |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 80 | help |
Borislav Petkov | 027dbd6 | 2010-10-13 22:12:15 +0200 | [diff] [blame] | 81 | Support for error detection and correction of DRAM ECC errors on |
Tomasz Pala | f5b10c4 | 2014-11-02 11:22:12 +0100 | [diff] [blame] | 82 | the AMD64 families (>= K8) of memory controllers. |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 83 | |
| 84 | config EDAC_AMD64_ERROR_INJECTION |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 85 | bool "Sysfs HW Error injection facilities" |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 86 | depends on EDAC_AMD64 |
| 87 | help |
| 88 | Recent Opterons (Family 10h and later) provide for Memory Error |
| 89 | Injection into the ECC detection circuits. The amd64_edac module |
| 90 | allows the operator/user to inject Uncorrectable and Correctable |
| 91 | errors into DRAM. |
| 92 | |
| 93 | When enabled, in each of the respective memory controller directories |
| 94 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: |
| 95 | |
| 96 | - inject_section (0..3, 16-byte section of 64-byte cacheline), |
| 97 | - inject_word (0..8, 16-bit word of 16-byte section), |
| 98 | - inject_ecc_vector (hex ecc vector: select bits of inject word) |
| 99 | |
| 100 | In addition, there are two control files, inject_read and inject_write, |
| 101 | which trigger the DRAM ECC Read and Write respectively. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 102 | |
| 103 | config EDAC_AMD76X |
| 104 | tristate "AMD 76x (760, 762, 768)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 105 | depends on PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 106 | help |
| 107 | Support for error detection and correction on the AMD 76x |
| 108 | series of chipsets used with the Athlon processor. |
| 109 | |
| 110 | config EDAC_E7XXX |
| 111 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 112 | depends on PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 113 | help |
| 114 | Support for error detection and correction on the Intel |
| 115 | E7205, E7500, E7501 and E7505 server chipsets. |
| 116 | |
| 117 | config EDAC_E752X |
Andrei Konovalov | 5135b79 | 2008-04-29 01:03:13 -0700 | [diff] [blame] | 118 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 119 | depends on PCI && X86 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 120 | help |
| 121 | Support for error detection and correction on the Intel |
| 122 | E7520, E7525, E7320 server chipsets. |
| 123 | |
Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 124 | config EDAC_I82443BXGX |
| 125 | tristate "Intel 82443BX/GX (440BX/GX)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 126 | depends on PCI && X86_32 |
Andrew Morton | 28f96eea | 2007-07-19 01:49:45 -0700 | [diff] [blame] | 127 | depends on BROKEN |
Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 128 | help |
| 129 | Support for error detection and correction on the Intel |
| 130 | 82443BX/GX memory controllers (440BX/GX chipsets). |
| 131 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 132 | config EDAC_I82875P |
| 133 | tristate "Intel 82875p (D82875P, E7210)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 134 | depends on PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 135 | help |
| 136 | Support for error detection and correction on the Intel |
| 137 | DP82785P and E7210 server chipsets. |
| 138 | |
Ranganathan Desikan | 420390f | 2007-07-19 01:50:31 -0700 | [diff] [blame] | 139 | config EDAC_I82975X |
| 140 | tristate "Intel 82975x (D82975x)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 141 | depends on PCI && X86 |
Ranganathan Desikan | 420390f | 2007-07-19 01:50:31 -0700 | [diff] [blame] | 142 | help |
| 143 | Support for error detection and correction on the Intel |
| 144 | DP82975x server chipsets. |
| 145 | |
Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 146 | config EDAC_I3000 |
| 147 | tristate "Intel 3000/3010" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 148 | depends on PCI && X86 |
Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 149 | help |
| 150 | Support for error detection and correction on the Intel |
| 151 | 3000 and 3010 server chipsets. |
| 152 | |
Jason Uhlenkott | dd8ef1d | 2009-09-23 15:57:27 -0700 | [diff] [blame] | 153 | config EDAC_I3200 |
| 154 | tristate "Intel 3200" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 155 | depends on PCI && X86 |
Jason Uhlenkott | dd8ef1d | 2009-09-23 15:57:27 -0700 | [diff] [blame] | 156 | help |
| 157 | Support for error detection and correction on the Intel |
| 158 | 3200 and 3210 server chipsets. |
| 159 | |
Jason Baron | 7ee40b8 | 2014-07-04 13:48:32 +0200 | [diff] [blame] | 160 | config EDAC_IE31200 |
| 161 | tristate "Intel e312xx" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 162 | depends on PCI && X86 |
Jason Baron | 7ee40b8 | 2014-07-04 13:48:32 +0200 | [diff] [blame] | 163 | help |
| 164 | Support for error detection and correction on the Intel |
| 165 | E3-1200 based DRAM controllers. |
| 166 | |
Hitoshi Mitake | df8bc08c | 2008-10-29 14:00:50 -0700 | [diff] [blame] | 167 | config EDAC_X38 |
| 168 | tristate "Intel X38" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 169 | depends on PCI && X86 |
Hitoshi Mitake | df8bc08c | 2008-10-29 14:00:50 -0700 | [diff] [blame] | 170 | help |
| 171 | Support for error detection and correction on the Intel |
| 172 | X38 server chipsets. |
| 173 | |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 174 | config EDAC_I5400 |
| 175 | tristate "Intel 5400 (Seaburg) chipsets" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 176 | depends on PCI && X86 |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 177 | help |
| 178 | Support for error detection and correction the Intel |
| 179 | i5400 MCH chipset (Seaburg). |
| 180 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 181 | config EDAC_I7CORE |
| 182 | tristate "Intel i7 Core (Nehalem) processors" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 183 | depends on PCI && X86 && X86_MCE_INTEL |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 184 | help |
| 185 | Support for error detection and correction the Intel |
Mauro Carvalho Chehab | 696e409 | 2009-07-23 06:57:45 -0300 | [diff] [blame] | 186 | i7 Core (Nehalem) Integrated Memory Controller that exists on |
| 187 | newer processors like i7 Core, i7 Core Extreme, Xeon 35xx |
| 188 | and Xeon 55xx processors. |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 189 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 190 | config EDAC_I82860 |
| 191 | tristate "Intel 82860" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 192 | depends on PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 193 | help |
| 194 | Support for error detection and correction on the Intel |
| 195 | 82860 chipset. |
| 196 | |
| 197 | config EDAC_R82600 |
| 198 | tristate "Radisys 82600 embedded chipset" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 199 | depends on PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 200 | help |
| 201 | Support for error detection and correction on the Radisys |
| 202 | 82600 embedded chipset. |
| 203 | |
Eric Wollesen | eb60705 | 2007-07-19 01:49:39 -0700 | [diff] [blame] | 204 | config EDAC_I5000 |
| 205 | tristate "Intel Greencreek/Blackford chipset" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 206 | depends on X86 && PCI |
Eric Wollesen | eb60705 | 2007-07-19 01:49:39 -0700 | [diff] [blame] | 207 | help |
| 208 | Support for error detection and correction the Intel |
| 209 | Greekcreek/Blackford chipsets. |
| 210 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 211 | config EDAC_I5100 |
| 212 | tristate "Intel San Clemente MCH" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 213 | depends on X86 && PCI |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 214 | help |
| 215 | Support for error detection and correction the Intel |
| 216 | San Clemente MCH. |
| 217 | |
Mauro Carvalho Chehab | fcaf780 | 2010-08-24 23:22:57 -0300 | [diff] [blame] | 218 | config EDAC_I7300 |
| 219 | tristate "Intel Clarksboro MCH" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 220 | depends on X86 && PCI |
Mauro Carvalho Chehab | fcaf780 | 2010-08-24 23:22:57 -0300 | [diff] [blame] | 221 | help |
| 222 | Support for error detection and correction the Intel |
| 223 | Clarksboro MCH (Intel 7300 chipset). |
| 224 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 225 | config EDAC_SBRIDGE |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 226 | tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 227 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 228 | help |
| 229 | Support for error detection and correction the Intel |
Aristeu Rozanski | 50d1bb9 | 2014-06-20 10:27:54 -0300 | [diff] [blame] | 230 | Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 231 | |
Tony Luck | 4ec656b | 2016-08-20 16:27:58 -0700 | [diff] [blame] | 232 | config EDAC_SKX |
| 233 | tristate "Intel Skylake server Integrated MC" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 234 | depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG |
Tony Luck | 4ec656b | 2016-08-20 16:27:58 -0700 | [diff] [blame] | 235 | help |
| 236 | Support for error detection and correction the Intel |
| 237 | Skylake server Integrated Memory Controllers. |
| 238 | |
Tony Luck | 5c71ad1 | 2017-03-09 01:45:39 +0800 | [diff] [blame] | 239 | config EDAC_PND2 |
| 240 | tristate "Intel Pondicherry2" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 241 | depends on PCI && X86_64 && X86_MCE_INTEL |
Tony Luck | 5c71ad1 | 2017-03-09 01:45:39 +0800 | [diff] [blame] | 242 | help |
| 243 | Support for error detection and correction on the Intel |
| 244 | Pondicherry2 Integrated Memory Controller. This SoC IP is |
| 245 | first used on the Apollo Lake platform and Denverton |
| 246 | micro-server but may appear on others in the future. |
| 247 | |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 248 | config EDAC_MPC85XX |
Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 249 | tristate "Freescale MPC83xx / MPC85xx" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 250 | depends on FSL_SOC |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 251 | help |
| 252 | Support for error detection and correction on the Freescale |
York Sun | 7421026 | 2015-05-12 18:03:41 +0800 | [diff] [blame] | 253 | MPC8349, MPC8560, MPC8540, MPC8548, T4240 |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 254 | |
York Sun | eeb3d68 | 2016-08-23 15:14:03 -0700 | [diff] [blame] | 255 | config EDAC_LAYERSCAPE |
| 256 | tristate "Freescale Layerscape DDR" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 257 | depends on ARCH_LAYERSCAPE |
York Sun | eeb3d68 | 2016-08-23 15:14:03 -0700 | [diff] [blame] | 258 | help |
| 259 | Support for error detection and correction on Freescale memory |
| 260 | controllers on Layerscape SoCs. |
| 261 | |
Dave Jiang | 4f4aeea | 2008-02-07 00:14:56 -0800 | [diff] [blame] | 262 | config EDAC_MV64X60 |
| 263 | tristate "Marvell MV64x60" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 264 | depends on MV64X60 |
Dave Jiang | 4f4aeea | 2008-02-07 00:14:56 -0800 | [diff] [blame] | 265 | help |
| 266 | Support for error detection and correction on the Marvell |
| 267 | MV64360 and MV64460 chipsets. |
| 268 | |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 269 | config EDAC_PASEMI |
| 270 | tristate "PA Semi PWRficient" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 271 | depends on PPC_PASEMI && PCI |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 272 | help |
| 273 | Support for error detection and correction on PA Semi |
| 274 | PWRficient. |
| 275 | |
Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 276 | config EDAC_CELL |
| 277 | tristate "Cell Broadband Engine memory controller" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 278 | depends on PPC_CELL_COMMON |
Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 279 | help |
| 280 | Support for error detection and correction on the |
| 281 | Cell Broadband Engine internal memory controller |
| 282 | on platform without a hypervisor |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 283 | |
Grant Erickson | dba7a77 | 2009-04-02 16:58:45 -0700 | [diff] [blame] | 284 | config EDAC_PPC4XX |
| 285 | tristate "PPC4xx IBM DDR2 Memory Controller" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 286 | depends on 4xx |
Grant Erickson | dba7a77 | 2009-04-02 16:58:45 -0700 | [diff] [blame] | 287 | help |
| 288 | This enables support for EDAC on the ECC memory used |
| 289 | with the IBM DDR2 memory controller found in various |
| 290 | PowerPC 4xx embedded processors such as the 405EX[r], |
| 291 | 440SP, 440SPe, 460EX, 460GT and 460SX. |
| 292 | |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 293 | config EDAC_AMD8131 |
| 294 | tristate "AMD8131 HyperTransport PCI-X Tunnel" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 295 | depends on PCI && PPC_MAPLE |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 296 | help |
| 297 | Support for error detection and correction on the |
| 298 | AMD8131 HyperTransport PCI-X Tunnel chip. |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 299 | Note, add more Kconfig dependency if it's adopted |
| 300 | on some machine other than Maple. |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 301 | |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 302 | config EDAC_AMD8111 |
| 303 | tristate "AMD8111 HyperTransport I/O Hub" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 304 | depends on PCI && PPC_MAPLE |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 305 | help |
| 306 | Support for error detection and correction on the |
| 307 | AMD8111 HyperTransport I/O Hub chip. |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 308 | Note, add more Kconfig dependency if it's adopted |
| 309 | on some machine other than Maple. |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 310 | |
Harry Ciao | 2a9036a | 2009-06-17 16:27:58 -0700 | [diff] [blame] | 311 | config EDAC_CPC925 |
| 312 | tristate "IBM CPC925 Memory Controller (PPC970FX)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 313 | depends on PPC64 |
Harry Ciao | 2a9036a | 2009-06-17 16:27:58 -0700 | [diff] [blame] | 314 | help |
| 315 | Support for error detection and correction on the |
| 316 | IBM CPC925 Bridge and Memory Controller, which is |
| 317 | a companion chip to the PowerPC 970 family of |
| 318 | processors. |
| 319 | |
Chris Metcalf | 5c77075 | 2011-03-01 13:01:49 -0500 | [diff] [blame] | 320 | config EDAC_TILE |
| 321 | tristate "Tilera Memory Controller" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 322 | depends on TILE |
Chris Metcalf | 5c77075 | 2011-03-01 13:01:49 -0500 | [diff] [blame] | 323 | default y |
| 324 | help |
| 325 | Support for error detection and correction on the |
| 326 | Tilera memory controller. |
| 327 | |
Rob Herring | a1b01ed | 2012-06-13 12:01:55 -0500 | [diff] [blame] | 328 | config EDAC_HIGHBANK_MC |
| 329 | tristate "Highbank Memory Controller" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 330 | depends on ARCH_HIGHBANK |
Rob Herring | a1b01ed | 2012-06-13 12:01:55 -0500 | [diff] [blame] | 331 | help |
| 332 | Support for error detection and correction on the |
| 333 | Calxeda Highbank memory controller. |
| 334 | |
Rob Herring | 69154d0 | 2012-06-11 21:32:14 -0500 | [diff] [blame] | 335 | config EDAC_HIGHBANK_L2 |
| 336 | tristate "Highbank L2 Cache" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 337 | depends on ARCH_HIGHBANK |
Rob Herring | 69154d0 | 2012-06-11 21:32:14 -0500 | [diff] [blame] | 338 | help |
| 339 | Support for error detection and correction on the |
| 340 | Calxeda Highbank memory controller. |
| 341 | |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 342 | config EDAC_OCTEON_PC |
| 343 | tristate "Cavium Octeon Primary Caches" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 344 | depends on CPU_CAVIUM_OCTEON |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 345 | help |
| 346 | Support for error detection and correction on the primary caches of |
| 347 | the cnMIPS cores of Cavium Octeon family SOCs. |
| 348 | |
| 349 | config EDAC_OCTEON_L2C |
| 350 | tristate "Cavium Octeon Secondary Caches (L2C)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 351 | depends on CAVIUM_OCTEON_SOC |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 352 | help |
| 353 | Support for error detection and correction on the |
| 354 | Cavium Octeon family of SOCs. |
| 355 | |
| 356 | config EDAC_OCTEON_LMC |
| 357 | tristate "Cavium Octeon DRAM Memory Controller (LMC)" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 358 | depends on CAVIUM_OCTEON_SOC |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 359 | help |
| 360 | Support for error detection and correction on the |
| 361 | Cavium Octeon family of SOCs. |
| 362 | |
| 363 | config EDAC_OCTEON_PCI |
| 364 | tristate "Cavium Octeon PCI Controller" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 365 | depends on PCI && CAVIUM_OCTEON_SOC |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 366 | help |
| 367 | Support for error detection and correction on the |
| 368 | Cavium Octeon family of SOCs. |
| 369 | |
Sergey Temerkhanov | 4100339 | 2017-03-24 22:28:37 +0000 | [diff] [blame] | 370 | config EDAC_THUNDERX |
| 371 | tristate "Cavium ThunderX EDAC" |
Sergey Temerkhanov | 4100339 | 2017-03-24 22:28:37 +0000 | [diff] [blame] | 372 | depends on ARM64 |
| 373 | depends on PCI |
| 374 | help |
| 375 | Support for error detection and correction on the |
| 376 | Cavium ThunderX memory controllers (LMC), Cache |
| 377 | Coherent Processor Interconnect (CCPI) and L2 cache |
| 378 | blocks (TAD, CBC, MCI). |
| 379 | |
Thor Thayer | c3eea19 | 2016-02-10 13:26:21 -0600 | [diff] [blame] | 380 | config EDAC_ALTERA |
| 381 | bool "Altera SOCFPGA ECC" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 382 | depends on EDAC=y && ARCH_SOCFPGA |
Thor Thayer | 71bcada | 2014-09-03 10:27:54 -0500 | [diff] [blame] | 383 | help |
| 384 | Support for error detection and correction on the |
Thor Thayer | c3eea19 | 2016-02-10 13:26:21 -0600 | [diff] [blame] | 385 | Altera SOCs. This must be selected for SDRAM ECC. |
| 386 | Note that the preloader must initialize the SDRAM |
| 387 | before loading the kernel. |
| 388 | |
| 389 | config EDAC_ALTERA_L2C |
| 390 | bool "Altera L2 Cache ECC" |
Thor Thayer | 3a8f21f | 2016-03-21 11:01:38 -0500 | [diff] [blame] | 391 | depends on EDAC_ALTERA=y && CACHE_L2X0 |
Thor Thayer | c3eea19 | 2016-02-10 13:26:21 -0600 | [diff] [blame] | 392 | help |
| 393 | Support for error detection and correction on the |
| 394 | Altera L2 cache Memory for Altera SoCs. This option |
Thor Thayer | 3a8f21f | 2016-03-21 11:01:38 -0500 | [diff] [blame] | 395 | requires L2 cache. |
Thor Thayer | c3eea19 | 2016-02-10 13:26:21 -0600 | [diff] [blame] | 396 | |
| 397 | config EDAC_ALTERA_OCRAM |
| 398 | bool "Altera On-Chip RAM ECC" |
| 399 | depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR |
| 400 | help |
| 401 | Support for error detection and correction on the |
| 402 | Altera On-Chip RAM Memory for Altera SoCs. |
Thor Thayer | 71bcada | 2014-09-03 10:27:54 -0500 | [diff] [blame] | 403 | |
Thor Thayer | ab8c1e0 | 2016-06-22 08:58:58 -0500 | [diff] [blame] | 404 | config EDAC_ALTERA_ETHERNET |
| 405 | bool "Altera Ethernet FIFO ECC" |
| 406 | depends on EDAC_ALTERA=y |
| 407 | help |
| 408 | Support for error detection and correction on the |
| 409 | Altera Ethernet FIFO Memory for Altera SoCs. |
| 410 | |
Thor Thayer | c6882fb | 2016-07-14 11:06:43 -0500 | [diff] [blame] | 411 | config EDAC_ALTERA_NAND |
| 412 | bool "Altera NAND FIFO ECC" |
| 413 | depends on EDAC_ALTERA=y && MTD_NAND_DENALI |
| 414 | help |
| 415 | Support for error detection and correction on the |
| 416 | Altera NAND FIFO Memory for Altera SoCs. |
| 417 | |
Thor Thayer | e826379 | 2016-07-28 10:03:57 +0200 | [diff] [blame] | 418 | config EDAC_ALTERA_DMA |
| 419 | bool "Altera DMA FIFO ECC" |
| 420 | depends on EDAC_ALTERA=y && PL330_DMA=y |
| 421 | help |
| 422 | Support for error detection and correction on the |
| 423 | Altera DMA FIFO Memory for Altera SoCs. |
| 424 | |
Thor Thayer | c609581 | 2016-07-14 11:06:45 -0500 | [diff] [blame] | 425 | config EDAC_ALTERA_USB |
| 426 | bool "Altera USB FIFO ECC" |
| 427 | depends on EDAC_ALTERA=y && USB_DWC2 |
| 428 | help |
| 429 | Support for error detection and correction on the |
| 430 | Altera USB FIFO Memory for Altera SoCs. |
| 431 | |
Thor Thayer | 485fe9e | 2016-07-14 11:06:46 -0500 | [diff] [blame] | 432 | config EDAC_ALTERA_QSPI |
| 433 | bool "Altera QSPI FIFO ECC" |
| 434 | depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI |
| 435 | help |
| 436 | Support for error detection and correction on the |
| 437 | Altera QSPI FIFO Memory for Altera SoCs. |
| 438 | |
Thor Thayer | 9110498 | 2016-08-09 09:40:52 -0500 | [diff] [blame] | 439 | config EDAC_ALTERA_SDMMC |
| 440 | bool "Altera SDMMC FIFO ECC" |
| 441 | depends on EDAC_ALTERA=y && MMC_DW |
| 442 | help |
| 443 | Support for error detection and correction on the |
| 444 | Altera SDMMC FIFO Memory for Altera SoCs. |
| 445 | |
Punnaiah Choudary Kalluri | ae9b56e | 2015-01-06 23:13:47 +0530 | [diff] [blame] | 446 | config EDAC_SYNOPSYS |
| 447 | tristate "Synopsys DDR Memory Controller" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 448 | depends on ARCH_ZYNQ |
Punnaiah Choudary Kalluri | ae9b56e | 2015-01-06 23:13:47 +0530 | [diff] [blame] | 449 | help |
| 450 | Support for error detection and correction on the Synopsys DDR |
| 451 | memory controller. |
| 452 | |
Loc Ho | 0d44293 | 2015-05-22 17:32:59 -0600 | [diff] [blame] | 453 | config EDAC_XGENE |
| 454 | tristate "APM X-Gene SoC" |
Borislav Petkov | e3c4ff6 | 2017-02-03 18:18:05 +0100 | [diff] [blame] | 455 | depends on (ARM64 || COMPILE_TEST) |
Loc Ho | 0d44293 | 2015-05-22 17:32:59 -0600 | [diff] [blame] | 456 | help |
| 457 | Support for error detection and correction on the |
| 458 | APM X-Gene family of SOCs. |
| 459 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 460 | endif # EDAC |