blob: ff380dac6629d16f4d3642f9ed6789ec2da7f2ab [file] [log] [blame]
Mugunthan V Ndf828592012-03-18 20:17:54 +00001/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
Richard Cochran2e5b38a2012-10-29 08:45:20 +000027#include <linux/net_tstamp.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000028#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
Mugunthan V Nf150bd72012-07-17 08:09:50 +000031#include <linux/pm_runtime.h>
Mugunthan V N2eb32b02012-07-30 10:17:14 +000032#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
Mugunthan V N3b72c2f2013-02-05 08:26:48 +000035#include <linux/if_vlan.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000036
Mugunthan V N739683b2013-06-06 23:45:14 +053037#include <linux/pinctrl/consumer.h>
Mugunthan V Ndf828592012-03-18 20:17:54 +000038
Mugunthan V Ndbe34722013-08-19 17:47:40 +053039#include "cpsw.h"
Mugunthan V Ndf828592012-03-18 20:17:54 +000040#include "cpsw_ale.h"
Richard Cochran2e5b38a2012-10-29 08:45:20 +000041#include "cpts.h"
Mugunthan V Ndf828592012-03-18 20:17:54 +000042#include "davinci_cpdma.h"
43
44#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
51 NETIF_MSG_RX_STATUS)
52
53#define cpsw_info(priv, type, format, ...) \
54do { \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
57} while (0)
58
59#define cpsw_err(priv, type, format, ...) \
60do { \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
63} while (0)
64
65#define cpsw_dbg(priv, type, format, ...) \
66do { \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
69} while (0)
70
71#define cpsw_notice(priv, type, format, ...) \
72do { \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
75} while (0)
76
Mugunthan V N5c50a852012-10-29 08:45:11 +000077#define ALE_ALL_PORTS 0x7
78
Mugunthan V Ndf828592012-03-18 20:17:54 +000079#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
82
Richard Cochrane90cfac2012-10-29 08:45:14 +000083#define CPSW_VERSION_1 0x19010a
84#define CPSW_VERSION_2 0x19010c
Mugunthan V Nc193f362013-08-05 17:30:05 +053085#define CPSW_VERSION_3 0x19010f
Mugunthan V N926489b2013-08-12 17:11:15 +053086#define CPSW_VERSION_4 0x190112
Richard Cochran549985e2012-11-14 09:07:56 +000087
88#define HOST_PORT_NUM 0
89#define SLIVER_SIZE 0x40
90
91#define CPSW1_HOST_PORT_OFFSET 0x028
92#define CPSW1_SLAVE_OFFSET 0x050
93#define CPSW1_SLAVE_SIZE 0x040
94#define CPSW1_CPDMA_OFFSET 0x100
95#define CPSW1_STATERAM_OFFSET 0x200
Mugunthan V Nd9718542013-07-23 15:38:17 +053096#define CPSW1_HW_STATS 0x400
Richard Cochran549985e2012-11-14 09:07:56 +000097#define CPSW1_CPTS_OFFSET 0x500
98#define CPSW1_ALE_OFFSET 0x600
99#define CPSW1_SLIVER_OFFSET 0x700
100
101#define CPSW2_HOST_PORT_OFFSET 0x108
102#define CPSW2_SLAVE_OFFSET 0x200
103#define CPSW2_SLAVE_SIZE 0x100
104#define CPSW2_CPDMA_OFFSET 0x800
Mugunthan V Nd9718542013-07-23 15:38:17 +0530105#define CPSW2_HW_STATS 0x900
Richard Cochran549985e2012-11-14 09:07:56 +0000106#define CPSW2_STATERAM_OFFSET 0xa00
107#define CPSW2_CPTS_OFFSET 0xc00
108#define CPSW2_ALE_OFFSET 0xd00
109#define CPSW2_SLIVER_OFFSET 0xd80
110#define CPSW2_BD_OFFSET 0x2000
111
Mugunthan V Ndf828592012-03-18 20:17:54 +0000112#define CPDMA_RXTHRESH 0x0c0
113#define CPDMA_RXFREE 0x0e0
114#define CPDMA_TXHDP 0x00
115#define CPDMA_RXHDP 0x20
116#define CPDMA_TXCP 0x40
117#define CPDMA_RXCP 0x60
118
Mugunthan V Ndf828592012-03-18 20:17:54 +0000119#define CPSW_POLL_WEIGHT 64
120#define CPSW_MIN_PACKET_SIZE 60
121#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
122
123#define RX_PRIORITY_MAPPING 0x76543210
124#define TX_PRIORITY_MAPPING 0x33221100
125#define CPDMA_TX_PRIORITY_MAP 0x76543210
126
Mugunthan V N3b72c2f2013-02-05 08:26:48 +0000127#define CPSW_VLAN_AWARE BIT(1)
128#define CPSW_ALE_VLAN_AWARE 1
129
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000130#define CPSW_FIFO_NORMAL_MODE (0 << 15)
131#define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
132#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
133
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000134#define CPSW_INTPACEEN (0x3f << 16)
135#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
136#define CPSW_CMINTMAX_CNT 63
137#define CPSW_CMINTMIN_CNT 2
138#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
139#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
140
Mugunthan V Ndf828592012-03-18 20:17:54 +0000141#define cpsw_enable_irq(priv) \
142 do { \
143 u32 i; \
144 for (i = 0; i < priv->num_irqs; i++) \
145 enable_irq(priv->irqs_table[i]); \
Joe Perches5f47dfb2014-05-14 12:15:13 -0700146 } while (0)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000147#define cpsw_disable_irq(priv) \
148 do { \
149 u32 i; \
150 for (i = 0; i < priv->num_irqs; i++) \
151 disable_irq_nosync(priv->irqs_table[i]); \
Joe Perches5f47dfb2014-05-14 12:15:13 -0700152 } while (0)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000153
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +0000154#define cpsw_slave_index(priv) \
155 ((priv->data.dual_emac) ? priv->emac_port : \
156 priv->data.active_slave)
157
Mugunthan V Ndf828592012-03-18 20:17:54 +0000158static int debug_level;
159module_param(debug_level, int, 0);
160MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
161
162static int ale_ageout = 10;
163module_param(ale_ageout, int, 0);
164MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
165
166static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
167module_param(rx_packet_max, int, 0);
168MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
169
Richard Cochran996a5c22012-10-29 08:45:12 +0000170struct cpsw_wr_regs {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000171 u32 id_ver;
172 u32 soft_reset;
173 u32 control;
174 u32 int_control;
175 u32 rx_thresh_en;
176 u32 rx_en;
177 u32 tx_en;
178 u32 misc_en;
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000179 u32 mem_allign1[8];
180 u32 rx_thresh_stat;
181 u32 rx_stat;
182 u32 tx_stat;
183 u32 misc_stat;
184 u32 mem_allign2[8];
185 u32 rx_imax;
186 u32 tx_imax;
187
Mugunthan V Ndf828592012-03-18 20:17:54 +0000188};
189
Richard Cochran996a5c22012-10-29 08:45:12 +0000190struct cpsw_ss_regs {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000191 u32 id_ver;
192 u32 control;
193 u32 soft_reset;
194 u32 stat_port_en;
195 u32 ptype;
Richard Cochranbd357af2012-10-29 08:45:13 +0000196 u32 soft_idle;
197 u32 thru_rate;
198 u32 gap_thresh;
199 u32 tx_start_wds;
200 u32 flow_control;
201 u32 vlan_ltype;
202 u32 ts_ltype;
203 u32 dlr_ltype;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000204};
205
Richard Cochran9750a3a2012-10-29 08:45:15 +0000206/* CPSW_PORT_V1 */
207#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
208#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
209#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
210#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
211#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
213#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
214#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
215
216/* CPSW_PORT_V2 */
217#define CPSW2_CONTROL 0x00 /* Control Register */
218#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
219#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
220#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
221#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
222#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
223#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
224
225/* CPSW_PORT_V1 and V2 */
226#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
227#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
228#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
229
230/* CPSW_PORT_V2 only */
231#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
236#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
237#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
238#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
239
240/* Bit definitions for the CPSW2_CONTROL register */
241#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
242#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
243#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
244#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
245#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
246#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
247#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
248#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
249#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
250#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
George Cherian09c55372014-05-02 12:02:02 +0530251#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
252#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
Richard Cochran9750a3a2012-10-29 08:45:15 +0000253#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
254#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
255#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
256#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
257#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
258
George Cherian09c55372014-05-02 12:02:02 +0530259#define CTRL_V2_TS_BITS \
260 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
Richard Cochran9750a3a2012-10-29 08:45:15 +0000262
George Cherian09c55372014-05-02 12:02:02 +0530263#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
264#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
265#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
266
267
268#define CTRL_V3_TS_BITS \
269 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
270 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
271 TS_LTYPE1_EN)
272
273#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
274#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
275#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
Richard Cochran9750a3a2012-10-29 08:45:15 +0000276
277/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
278#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
279#define TS_SEQ_ID_OFFSET_MASK (0x3f)
280#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
281#define TS_MSG_TYPE_EN_MASK (0xffff)
282
283/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
284#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
Mugunthan V Ndf828592012-03-18 20:17:54 +0000285
Richard Cochran2e5b38a2012-10-29 08:45:20 +0000286/* Bit definitions for the CPSW1_TS_CTL register */
287#define CPSW_V1_TS_RX_EN BIT(0)
288#define CPSW_V1_TS_TX_EN BIT(4)
289#define CPSW_V1_MSG_TYPE_OFS 16
290
291/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
292#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
293
Mugunthan V Ndf828592012-03-18 20:17:54 +0000294struct cpsw_host_regs {
295 u32 max_blks;
296 u32 blk_cnt;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000297 u32 tx_in_ctl;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000298 u32 port_vlan;
299 u32 tx_pri_map;
300 u32 cpdma_tx_pri_map;
301 u32 cpdma_rx_chan_map;
302};
303
304struct cpsw_sliver_regs {
305 u32 id_ver;
306 u32 mac_control;
307 u32 mac_status;
308 u32 soft_reset;
309 u32 rx_maxlen;
310 u32 __reserved_0;
311 u32 rx_pause;
312 u32 tx_pause;
313 u32 __reserved_1;
314 u32 rx_pri_map;
315};
316
Mugunthan V Nd9718542013-07-23 15:38:17 +0530317struct cpsw_hw_stats {
318 u32 rxgoodframes;
319 u32 rxbroadcastframes;
320 u32 rxmulticastframes;
321 u32 rxpauseframes;
322 u32 rxcrcerrors;
323 u32 rxaligncodeerrors;
324 u32 rxoversizedframes;
325 u32 rxjabberframes;
326 u32 rxundersizedframes;
327 u32 rxfragments;
328 u32 __pad_0[2];
329 u32 rxoctets;
330 u32 txgoodframes;
331 u32 txbroadcastframes;
332 u32 txmulticastframes;
333 u32 txpauseframes;
334 u32 txdeferredframes;
335 u32 txcollisionframes;
336 u32 txsinglecollframes;
337 u32 txmultcollframes;
338 u32 txexcessivecollisions;
339 u32 txlatecollisions;
340 u32 txunderrun;
341 u32 txcarriersenseerrors;
342 u32 txoctets;
343 u32 octetframes64;
344 u32 octetframes65t127;
345 u32 octetframes128t255;
346 u32 octetframes256t511;
347 u32 octetframes512t1023;
348 u32 octetframes1024tup;
349 u32 netoctets;
350 u32 rxsofoverruns;
351 u32 rxmofoverruns;
352 u32 rxdmaoverruns;
353};
354
Mugunthan V Ndf828592012-03-18 20:17:54 +0000355struct cpsw_slave {
Richard Cochran9750a3a2012-10-29 08:45:15 +0000356 void __iomem *regs;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000357 struct cpsw_sliver_regs __iomem *sliver;
358 int slave_num;
359 u32 mac_control;
360 struct cpsw_slave_data *data;
361 struct phy_device *phy;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000362 struct net_device *ndev;
363 u32 port_vlan;
364 u32 open_stat;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000365};
366
Richard Cochran9750a3a2012-10-29 08:45:15 +0000367static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
368{
369 return __raw_readl(slave->regs + offset);
370}
371
372static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
373{
374 __raw_writel(val, slave->regs + offset);
375}
376
Mugunthan V Ndf828592012-03-18 20:17:54 +0000377struct cpsw_priv {
378 spinlock_t lock;
379 struct platform_device *pdev;
380 struct net_device *ndev;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000381 struct napi_struct napi;
382 struct device *dev;
383 struct cpsw_platform_data data;
Richard Cochran996a5c22012-10-29 08:45:12 +0000384 struct cpsw_ss_regs __iomem *regs;
385 struct cpsw_wr_regs __iomem *wr_regs;
Mugunthan V Nd9718542013-07-23 15:38:17 +0530386 u8 __iomem *hw_stats;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000387 struct cpsw_host_regs __iomem *host_port_regs;
388 u32 msg_enable;
Richard Cochrane90cfac2012-10-29 08:45:14 +0000389 u32 version;
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000390 u32 coal_intvl;
391 u32 bus_freq_mhz;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000392 int rx_packet_max;
393 int host_port;
394 struct clk *clk;
395 u8 mac_addr[ETH_ALEN];
396 struct cpsw_slave *slaves;
397 struct cpdma_ctlr *dma;
398 struct cpdma_chan *txch, *rxch;
399 struct cpsw_ale *ale;
400 /* snapshot of IRQ numbers */
401 u32 irqs_table[4];
402 u32 num_irqs;
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000403 bool irq_enabled;
Mugunthan V N9232b162013-02-11 09:52:19 +0000404 struct cpts *cpts;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000405 u32 emac_port;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000406};
407
Mugunthan V Nd9718542013-07-23 15:38:17 +0530408struct cpsw_stats {
409 char stat_string[ETH_GSTRING_LEN];
410 int type;
411 int sizeof_stat;
412 int stat_offset;
413};
414
415enum {
416 CPSW_STATS,
417 CPDMA_RX_STATS,
418 CPDMA_TX_STATS,
419};
420
421#define CPSW_STAT(m) CPSW_STATS, \
422 sizeof(((struct cpsw_hw_stats *)0)->m), \
423 offsetof(struct cpsw_hw_stats, m)
424#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
425 sizeof(((struct cpdma_chan_stats *)0)->m), \
426 offsetof(struct cpdma_chan_stats, m)
427#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
428 sizeof(((struct cpdma_chan_stats *)0)->m), \
429 offsetof(struct cpdma_chan_stats, m)
430
431static const struct cpsw_stats cpsw_gstrings_stats[] = {
432 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
433 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
434 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
435 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
436 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
437 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
438 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
439 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
440 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
441 { "Rx Fragments", CPSW_STAT(rxfragments) },
442 { "Rx Octets", CPSW_STAT(rxoctets) },
443 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
444 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
445 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
446 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
447 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
448 { "Collisions", CPSW_STAT(txcollisionframes) },
449 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
450 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
451 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
452 { "Late Collisions", CPSW_STAT(txlatecollisions) },
453 { "Tx Underrun", CPSW_STAT(txunderrun) },
454 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
455 { "Tx Octets", CPSW_STAT(txoctets) },
456 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
457 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
458 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
459 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
460 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
461 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
462 { "Net Octets", CPSW_STAT(netoctets) },
463 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
464 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
465 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
466 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
467 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
468 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
469 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
470 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
471 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
472 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
473 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
474 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
475 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
476 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
477 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
478 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
479 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
480 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
481 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
482 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
483 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
484 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
485 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
486 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
487 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
488 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
489 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
490 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
491 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
492};
493
494#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
495
Mugunthan V Ndf828592012-03-18 20:17:54 +0000496#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000497#define for_each_slave(priv, func, arg...) \
498 do { \
Sebastian Siewior6e6ceae2013-04-24 08:48:24 +0000499 struct cpsw_slave *slave; \
500 int n; \
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000501 if (priv->data.dual_emac) \
502 (func)((priv)->slaves + priv->emac_port, ##arg);\
503 else \
Sebastian Siewior6e6ceae2013-04-24 08:48:24 +0000504 for (n = (priv)->data.slaves, \
505 slave = (priv)->slaves; \
506 n; n--) \
507 (func)(slave++, ##arg); \
Mugunthan V Ndf828592012-03-18 20:17:54 +0000508 } while (0)
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000509#define cpsw_get_slave_ndev(priv, __slave_no__) \
510 (priv->slaves[__slave_no__].ndev)
511#define cpsw_get_slave_priv(priv, __slave_no__) \
512 ((priv->slaves[__slave_no__].ndev) ? \
513 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
514
515#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
516 do { \
517 if (!priv->data.dual_emac) \
518 break; \
519 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
520 ndev = cpsw_get_slave_ndev(priv, 0); \
521 priv = netdev_priv(ndev); \
522 skb->dev = ndev; \
523 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
524 ndev = cpsw_get_slave_ndev(priv, 1); \
525 priv = netdev_priv(ndev); \
526 skb->dev = ndev; \
527 } \
528 } while (0)
529#define cpsw_add_mcast(priv, addr) \
530 do { \
531 if (priv->data.dual_emac) { \
532 struct cpsw_slave *slave = priv->slaves + \
533 priv->emac_port; \
534 int slave_port = cpsw_get_slave_port(priv, \
535 slave->slave_num); \
536 cpsw_ale_add_mcast(priv->ale, addr, \
537 1 << slave_port | 1 << priv->host_port, \
538 ALE_VLAN, slave->port_vlan, 0); \
539 } else { \
540 cpsw_ale_add_mcast(priv->ale, addr, \
541 ALE_ALL_PORTS << priv->host_port, \
542 0, 0, 0); \
543 } \
544 } while (0)
545
546static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
547{
548 if (priv->host_port == 0)
549 return slave_num + 1;
550 else
551 return slave_num;
552}
Mugunthan V Ndf828592012-03-18 20:17:54 +0000553
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530554static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
555{
556 struct cpsw_priv *priv = netdev_priv(ndev);
557 struct cpsw_ale *ale = priv->ale;
558 int i;
559
560 if (priv->data.dual_emac) {
561 bool flag = false;
562
563 /* Enabling promiscuous mode for one interface will be
564 * common for both the interface as the interface shares
565 * the same hardware resource.
566 */
Heiko Schocher0d961b32014-02-13 14:47:27 +0100567 for (i = 0; i < priv->data.slaves; i++)
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530568 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
569 flag = true;
570
571 if (!enable && flag) {
572 enable = true;
573 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
574 }
575
576 if (enable) {
577 /* Enable Bypass */
578 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
579
580 dev_dbg(&ndev->dev, "promiscuity enabled\n");
581 } else {
582 /* Disable Bypass */
583 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
584 dev_dbg(&ndev->dev, "promiscuity disabled\n");
585 }
586 } else {
587 if (enable) {
588 unsigned long timeout = jiffies + HZ;
589
590 /* Disable Learn for all ports */
Heiko Schocher0d961b32014-02-13 14:47:27 +0100591 for (i = 0; i < priv->data.slaves; i++) {
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530592 cpsw_ale_control_set(ale, i,
593 ALE_PORT_NOLEARN, 1);
594 cpsw_ale_control_set(ale, i,
595 ALE_PORT_NO_SA_UPDATE, 1);
596 }
597
598 /* Clear All Untouched entries */
599 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
600 do {
601 cpu_relax();
602 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
603 break;
604 } while (time_after(timeout, jiffies));
605 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
606
607 /* Clear all mcast from ALE */
608 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
609 priv->host_port);
610
611 /* Flood All Unicast Packets to Host port */
612 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
613 dev_dbg(&ndev->dev, "promiscuity enabled\n");
614 } else {
615 /* Flood All Unicast Packets to Host port */
616 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
617
618 /* Enable Learn for all ports */
Heiko Schocher0d961b32014-02-13 14:47:27 +0100619 for (i = 0; i < priv->data.slaves; i++) {
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530620 cpsw_ale_control_set(ale, i,
621 ALE_PORT_NOLEARN, 0);
622 cpsw_ale_control_set(ale, i,
623 ALE_PORT_NO_SA_UPDATE, 0);
624 }
625 dev_dbg(&ndev->dev, "promiscuity disabled\n");
626 }
627 }
628}
629
Mugunthan V N5c50a852012-10-29 08:45:11 +0000630static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
631{
632 struct cpsw_priv *priv = netdev_priv(ndev);
633
634 if (ndev->flags & IFF_PROMISC) {
635 /* Enable promiscuous mode */
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530636 cpsw_set_promiscious(ndev, true);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000637 return;
Mugunthan V N0cd8f9c2014-01-23 00:03:12 +0530638 } else {
639 /* Disable promiscuous mode */
640 cpsw_set_promiscious(ndev, false);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000641 }
642
643 /* Clear all mcast from ALE */
644 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
645
646 if (!netdev_mc_empty(ndev)) {
647 struct netdev_hw_addr *ha;
648
649 /* program multicast address list into ALE register */
650 netdev_for_each_mc_addr(ha, ndev) {
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000651 cpsw_add_mcast(priv, (u8 *)ha->addr);
Mugunthan V N5c50a852012-10-29 08:45:11 +0000652 }
653 }
654}
655
Mugunthan V Ndf828592012-03-18 20:17:54 +0000656static void cpsw_intr_enable(struct cpsw_priv *priv)
657{
Richard Cochran996a5c22012-10-29 08:45:12 +0000658 __raw_writel(0xFF, &priv->wr_regs->tx_en);
659 __raw_writel(0xFF, &priv->wr_regs->rx_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000660
661 cpdma_ctlr_int_ctrl(priv->dma, true);
662 return;
663}
664
665static void cpsw_intr_disable(struct cpsw_priv *priv)
666{
Richard Cochran996a5c22012-10-29 08:45:12 +0000667 __raw_writel(0, &priv->wr_regs->tx_en);
668 __raw_writel(0, &priv->wr_regs->rx_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000669
670 cpdma_ctlr_int_ctrl(priv->dma, false);
671 return;
672}
673
Olof Johansson1a3b5052013-12-11 15:58:07 -0800674static void cpsw_tx_handler(void *token, int len, int status)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000675{
676 struct sk_buff *skb = token;
677 struct net_device *ndev = skb->dev;
678 struct cpsw_priv *priv = netdev_priv(ndev);
679
Mugunthan V Nfae50822013-01-17 06:31:34 +0000680 /* Check whether the queue is stopped due to stalled tx dma, if the
681 * queue is stopped then start the queue as we have free desc for tx
682 */
Mugunthan V Ndf828592012-03-18 20:17:54 +0000683 if (unlikely(netif_queue_stopped(ndev)))
Mugunthan V Nb56d6b3f2013-03-27 04:41:59 +0000684 netif_wake_queue(ndev);
Mugunthan V N9232b162013-02-11 09:52:19 +0000685 cpts_tx_timestamp(priv->cpts, skb);
Tobias Klauser8dc43dd2014-03-10 13:12:23 +0100686 ndev->stats.tx_packets++;
687 ndev->stats.tx_bytes += len;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000688 dev_kfree_skb_any(skb);
689}
690
Olof Johansson1a3b5052013-12-11 15:58:07 -0800691static void cpsw_rx_handler(void *token, int len, int status)
Mugunthan V Ndf828592012-03-18 20:17:54 +0000692{
693 struct sk_buff *skb = token;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000694 struct sk_buff *new_skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000695 struct net_device *ndev = skb->dev;
696 struct cpsw_priv *priv = netdev_priv(ndev);
697 int ret = 0;
698
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +0000699 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
700
Mugunthan V N16e5c572014-04-10 14:23:23 +0530701 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000702 /* the interface is going down, skbs are purged */
Mugunthan V Ndf828592012-03-18 20:17:54 +0000703 dev_kfree_skb_any(skb);
704 return;
705 }
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000706
707 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
708 if (new_skb) {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000709 skb_put(skb, len);
Mugunthan V N9232b162013-02-11 09:52:19 +0000710 cpts_rx_timestamp(priv->cpts, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000711 skb->protocol = eth_type_trans(skb, ndev);
712 netif_receive_skb(skb);
Tobias Klauser8dc43dd2014-03-10 13:12:23 +0100713 ndev->stats.rx_bytes += len;
714 ndev->stats.rx_packets++;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000715 } else {
Tobias Klauser8dc43dd2014-03-10 13:12:23 +0100716 ndev->stats.rx_dropped++;
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000717 new_skb = skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000718 }
719
Sebastian Siewiorb4727e62013-04-23 07:31:39 +0000720 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
721 skb_tailroom(new_skb), 0);
722 if (WARN_ON(ret < 0))
723 dev_kfree_skb_any(new_skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000724}
725
726static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
727{
728 struct cpsw_priv *priv = dev_id;
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000729
730 cpsw_intr_disable(priv);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000731 if (priv->irq_enabled == true) {
732 cpsw_disable_irq(priv);
733 priv->irq_enabled = false;
734 }
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000735
736 if (netif_running(priv->ndev)) {
Mugunthan V Ndf828592012-03-18 20:17:54 +0000737 napi_schedule(&priv->napi);
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000738 return IRQ_HANDLED;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000739 }
Sebastian Siewiorfd51cf12013-04-23 07:31:37 +0000740
741 priv = cpsw_get_slave_priv(priv, 1);
742 if (!priv)
743 return IRQ_NONE;
744
745 if (netif_running(priv->ndev)) {
746 napi_schedule(&priv->napi);
747 return IRQ_HANDLED;
748 }
749 return IRQ_NONE;
Mugunthan V Ndf828592012-03-18 20:17:54 +0000750}
751
Mugunthan V Ndf828592012-03-18 20:17:54 +0000752static int cpsw_poll(struct napi_struct *napi, int budget)
753{
754 struct cpsw_priv *priv = napi_to_priv(napi);
755 int num_tx, num_rx;
756
757 num_tx = cpdma_chan_process(priv->txch, 128);
Mugunthan V N510a1e722013-02-17 22:19:20 +0000758 if (num_tx)
759 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
760
Mugunthan V Ndf828592012-03-18 20:17:54 +0000761 num_rx = cpdma_chan_process(priv->rxch, budget);
Mugunthan V N510a1e722013-02-17 22:19:20 +0000762 if (num_rx < budget) {
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000763 struct cpsw_priv *prim_cpsw;
764
Mugunthan V N510a1e722013-02-17 22:19:20 +0000765 napi_complete(napi);
766 cpsw_intr_enable(priv);
767 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000768 prim_cpsw = cpsw_get_slave_priv(priv, 0);
769 if (prim_cpsw->irq_enabled == false) {
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000770 prim_cpsw->irq_enabled = true;
Mugunthan V Naf5c6df2013-05-02 01:52:11 +0000771 cpsw_enable_irq(priv);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +0000772 }
Mugunthan V N510a1e722013-02-17 22:19:20 +0000773 }
Mugunthan V Ndf828592012-03-18 20:17:54 +0000774
775 if (num_rx || num_tx)
776 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
777 num_rx, num_tx);
778
Mugunthan V Ndf828592012-03-18 20:17:54 +0000779 return num_rx;
780}
781
782static inline void soft_reset(const char *module, void __iomem *reg)
783{
784 unsigned long timeout = jiffies + HZ;
785
786 __raw_writel(1, reg);
787 do {
788 cpu_relax();
789 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
790
791 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
792}
793
794#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
795 ((mac)[2] << 16) | ((mac)[3] << 24))
796#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
797
798static void cpsw_set_slave_mac(struct cpsw_slave *slave,
799 struct cpsw_priv *priv)
800{
Richard Cochran9750a3a2012-10-29 08:45:15 +0000801 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
802 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
Mugunthan V Ndf828592012-03-18 20:17:54 +0000803}
804
805static void _cpsw_adjust_link(struct cpsw_slave *slave,
806 struct cpsw_priv *priv, bool *link)
807{
808 struct phy_device *phy = slave->phy;
809 u32 mac_control = 0;
810 u32 slave_port;
811
812 if (!phy)
813 return;
814
815 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
816
817 if (phy->link) {
818 mac_control = priv->data.mac_control;
819
820 /* enable forwarding */
821 cpsw_ale_control_set(priv->ale, slave_port,
822 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
823
824 if (phy->speed == 1000)
825 mac_control |= BIT(7); /* GIGABITEN */
826 if (phy->duplex)
827 mac_control |= BIT(0); /* FULLDUPLEXEN */
Daniel Mack342b7b72012-09-27 09:19:34 +0000828
829 /* set speed_in input in case RMII mode is used in 100Mbps */
830 if (phy->speed == 100)
831 mac_control |= BIT(15);
Mugunthan V Na81d8762013-12-13 18:42:55 +0530832 else if (phy->speed == 10)
833 mac_control |= BIT(18); /* In Band mode */
Daniel Mack342b7b72012-09-27 09:19:34 +0000834
Mugunthan V Ndf828592012-03-18 20:17:54 +0000835 *link = true;
836 } else {
837 mac_control = 0;
838 /* disable forwarding */
839 cpsw_ale_control_set(priv->ale, slave_port,
840 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
841 }
842
843 if (mac_control != slave->mac_control) {
844 phy_print_status(phy);
845 __raw_writel(mac_control, &slave->sliver->mac_control);
846 }
847
848 slave->mac_control = mac_control;
849}
850
851static void cpsw_adjust_link(struct net_device *ndev)
852{
853 struct cpsw_priv *priv = netdev_priv(ndev);
854 bool link = false;
855
856 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
857
858 if (link) {
859 netif_carrier_on(ndev);
860 if (netif_running(ndev))
861 netif_wake_queue(ndev);
862 } else {
863 netif_carrier_off(ndev);
864 netif_stop_queue(ndev);
865 }
866}
867
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +0000868static int cpsw_get_coalesce(struct net_device *ndev,
869 struct ethtool_coalesce *coal)
870{
871 struct cpsw_priv *priv = netdev_priv(ndev);
872
873 coal->rx_coalesce_usecs = priv->coal_intvl;
874 return 0;
875}
876
877static int cpsw_set_coalesce(struct net_device *ndev,
878 struct ethtool_coalesce *coal)
879{
880 struct cpsw_priv *priv = netdev_priv(ndev);
881 u32 int_ctrl;
882 u32 num_interrupts = 0;
883 u32 prescale = 0;
884 u32 addnl_dvdr = 1;
885 u32 coal_intvl = 0;
886
887 if (!coal->rx_coalesce_usecs)
888 return -EINVAL;
889
890 coal_intvl = coal->rx_coalesce_usecs;
891
892 int_ctrl = readl(&priv->wr_regs->int_control);
893 prescale = priv->bus_freq_mhz * 4;
894
895 if (coal_intvl < CPSW_CMINTMIN_INTVL)
896 coal_intvl = CPSW_CMINTMIN_INTVL;
897
898 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
899 /* Interrupt pacer works with 4us Pulse, we can
900 * throttle further by dilating the 4us pulse.
901 */
902 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
903
904 if (addnl_dvdr > 1) {
905 prescale *= addnl_dvdr;
906 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
907 coal_intvl = (CPSW_CMINTMAX_INTVL
908 * addnl_dvdr);
909 } else {
910 addnl_dvdr = 1;
911 coal_intvl = CPSW_CMINTMAX_INTVL;
912 }
913 }
914
915 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
916 writel(num_interrupts, &priv->wr_regs->rx_imax);
917 writel(num_interrupts, &priv->wr_regs->tx_imax);
918
919 int_ctrl |= CPSW_INTPACEEN;
920 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
921 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
922 writel(int_ctrl, &priv->wr_regs->int_control);
923
924 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
925 if (priv->data.dual_emac) {
926 int i;
927
928 for (i = 0; i < priv->data.slaves; i++) {
929 priv = netdev_priv(priv->slaves[i].ndev);
930 priv->coal_intvl = coal_intvl;
931 }
932 } else {
933 priv->coal_intvl = coal_intvl;
934 }
935
936 return 0;
937}
938
Mugunthan V Nd9718542013-07-23 15:38:17 +0530939static int cpsw_get_sset_count(struct net_device *ndev, int sset)
940{
941 switch (sset) {
942 case ETH_SS_STATS:
943 return CPSW_STATS_LEN;
944 default:
945 return -EOPNOTSUPP;
946 }
947}
948
949static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
950{
951 u8 *p = data;
952 int i;
953
954 switch (stringset) {
955 case ETH_SS_STATS:
956 for (i = 0; i < CPSW_STATS_LEN; i++) {
957 memcpy(p, cpsw_gstrings_stats[i].stat_string,
958 ETH_GSTRING_LEN);
959 p += ETH_GSTRING_LEN;
960 }
961 break;
962 }
963}
964
965static void cpsw_get_ethtool_stats(struct net_device *ndev,
966 struct ethtool_stats *stats, u64 *data)
967{
968 struct cpsw_priv *priv = netdev_priv(ndev);
969 struct cpdma_chan_stats rx_stats;
970 struct cpdma_chan_stats tx_stats;
971 u32 val;
972 u8 *p;
973 int i;
974
975 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
976 cpdma_chan_get_stats(priv->rxch, &rx_stats);
977 cpdma_chan_get_stats(priv->txch, &tx_stats);
978
979 for (i = 0; i < CPSW_STATS_LEN; i++) {
980 switch (cpsw_gstrings_stats[i].type) {
981 case CPSW_STATS:
982 val = readl(priv->hw_stats +
983 cpsw_gstrings_stats[i].stat_offset);
984 data[i] = val;
985 break;
986
987 case CPDMA_RX_STATS:
988 p = (u8 *)&rx_stats +
989 cpsw_gstrings_stats[i].stat_offset;
990 data[i] = *(u32 *)p;
991 break;
992
993 case CPDMA_TX_STATS:
994 p = (u8 *)&tx_stats +
995 cpsw_gstrings_stats[i].stat_offset;
996 data[i] = *(u32 *)p;
997 break;
998 }
999 }
1000}
1001
Mugunthan V Ndf828592012-03-18 20:17:54 +00001002static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
1003{
1004 static char *leader = "........................................";
1005
1006 if (!val)
1007 return 0;
1008 else
1009 return snprintf(buf, maxlen, "%s %s %10d\n", name,
1010 leader + strlen(name), val);
1011}
1012
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001013static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1014{
1015 u32 i;
1016 u32 usage_count = 0;
1017
1018 if (!priv->data.dual_emac)
1019 return 0;
1020
1021 for (i = 0; i < priv->data.slaves; i++)
1022 if (priv->slaves[i].open_stat)
1023 usage_count++;
1024
1025 return usage_count;
1026}
1027
1028static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1029 struct cpsw_priv *priv, struct sk_buff *skb)
1030{
1031 if (!priv->data.dual_emac)
1032 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001033 skb->len, 0);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001034
1035 if (ndev == cpsw_get_slave_ndev(priv, 0))
1036 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001037 skb->len, 1);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001038 else
1039 return cpdma_chan_submit(priv->txch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001040 skb->len, 2);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001041}
1042
1043static inline void cpsw_add_dual_emac_def_ale_entries(
1044 struct cpsw_priv *priv, struct cpsw_slave *slave,
1045 u32 slave_port)
1046{
1047 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1048
1049 if (priv->version == CPSW_VERSION_1)
1050 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1051 else
1052 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1053 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1054 port_mask, port_mask, 0);
1055 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1056 port_mask, ALE_VLAN, slave->port_vlan, 0);
1057 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1058 priv->host_port, ALE_VLAN, slave->port_vlan);
1059}
1060
Daniel Mack1e7a2e22013-11-15 08:29:16 +01001061static void soft_reset_slave(struct cpsw_slave *slave)
Mugunthan V Ndf828592012-03-18 20:17:54 +00001062{
1063 char name[32];
Daniel Mack1e7a2e22013-11-15 08:29:16 +01001064
1065 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1066 soft_reset(name, &slave->sliver->soft_reset);
1067}
1068
1069static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1070{
Mugunthan V Ndf828592012-03-18 20:17:54 +00001071 u32 slave_port;
1072
Daniel Mack1e7a2e22013-11-15 08:29:16 +01001073 soft_reset_slave(slave);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001074
1075 /* setup priority mapping */
1076 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
Richard Cochran9750a3a2012-10-29 08:45:15 +00001077
1078 switch (priv->version) {
1079 case CPSW_VERSION_1:
1080 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1081 break;
1082 case CPSW_VERSION_2:
Mugunthan V Nc193f362013-08-05 17:30:05 +05301083 case CPSW_VERSION_3:
Mugunthan V N926489b2013-08-12 17:11:15 +05301084 case CPSW_VERSION_4:
Richard Cochran9750a3a2012-10-29 08:45:15 +00001085 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1086 break;
1087 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001088
1089 /* setup max packet size, and mac address */
1090 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1091 cpsw_set_slave_mac(slave, priv);
1092
1093 slave->mac_control = 0; /* no link yet */
1094
1095 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1096
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001097 if (priv->data.dual_emac)
1098 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1099 else
1100 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1101 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001102
1103 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
Florian Fainellif9a8f832013-01-14 00:52:52 +00001104 &cpsw_adjust_link, slave->data->phy_if);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001105 if (IS_ERR(slave->phy)) {
1106 dev_err(priv->dev, "phy %s not found on slave %d\n",
1107 slave->data->phy_id, slave->slave_num);
1108 slave->phy = NULL;
1109 } else {
1110 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1111 slave->phy->phy_id);
1112 phy_start(slave->phy);
Mugunthan V N388367a2013-09-21 00:50:40 +05301113
1114 /* Configure GMII_SEL register */
1115 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1116 slave->slave_num);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001117 }
1118}
1119
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001120static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1121{
1122 const int vlan = priv->data.default_vlan;
1123 const int port = priv->host_port;
1124 u32 reg;
1125 int i;
1126
1127 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1128 CPSW2_PORT_VLAN;
1129
1130 writel(vlan, &priv->host_port_regs->port_vlan);
1131
Daniel Mack0237c112013-02-26 04:06:20 +00001132 for (i = 0; i < priv->data.slaves; i++)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001133 slave_write(priv->slaves + i, vlan, reg);
1134
1135 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1136 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1137 (ALE_PORT_1 | ALE_PORT_2) << port);
1138}
1139
Mugunthan V Ndf828592012-03-18 20:17:54 +00001140static void cpsw_init_host_port(struct cpsw_priv *priv)
1141{
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001142 u32 control_reg;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001143 u32 fifo_mode;
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001144
Mugunthan V Ndf828592012-03-18 20:17:54 +00001145 /* soft reset the controller and initialize ale */
1146 soft_reset("cpsw", &priv->regs->soft_reset);
1147 cpsw_ale_start(priv->ale);
1148
1149 /* switch to vlan unaware mode */
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001150 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1151 CPSW_ALE_VLAN_AWARE);
1152 control_reg = readl(&priv->regs->control);
1153 control_reg |= CPSW_VLAN_AWARE;
1154 writel(control_reg, &priv->regs->control);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001155 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1156 CPSW_FIFO_NORMAL_MODE;
1157 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001158
1159 /* setup host port priority mapping */
1160 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1161 &priv->host_port_regs->cpdma_tx_pri_map);
1162 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1163
1164 cpsw_ale_control_set(priv->ale, priv->host_port,
1165 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1166
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001167 if (!priv->data.dual_emac) {
1168 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1169 0, 0);
1170 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1171 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1172 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001173}
1174
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001175static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1176{
Schuyler Patton3995d262014-03-03 16:19:06 +05301177 u32 slave_port;
1178
1179 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1180
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001181 if (!slave->phy)
1182 return;
1183 phy_stop(slave->phy);
1184 phy_disconnect(slave->phy);
1185 slave->phy = NULL;
Schuyler Patton3995d262014-03-03 16:19:06 +05301186 cpsw_ale_control_set(priv->ale, slave_port,
1187 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001188}
1189
Mugunthan V Ndf828592012-03-18 20:17:54 +00001190static int cpsw_ndo_open(struct net_device *ndev)
1191{
1192 struct cpsw_priv *priv = netdev_priv(ndev);
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001193 struct cpsw_priv *prim_cpsw;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001194 int i, ret;
1195 u32 reg;
1196
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001197 if (!cpsw_common_res_usage_state(priv))
1198 cpsw_intr_disable(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001199 netif_carrier_off(ndev);
1200
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001201 pm_runtime_get_sync(&priv->pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001202
Richard Cochran549985e2012-11-14 09:07:56 +00001203 reg = priv->version;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001204
1205 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1206 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1207 CPSW_RTL_VERSION(reg));
1208
1209 /* initialize host and slave ports */
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001210 if (!cpsw_common_res_usage_state(priv))
1211 cpsw_init_host_port(priv);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001212 for_each_slave(priv, cpsw_slave_open, priv);
1213
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001214 /* Add default VLAN */
Mugunthan V N629c9a82014-04-09 11:34:40 +05301215 cpsw_add_default_vlan(priv);
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001216
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001217 if (!cpsw_common_res_usage_state(priv)) {
1218 /* setup tx dma to fixed prio and zero offset */
1219 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1220 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001221
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001222 /* disable priority elevation */
1223 __raw_writel(0, &priv->regs->ptype);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001224
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001225 /* enable statistics collection only on all ports */
1226 __raw_writel(0x7, &priv->regs->stat_port_en);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001227
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001228 if (WARN_ON(!priv->data.rx_descs))
1229 priv->data.rx_descs = 128;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001230
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001231 for (i = 0; i < priv->data.rx_descs; i++) {
1232 struct sk_buff *skb;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001233
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001234 ret = -ENOMEM;
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001235 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1236 priv->rx_packet_max, GFP_KERNEL);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001237 if (!skb)
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001238 goto err_cleanup;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001239 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
Sebastian Siewioraef614e2013-04-23 07:31:38 +00001240 skb_tailroom(skb), 0);
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001241 if (ret < 0) {
1242 kfree_skb(skb);
1243 goto err_cleanup;
1244 }
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001245 }
1246 /* continue even if we didn't manage to submit all
1247 * receive descs
1248 */
1249 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
Mugunthan V Nf280e892013-12-11 22:09:05 -06001250
1251 if (cpts_register(&priv->pdev->dev, priv->cpts,
1252 priv->data.cpts_clock_mult,
1253 priv->data.cpts_clock_shift))
1254 dev_err(priv->dev, "error registering cpts device\n");
1255
Mugunthan V Ndf828592012-03-18 20:17:54 +00001256 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001257
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001258 /* Enable Interrupt pacing if configured */
1259 if (priv->coal_intvl != 0) {
1260 struct ethtool_coalesce coal;
1261
1262 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1263 cpsw_set_coalesce(ndev, &coal);
1264 }
1265
Mugunthan V Nf63a9752014-04-10 14:23:24 +05301266 napi_enable(&priv->napi);
1267 cpdma_ctlr_start(priv->dma);
1268 cpsw_intr_enable(priv);
1269 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1270 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1271
Sebastian Siewiora11fbba2013-04-24 08:48:25 +00001272 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1273 if (prim_cpsw->irq_enabled == false) {
1274 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1275 prim_cpsw->irq_enabled = true;
1276 cpsw_enable_irq(prim_cpsw);
1277 }
1278 }
1279
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001280 if (priv->data.dual_emac)
1281 priv->slaves[priv->emac_port].open_stat = true;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001282 return 0;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001283
Sebastian Siewioraacebbf2013-04-23 07:31:36 +00001284err_cleanup:
1285 cpdma_ctlr_stop(priv->dma);
1286 for_each_slave(priv, cpsw_slave_stop, priv);
1287 pm_runtime_put_sync(&priv->pdev->dev);
1288 netif_carrier_off(priv->ndev);
1289 return ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001290}
1291
1292static int cpsw_ndo_stop(struct net_device *ndev)
1293{
1294 struct cpsw_priv *priv = netdev_priv(ndev);
1295
1296 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
Mugunthan V Ndf828592012-03-18 20:17:54 +00001297 netif_stop_queue(priv->ndev);
1298 napi_disable(&priv->napi);
1299 netif_carrier_off(priv->ndev);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001300
1301 if (cpsw_common_res_usage_state(priv) <= 1) {
Mugunthan V Nf280e892013-12-11 22:09:05 -06001302 cpts_unregister(priv->cpts);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001303 cpsw_intr_disable(priv);
1304 cpdma_ctlr_int_ctrl(priv->dma, false);
1305 cpdma_ctlr_stop(priv->dma);
1306 cpsw_ale_stop(priv->ale);
1307 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00001308 for_each_slave(priv, cpsw_slave_stop, priv);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00001309 pm_runtime_put_sync(&priv->pdev->dev);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001310 if (priv->data.dual_emac)
1311 priv->slaves[priv->emac_port].open_stat = false;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001312 return 0;
1313}
1314
1315static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1316 struct net_device *ndev)
1317{
1318 struct cpsw_priv *priv = netdev_priv(ndev);
1319 int ret;
1320
1321 ndev->trans_start = jiffies;
1322
1323 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1324 cpsw_err(priv, tx_err, "packet pad failed\n");
Tobias Klauser8dc43dd2014-03-10 13:12:23 +01001325 ndev->stats.tx_dropped++;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001326 return NETDEV_TX_OK;
1327 }
1328
Mugunthan V N9232b162013-02-11 09:52:19 +00001329 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1330 priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001331 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1332
1333 skb_tx_timestamp(skb);
1334
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001335 ret = cpsw_tx_packet_submit(ndev, priv, skb);
Mugunthan V Ndf828592012-03-18 20:17:54 +00001336 if (unlikely(ret != 0)) {
1337 cpsw_err(priv, tx_err, "desc submit failed\n");
1338 goto fail;
1339 }
1340
Mugunthan V Nfae50822013-01-17 06:31:34 +00001341 /* If there is no more tx desc left free then we need to
1342 * tell the kernel to stop sending us tx frames.
1343 */
Daniel Mackd35162f2013-03-12 06:31:19 +00001344 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
Mugunthan V Nfae50822013-01-17 06:31:34 +00001345 netif_stop_queue(ndev);
1346
Mugunthan V Ndf828592012-03-18 20:17:54 +00001347 return NETDEV_TX_OK;
1348fail:
Tobias Klauser8dc43dd2014-03-10 13:12:23 +01001349 ndev->stats.tx_dropped++;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001350 netif_stop_queue(ndev);
1351 return NETDEV_TX_BUSY;
1352}
1353
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001354#ifdef CONFIG_TI_CPTS
1355
1356static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1357{
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001358 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001359 u32 ts_en, seq_id;
1360
Mugunthan V N9232b162013-02-11 09:52:19 +00001361 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001362 slave_write(slave, 0, CPSW1_TS_CTL);
1363 return;
1364 }
1365
1366 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1367 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1368
Mugunthan V N9232b162013-02-11 09:52:19 +00001369 if (priv->cpts->tx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001370 ts_en |= CPSW_V1_TS_TX_EN;
1371
Mugunthan V N9232b162013-02-11 09:52:19 +00001372 if (priv->cpts->rx_enable)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001373 ts_en |= CPSW_V1_TS_RX_EN;
1374
1375 slave_write(slave, ts_en, CPSW1_TS_CTL);
1376 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1377}
1378
1379static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1380{
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001381 struct cpsw_slave *slave;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001382 u32 ctrl, mtype;
1383
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001384 if (priv->data.dual_emac)
1385 slave = &priv->slaves[priv->emac_port];
1386 else
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001387 slave = &priv->slaves[priv->data.active_slave];
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001388
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001389 ctrl = slave_read(slave, CPSW2_CONTROL);
George Cherian09c55372014-05-02 12:02:02 +05301390 switch (priv->version) {
1391 case CPSW_VERSION_2:
1392 ctrl &= ~CTRL_V2_ALL_TS_MASK;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001393
George Cherian09c55372014-05-02 12:02:02 +05301394 if (priv->cpts->tx_enable)
1395 ctrl |= CTRL_V2_TX_TS_BITS;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001396
George Cherian09c55372014-05-02 12:02:02 +05301397 if (priv->cpts->rx_enable)
1398 ctrl |= CTRL_V2_RX_TS_BITS;
1399 break;
1400 case CPSW_VERSION_3:
1401 default:
1402 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1403
1404 if (priv->cpts->tx_enable)
1405 ctrl |= CTRL_V3_TX_TS_BITS;
1406
1407 if (priv->cpts->rx_enable)
1408 ctrl |= CTRL_V3_RX_TS_BITS;
1409 break;
1410 }
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001411
1412 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1413
1414 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1415 slave_write(slave, ctrl, CPSW2_CONTROL);
1416 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1417}
1418
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001419static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001420{
Mugunthan V N3177bf62012-11-27 07:53:40 +00001421 struct cpsw_priv *priv = netdev_priv(dev);
Mugunthan V N9232b162013-02-11 09:52:19 +00001422 struct cpts *cpts = priv->cpts;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001423 struct hwtstamp_config cfg;
1424
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001425 if (priv->version != CPSW_VERSION_1 &&
George Cherianf7d403c2014-05-02 12:02:01 +05301426 priv->version != CPSW_VERSION_2 &&
1427 priv->version != CPSW_VERSION_3)
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001428 return -EOPNOTSUPP;
1429
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001430 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1431 return -EFAULT;
1432
1433 /* reserved for future extensions */
1434 if (cfg.flags)
1435 return -EINVAL;
1436
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001437 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001438 return -ERANGE;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001439
1440 switch (cfg.rx_filter) {
1441 case HWTSTAMP_FILTER_NONE:
1442 cpts->rx_enable = 0;
1443 break;
1444 case HWTSTAMP_FILTER_ALL:
1445 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1446 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1447 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1448 return -ERANGE;
1449 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1450 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1451 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1452 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1453 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1454 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1455 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1456 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1457 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1458 cpts->rx_enable = 1;
1459 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1460 break;
1461 default:
1462 return -ERANGE;
1463 }
1464
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001465 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1466
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001467 switch (priv->version) {
1468 case CPSW_VERSION_1:
1469 cpsw_hwtstamp_v1(priv);
1470 break;
1471 case CPSW_VERSION_2:
George Cherianf7d403c2014-05-02 12:02:01 +05301472 case CPSW_VERSION_3:
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001473 cpsw_hwtstamp_v2(priv);
1474 break;
1475 default:
Ben Hutchings2ee91e52013-11-14 00:47:36 +00001476 WARN_ON(1);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001477 }
1478
1479 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1480}
1481
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001482static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1483{
1484 struct cpsw_priv *priv = netdev_priv(dev);
1485 struct cpts *cpts = priv->cpts;
1486 struct hwtstamp_config cfg;
1487
1488 if (priv->version != CPSW_VERSION_1 &&
George Cherianf7d403c2014-05-02 12:02:01 +05301489 priv->version != CPSW_VERSION_2 &&
1490 priv->version != CPSW_VERSION_3)
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001491 return -EOPNOTSUPP;
1492
1493 cfg.flags = 0;
1494 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1495 cfg.rx_filter = (cpts->rx_enable ?
1496 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1497
1498 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1499}
1500
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001501#endif /*CONFIG_TI_CPTS*/
1502
1503static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1504{
Mugunthan V N11f2c982013-03-11 23:16:38 +00001505 struct cpsw_priv *priv = netdev_priv(dev);
Mugunthan V N11f2c982013-03-11 23:16:38 +00001506 int slave_no = cpsw_slave_index(priv);
1507
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001508 if (!netif_running(dev))
1509 return -EINVAL;
1510
Mugunthan V N11f2c982013-03-11 23:16:38 +00001511 switch (cmd) {
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001512#ifdef CONFIG_TI_CPTS
Mugunthan V N11f2c982013-03-11 23:16:38 +00001513 case SIOCSHWTSTAMP:
Ben Hutchingsa5b41452013-11-18 23:23:40 +00001514 return cpsw_hwtstamp_set(dev, req);
1515 case SIOCGHWTSTAMP:
1516 return cpsw_hwtstamp_get(dev, req);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001517#endif
Mugunthan V N11f2c982013-03-11 23:16:38 +00001518 }
1519
Stefan Sørensenc1b59942014-02-16 14:54:25 +01001520 if (!priv->slaves[slave_no].phy)
1521 return -EOPNOTSUPP;
1522 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001523}
1524
Mugunthan V Ndf828592012-03-18 20:17:54 +00001525static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1526{
1527 struct cpsw_priv *priv = netdev_priv(ndev);
1528
1529 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
Tobias Klauser8dc43dd2014-03-10 13:12:23 +01001530 ndev->stats.tx_errors++;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001531 cpsw_intr_disable(priv);
1532 cpdma_ctlr_int_ctrl(priv->dma, false);
1533 cpdma_chan_stop(priv->txch);
1534 cpdma_chan_start(priv->txch);
1535 cpdma_ctlr_int_ctrl(priv->dma, true);
1536 cpsw_intr_enable(priv);
Mugunthan V N510a1e722013-02-17 22:19:20 +00001537 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1538 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1539
Mugunthan V Ndf828592012-03-18 20:17:54 +00001540}
1541
Mugunthan V Ndcfd8d52013-07-25 23:44:01 +05301542static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1543{
1544 struct cpsw_priv *priv = netdev_priv(ndev);
1545 struct sockaddr *addr = (struct sockaddr *)p;
1546 int flags = 0;
1547 u16 vid = 0;
1548
1549 if (!is_valid_ether_addr(addr->sa_data))
1550 return -EADDRNOTAVAIL;
1551
1552 if (priv->data.dual_emac) {
1553 vid = priv->slaves[priv->emac_port].port_vlan;
1554 flags = ALE_VLAN;
1555 }
1556
1557 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1558 flags, vid);
1559 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1560 flags, vid);
1561
1562 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1563 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1564 for_each_slave(priv, cpsw_set_slave_mac, priv);
1565
1566 return 0;
1567}
1568
Mugunthan V Ndf828592012-03-18 20:17:54 +00001569#ifdef CONFIG_NET_POLL_CONTROLLER
1570static void cpsw_ndo_poll_controller(struct net_device *ndev)
1571{
1572 struct cpsw_priv *priv = netdev_priv(ndev);
1573
1574 cpsw_intr_disable(priv);
1575 cpdma_ctlr_int_ctrl(priv->dma, false);
1576 cpsw_interrupt(ndev->irq, priv);
1577 cpdma_ctlr_int_ctrl(priv->dma, true);
1578 cpsw_intr_enable(priv);
Mugunthan V N510a1e722013-02-17 22:19:20 +00001579 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1580 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1581
Mugunthan V Ndf828592012-03-18 20:17:54 +00001582}
1583#endif
1584
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001585static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1586 unsigned short vid)
1587{
1588 int ret;
1589
1590 ret = cpsw_ale_add_vlan(priv->ale, vid,
1591 ALE_ALL_PORTS << priv->host_port,
1592 0, ALE_ALL_PORTS << priv->host_port,
1593 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1594 if (ret != 0)
1595 return ret;
1596
1597 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1598 priv->host_port, ALE_VLAN, vid);
1599 if (ret != 0)
1600 goto clean_vid;
1601
1602 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1603 ALE_ALL_PORTS << priv->host_port,
1604 ALE_VLAN, vid, 0);
1605 if (ret != 0)
1606 goto clean_vlan_ucast;
1607 return 0;
1608
1609clean_vlan_ucast:
1610 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1611 priv->host_port, ALE_VLAN, vid);
1612clean_vid:
1613 cpsw_ale_del_vlan(priv->ale, vid, 0);
1614 return ret;
1615}
1616
1617static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
Patrick McHardy80d5c362013-04-19 02:04:28 +00001618 __be16 proto, u16 vid)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001619{
1620 struct cpsw_priv *priv = netdev_priv(ndev);
1621
1622 if (vid == priv->data.default_vlan)
1623 return 0;
1624
1625 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1626 return cpsw_add_vlan_ale_entry(priv, vid);
1627}
1628
1629static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
Patrick McHardy80d5c362013-04-19 02:04:28 +00001630 __be16 proto, u16 vid)
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001631{
1632 struct cpsw_priv *priv = netdev_priv(ndev);
1633 int ret;
1634
1635 if (vid == priv->data.default_vlan)
1636 return 0;
1637
1638 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1639 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1640 if (ret != 0)
1641 return ret;
1642
1643 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1644 priv->host_port, ALE_VLAN, vid);
1645 if (ret != 0)
1646 return ret;
1647
1648 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1649 0, ALE_VLAN, vid);
1650}
1651
Mugunthan V Ndf828592012-03-18 20:17:54 +00001652static const struct net_device_ops cpsw_netdev_ops = {
1653 .ndo_open = cpsw_ndo_open,
1654 .ndo_stop = cpsw_ndo_stop,
1655 .ndo_start_xmit = cpsw_ndo_start_xmit,
Mugunthan V Ndcfd8d52013-07-25 23:44:01 +05301656 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001657 .ndo_do_ioctl = cpsw_ndo_ioctl,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001658 .ndo_validate_addr = eth_validate_addr,
David S. Miller5c473ed2012-03-20 00:33:59 -04001659 .ndo_change_mtu = eth_change_mtu,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001660 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
Mugunthan V N5c50a852012-10-29 08:45:11 +00001661 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001662#ifdef CONFIG_NET_POLL_CONTROLLER
1663 .ndo_poll_controller = cpsw_ndo_poll_controller,
1664#endif
Mugunthan V N3b72c2f2013-02-05 08:26:48 +00001665 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1666 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001667};
1668
1669static void cpsw_get_drvinfo(struct net_device *ndev,
1670 struct ethtool_drvinfo *info)
1671{
1672 struct cpsw_priv *priv = netdev_priv(ndev);
Jiri Pirko7826d432013-01-06 00:44:26 +00001673
1674 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1675 strlcpy(info->version, "1.0", sizeof(info->version));
1676 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
Mugunthan V Ndf828592012-03-18 20:17:54 +00001677}
1678
1679static u32 cpsw_get_msglevel(struct net_device *ndev)
1680{
1681 struct cpsw_priv *priv = netdev_priv(ndev);
1682 return priv->msg_enable;
1683}
1684
1685static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1686{
1687 struct cpsw_priv *priv = netdev_priv(ndev);
1688 priv->msg_enable = value;
1689}
1690
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001691static int cpsw_get_ts_info(struct net_device *ndev,
1692 struct ethtool_ts_info *info)
1693{
1694#ifdef CONFIG_TI_CPTS
1695 struct cpsw_priv *priv = netdev_priv(ndev);
1696
1697 info->so_timestamping =
1698 SOF_TIMESTAMPING_TX_HARDWARE |
1699 SOF_TIMESTAMPING_TX_SOFTWARE |
1700 SOF_TIMESTAMPING_RX_HARDWARE |
1701 SOF_TIMESTAMPING_RX_SOFTWARE |
1702 SOF_TIMESTAMPING_SOFTWARE |
1703 SOF_TIMESTAMPING_RAW_HARDWARE;
Mugunthan V N9232b162013-02-11 09:52:19 +00001704 info->phc_index = priv->cpts->phc_index;
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001705 info->tx_types =
1706 (1 << HWTSTAMP_TX_OFF) |
1707 (1 << HWTSTAMP_TX_ON);
1708 info->rx_filters =
1709 (1 << HWTSTAMP_FILTER_NONE) |
1710 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1711#else
1712 info->so_timestamping =
1713 SOF_TIMESTAMPING_TX_SOFTWARE |
1714 SOF_TIMESTAMPING_RX_SOFTWARE |
1715 SOF_TIMESTAMPING_SOFTWARE;
1716 info->phc_index = -1;
1717 info->tx_types = 0;
1718 info->rx_filters = 0;
1719#endif
1720 return 0;
1721}
1722
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +00001723static int cpsw_get_settings(struct net_device *ndev,
1724 struct ethtool_cmd *ecmd)
1725{
1726 struct cpsw_priv *priv = netdev_priv(ndev);
1727 int slave_no = cpsw_slave_index(priv);
1728
1729 if (priv->slaves[slave_no].phy)
1730 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1731 else
1732 return -EOPNOTSUPP;
1733}
1734
1735static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1736{
1737 struct cpsw_priv *priv = netdev_priv(ndev);
1738 int slave_no = cpsw_slave_index(priv);
1739
1740 if (priv->slaves[slave_no].phy)
1741 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1742 else
1743 return -EOPNOTSUPP;
1744}
1745
Matus Ujhelyid8a64422013-08-20 07:59:38 +02001746static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1747{
1748 struct cpsw_priv *priv = netdev_priv(ndev);
1749 int slave_no = cpsw_slave_index(priv);
1750
1751 wol->supported = 0;
1752 wol->wolopts = 0;
1753
1754 if (priv->slaves[slave_no].phy)
1755 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1756}
1757
1758static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1759{
1760 struct cpsw_priv *priv = netdev_priv(ndev);
1761 int slave_no = cpsw_slave_index(priv);
1762
1763 if (priv->slaves[slave_no].phy)
1764 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1765 else
1766 return -EOPNOTSUPP;
1767}
1768
Mugunthan V Ndf828592012-03-18 20:17:54 +00001769static const struct ethtool_ops cpsw_ethtool_ops = {
1770 .get_drvinfo = cpsw_get_drvinfo,
1771 .get_msglevel = cpsw_get_msglevel,
1772 .set_msglevel = cpsw_set_msglevel,
1773 .get_link = ethtool_op_get_link,
Richard Cochran2e5b38a2012-10-29 08:45:20 +00001774 .get_ts_info = cpsw_get_ts_info,
Mugunthan V Nd3bb9c52013-03-11 23:16:36 +00001775 .get_settings = cpsw_get_settings,
1776 .set_settings = cpsw_set_settings,
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001777 .get_coalesce = cpsw_get_coalesce,
1778 .set_coalesce = cpsw_set_coalesce,
Mugunthan V Nd9718542013-07-23 15:38:17 +05301779 .get_sset_count = cpsw_get_sset_count,
1780 .get_strings = cpsw_get_strings,
1781 .get_ethtool_stats = cpsw_get_ethtool_stats,
Matus Ujhelyid8a64422013-08-20 07:59:38 +02001782 .get_wol = cpsw_get_wol,
1783 .set_wol = cpsw_set_wol,
Mugunthan V Ndf828592012-03-18 20:17:54 +00001784};
1785
Richard Cochran549985e2012-11-14 09:07:56 +00001786static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1787 u32 slave_reg_ofs, u32 sliver_reg_ofs)
Mugunthan V Ndf828592012-03-18 20:17:54 +00001788{
1789 void __iomem *regs = priv->regs;
1790 int slave_num = slave->slave_num;
1791 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1792
1793 slave->data = data;
Richard Cochran549985e2012-11-14 09:07:56 +00001794 slave->regs = regs + slave_reg_ofs;
1795 slave->sliver = regs + sliver_reg_ofs;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001796 slave->port_vlan = data->dual_emac_res_vlan;
Mugunthan V Ndf828592012-03-18 20:17:54 +00001797}
1798
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001799static int cpsw_probe_dt(struct cpsw_platform_data *data,
1800 struct platform_device *pdev)
1801{
1802 struct device_node *node = pdev->dev.of_node;
1803 struct device_node *slave_node;
1804 int i = 0, ret;
1805 u32 prop;
1806
1807 if (!node)
1808 return -EINVAL;
1809
1810 if (of_property_read_u32(node, "slaves", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301811 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001812 return -EINVAL;
1813 }
1814 data->slaves = prop;
1815
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001816 if (of_property_read_u32(node, "active_slave", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301817 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301818 return -EINVAL;
Richard Cochran78ca0b22012-10-29 08:45:18 +00001819 }
Mugunthan V Ne86ac132013-03-11 23:16:35 +00001820 data->active_slave = prop;
Richard Cochran78ca0b22012-10-29 08:45:18 +00001821
Richard Cochran00ab94e2012-10-29 08:45:19 +00001822 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301823 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301824 return -EINVAL;
Richard Cochran00ab94e2012-10-29 08:45:19 +00001825 }
1826 data->cpts_clock_mult = prop;
1827
1828 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301829 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301830 return -EINVAL;
Richard Cochran00ab94e2012-10-29 08:45:19 +00001831 }
1832 data->cpts_clock_shift = prop;
1833
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301834 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1835 * sizeof(struct cpsw_slave_data),
1836 GFP_KERNEL);
Joe Perchesb2adaca2013-02-03 17:43:58 +00001837 if (!data->slave_data)
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301838 return -ENOMEM;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001839
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001840 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301841 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301842 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001843 }
1844 data->channels = prop;
1845
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001846 if (of_property_read_u32(node, "ale_entries", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301847 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301848 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001849 }
1850 data->ale_entries = prop;
1851
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001852 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301853 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301854 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001855 }
1856 data->bd_ram_size = prop;
1857
1858 if (of_property_read_u32(node, "rx_descs", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301859 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301860 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001861 }
1862 data->rx_descs = prop;
1863
1864 if (of_property_read_u32(node, "mac_control", &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301865 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301866 return -EINVAL;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001867 }
1868 data->mac_control = prop;
1869
Markus Pargmann281abd92013-10-04 14:44:40 +02001870 if (of_property_read_bool(node, "dual_emac"))
1871 data->dual_emac = 1;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001872
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00001873 /*
1874 * Populate all the child nodes here...
1875 */
1876 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1877 /* We do not want to force this, as in some cases may not have child */
1878 if (ret)
George Cherian88c99ff2014-05-12 10:21:19 +05301879 dev_warn(&pdev->dev, "Doesn't have any child node\n");
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00001880
Markus Pargmannf468b102013-10-04 14:44:39 +02001881 for_each_child_of_node(node, slave_node) {
Richard Cochran549985e2012-11-14 09:07:56 +00001882 struct cpsw_slave_data *slave_data = data->slave_data + i;
1883 const void *mac_addr = NULL;
1884 u32 phyid;
1885 int lenp;
1886 const __be32 *parp;
1887 struct device_node *mdio_node;
1888 struct platform_device *mdio;
1889
Markus Pargmannf468b102013-10-04 14:44:39 +02001890 /* This is no slave child node, continue */
1891 if (strcmp(slave_node->name, "slave"))
1892 continue;
1893
Richard Cochran549985e2012-11-14 09:07:56 +00001894 parp = of_get_property(slave_node, "phy_id", &lenp);
Lothar Waßmannce162942013-03-21 02:20:11 +00001895 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
George Cherian88c99ff2014-05-12 10:21:19 +05301896 dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
Daniel Mackaa1a15e2013-09-21 00:50:38 +05301897 return -EINVAL;
Richard Cochran549985e2012-11-14 09:07:56 +00001898 }
1899 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1900 phyid = be32_to_cpup(parp+1);
1901 mdio = of_find_device_by_node(mdio_node);
Johan Hovold60e71ab2014-05-08 10:09:24 +02001902 of_node_put(mdio_node);
Johan Hovold6954cc12014-05-08 10:09:23 +02001903 if (!mdio) {
1904 pr_err("Missing mdio platform device\n");
1905 return -EINVAL;
Stefan Roesef8d56d82014-01-29 11:32:37 +01001906 }
Johan Hovold59993f482014-05-08 10:09:22 +02001907 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1908 PHY_ID_FMT, mdio->name, phyid);
Richard Cochran549985e2012-11-14 09:07:56 +00001909
1910 mac_addr = of_get_mac_address(slave_node);
1911 if (mac_addr)
1912 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1913
Mugunthan V Nc5ceea72013-06-03 20:10:10 +00001914 slave_data->phy_if = of_get_phy_mode(slave_node);
Uwe Kleine-König89e10172014-02-12 23:33:22 +01001915 if (slave_data->phy_if < 0) {
George Cherian88c99ff2014-05-12 10:21:19 +05301916 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
1917 i);
Uwe Kleine-König89e10172014-02-12 23:33:22 +01001918 return slave_data->phy_if;
1919 }
Mugunthan V Nc5ceea72013-06-03 20:10:10 +00001920
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001921 if (data->dual_emac) {
Mugunthan V N91c41662013-04-15 07:31:28 +00001922 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001923 &prop)) {
George Cherian88c99ff2014-05-12 10:21:19 +05301924 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001925 slave_data->dual_emac_res_vlan = i+1;
George Cherian88c99ff2014-05-12 10:21:19 +05301926 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
1927 slave_data->dual_emac_res_vlan, i);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001928 } else {
1929 slave_data->dual_emac_res_vlan = prop;
1930 }
1931 }
1932
Richard Cochran549985e2012-11-14 09:07:56 +00001933 i++;
Mugunthan V N3a27bfa2013-12-02 12:53:39 +05301934 if (i == data->slaves)
1935 break;
Richard Cochran549985e2012-11-14 09:07:56 +00001936 }
1937
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001938 return 0;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00001939}
1940
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001941static int cpsw_probe_dual_emac(struct platform_device *pdev,
1942 struct cpsw_priv *priv)
1943{
1944 struct cpsw_platform_data *data = &priv->data;
1945 struct net_device *ndev;
1946 struct cpsw_priv *priv_sl2;
1947 int ret = 0, i;
1948
1949 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1950 if (!ndev) {
George Cherian88c99ff2014-05-12 10:21:19 +05301951 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001952 return -ENOMEM;
1953 }
1954
1955 priv_sl2 = netdev_priv(ndev);
1956 spin_lock_init(&priv_sl2->lock);
1957 priv_sl2->data = *data;
1958 priv_sl2->pdev = pdev;
1959 priv_sl2->ndev = ndev;
1960 priv_sl2->dev = &ndev->dev;
1961 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1962 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1963
1964 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1965 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1966 ETH_ALEN);
George Cherian88c99ff2014-05-12 10:21:19 +05301967 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001968 } else {
1969 random_ether_addr(priv_sl2->mac_addr);
George Cherian88c99ff2014-05-12 10:21:19 +05301970 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001971 }
1972 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1973
1974 priv_sl2->slaves = priv->slaves;
1975 priv_sl2->clk = priv->clk;
1976
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00001977 priv_sl2->coal_intvl = 0;
1978 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1979
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001980 priv_sl2->regs = priv->regs;
1981 priv_sl2->host_port = priv->host_port;
1982 priv_sl2->host_port_regs = priv->host_port_regs;
1983 priv_sl2->wr_regs = priv->wr_regs;
Mugunthan V Nd9718542013-07-23 15:38:17 +05301984 priv_sl2->hw_stats = priv->hw_stats;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001985 priv_sl2->dma = priv->dma;
1986 priv_sl2->txch = priv->txch;
1987 priv_sl2->rxch = priv->rxch;
1988 priv_sl2->ale = priv->ale;
1989 priv_sl2->emac_port = 1;
1990 priv->slaves[1].ndev = ndev;
1991 priv_sl2->cpts = priv->cpts;
1992 priv_sl2->version = priv->version;
1993
1994 for (i = 0; i < priv->num_irqs; i++) {
1995 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1996 priv_sl2->num_irqs = priv->num_irqs;
1997 }
Patrick McHardyf6469682013-04-19 02:04:27 +00001998 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00001999
2000 ndev->netdev_ops = &cpsw_netdev_ops;
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00002001 ndev->ethtool_ops = &cpsw_ethtool_ops;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002002 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2003
2004 /* register the network device */
2005 SET_NETDEV_DEV(ndev, &pdev->dev);
2006 ret = register_netdev(ndev);
2007 if (ret) {
George Cherian88c99ff2014-05-12 10:21:19 +05302008 dev_err(&pdev->dev, "cpsw: error registering net device\n");
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002009 free_netdev(ndev);
2010 ret = -ENODEV;
2011 }
2012
2013 return ret;
2014}
2015
Bill Pemberton663e12e2012-12-03 09:23:45 -05002016static int cpsw_probe(struct platform_device *pdev)
Mugunthan V Ndf828592012-03-18 20:17:54 +00002017{
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002018 struct cpsw_platform_data *data;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002019 struct net_device *ndev;
2020 struct cpsw_priv *priv;
2021 struct cpdma_params dma_params;
2022 struct cpsw_ale_params ale_params;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302023 void __iomem *ss_regs;
2024 struct resource *res, *ss_res;
Richard Cochran549985e2012-11-14 09:07:56 +00002025 u32 slave_offset, sliver_offset, slave_size;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002026 int ret = 0, i, k = 0;
2027
Mugunthan V Ndf828592012-03-18 20:17:54 +00002028 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2029 if (!ndev) {
George Cherian88c99ff2014-05-12 10:21:19 +05302030 dev_err(&pdev->dev, "error allocating net_device\n");
Mugunthan V Ndf828592012-03-18 20:17:54 +00002031 return -ENOMEM;
2032 }
2033
2034 platform_set_drvdata(pdev, ndev);
2035 priv = netdev_priv(ndev);
2036 spin_lock_init(&priv->lock);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002037 priv->pdev = pdev;
2038 priv->ndev = ndev;
2039 priv->dev = &ndev->dev;
2040 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2041 priv->rx_packet_max = max(rx_packet_max, 128);
Mugunthan V N9232b162013-02-11 09:52:19 +00002042 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
Mugunthan V N7dcf3132013-04-29 23:27:28 +00002043 priv->irq_enabled = true;
Sebastian Siewiorab8e99d2013-06-17 19:31:52 +02002044 if (!priv->cpts) {
George Cherian88c99ff2014-05-12 10:21:19 +05302045 dev_err(&pdev->dev, "error allocating cpts\n");
Mugunthan V N9232b162013-02-11 09:52:19 +00002046 goto clean_ndev_ret;
2047 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00002048
Vaibhav Hiremath1fb19aa2012-11-14 09:07:55 +00002049 /*
2050 * This may be required here for child devices.
2051 */
2052 pm_runtime_enable(&pdev->dev);
2053
Mugunthan V N739683b2013-06-06 23:45:14 +05302054 /* Select default pin state */
2055 pinctrl_pm_select_default_state(&pdev->dev);
2056
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002057 if (cpsw_probe_dt(&priv->data, pdev)) {
George Cherian88c99ff2014-05-12 10:21:19 +05302058 dev_err(&pdev->dev, "cpsw: platform data missing\n");
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002059 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302060 goto clean_runtime_disable_ret;
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002061 }
2062 data = &priv->data;
2063
Mugunthan V Ndf828592012-03-18 20:17:54 +00002064 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2065 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
George Cherian88c99ff2014-05-12 10:21:19 +05302066 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002067 } else {
Joe Perches7efd26d2012-07-12 19:33:06 +00002068 eth_random_addr(priv->mac_addr);
George Cherian88c99ff2014-05-12 10:21:19 +05302069 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002070 }
2071
2072 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2073
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302074 priv->slaves = devm_kzalloc(&pdev->dev,
2075 sizeof(struct cpsw_slave) * data->slaves,
2076 GFP_KERNEL);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002077 if (!priv->slaves) {
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302078 ret = -ENOMEM;
2079 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002080 }
2081 for (i = 0; i < data->slaves; i++)
2082 priv->slaves[i].slave_num = i;
2083
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002084 priv->slaves[0].ndev = ndev;
2085 priv->emac_port = 0;
2086
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302087 priv->clk = devm_clk_get(&pdev->dev, "fck");
Mugunthan V Ndf828592012-03-18 20:17:54 +00002088 if (IS_ERR(priv->clk)) {
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302089 dev_err(priv->dev, "fck is not found\n");
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002090 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302091 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002092 }
Mugunthan V Nff5b8ef2013-03-11 23:16:37 +00002093 priv->coal_intvl = 0;
2094 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002095
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302096 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2097 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2098 if (IS_ERR(ss_regs)) {
2099 ret = PTR_ERR(ss_regs);
2100 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002101 }
Richard Cochran549985e2012-11-14 09:07:56 +00002102 priv->regs = ss_regs;
Richard Cochran549985e2012-11-14 09:07:56 +00002103 priv->host_port = HOST_PORT_NUM;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002104
Mugunthan V Nf280e892013-12-11 22:09:05 -06002105 /* Need to enable clocks with runtime PM api to access module
2106 * registers
2107 */
2108 pm_runtime_get_sync(&pdev->dev);
2109 priv->version = readl(&priv->regs->id_ver);
2110 pm_runtime_put_sync(&pdev->dev);
2111
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302112 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2113 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2114 if (IS_ERR(priv->wr_regs)) {
2115 ret = PTR_ERR(priv->wr_regs);
2116 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002117 }
Mugunthan V Ndf828592012-03-18 20:17:54 +00002118
2119 memset(&dma_params, 0, sizeof(dma_params));
Richard Cochran549985e2012-11-14 09:07:56 +00002120 memset(&ale_params, 0, sizeof(ale_params));
2121
2122 switch (priv->version) {
2123 case CPSW_VERSION_1:
2124 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
Mugunthan V Nd9718542013-07-23 15:38:17 +05302125 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2126 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
Richard Cochran549985e2012-11-14 09:07:56 +00002127 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2128 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2129 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2130 slave_offset = CPSW1_SLAVE_OFFSET;
2131 slave_size = CPSW1_SLAVE_SIZE;
2132 sliver_offset = CPSW1_SLIVER_OFFSET;
2133 dma_params.desc_mem_phys = 0;
2134 break;
2135 case CPSW_VERSION_2:
Mugunthan V Nc193f362013-08-05 17:30:05 +05302136 case CPSW_VERSION_3:
Mugunthan V N926489b2013-08-12 17:11:15 +05302137 case CPSW_VERSION_4:
Richard Cochran549985e2012-11-14 09:07:56 +00002138 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
Mugunthan V Nd9718542013-07-23 15:38:17 +05302139 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2140 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
Richard Cochran549985e2012-11-14 09:07:56 +00002141 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2142 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2143 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2144 slave_offset = CPSW2_SLAVE_OFFSET;
2145 slave_size = CPSW2_SLAVE_SIZE;
2146 sliver_offset = CPSW2_SLIVER_OFFSET;
2147 dma_params.desc_mem_phys =
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302148 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
Richard Cochran549985e2012-11-14 09:07:56 +00002149 break;
2150 default:
2151 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2152 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302153 goto clean_runtime_disable_ret;
Richard Cochran549985e2012-11-14 09:07:56 +00002154 }
2155 for (i = 0; i < priv->data.slaves; i++) {
2156 struct cpsw_slave *slave = &priv->slaves[i];
2157 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2158 slave_offset += slave_size;
2159 sliver_offset += SLIVER_SIZE;
2160 }
2161
Mugunthan V Ndf828592012-03-18 20:17:54 +00002162 dma_params.dev = &pdev->dev;
Richard Cochran549985e2012-11-14 09:07:56 +00002163 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2164 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2165 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2166 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2167 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002168
2169 dma_params.num_chan = data->channels;
2170 dma_params.has_soft_reset = true;
2171 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2172 dma_params.desc_mem_size = data->bd_ram_size;
2173 dma_params.desc_align = 16;
2174 dma_params.has_ext_regs = true;
Richard Cochran549985e2012-11-14 09:07:56 +00002175 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002176
2177 priv->dma = cpdma_ctlr_create(&dma_params);
2178 if (!priv->dma) {
2179 dev_err(priv->dev, "error initializing dma\n");
2180 ret = -ENOMEM;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302181 goto clean_runtime_disable_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002182 }
2183
2184 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2185 cpsw_tx_handler);
2186 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2187 cpsw_rx_handler);
2188
2189 if (WARN_ON(!priv->txch || !priv->rxch)) {
2190 dev_err(priv->dev, "error initializing dma channels\n");
2191 ret = -ENOMEM;
2192 goto clean_dma_ret;
2193 }
2194
Mugunthan V Ndf828592012-03-18 20:17:54 +00002195 ale_params.dev = &ndev->dev;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002196 ale_params.ale_ageout = ale_ageout;
2197 ale_params.ale_entries = data->ale_entries;
2198 ale_params.ale_ports = data->slaves;
2199
2200 priv->ale = cpsw_ale_create(&ale_params);
2201 if (!priv->ale) {
2202 dev_err(priv->dev, "error initializing ale engine\n");
2203 ret = -ENODEV;
2204 goto clean_dma_ret;
2205 }
2206
2207 ndev->irq = platform_get_irq(pdev, 0);
2208 if (ndev->irq < 0) {
2209 dev_err(priv->dev, "error getting irq resource\n");
2210 ret = -ENOENT;
2211 goto clean_ale_ret;
2212 }
2213
2214 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2215 for (i = res->start; i <= res->end; i++) {
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302216 if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
Mugunthan V Ndb850552013-12-18 21:33:50 +05302217 dev_name(&pdev->dev), priv)) {
Mugunthan V Ndf828592012-03-18 20:17:54 +00002218 dev_err(priv->dev, "error attaching irq\n");
2219 goto clean_ale_ret;
2220 }
2221 priv->irqs_table[k] = i;
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002222 priv->num_irqs = k + 1;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002223 }
2224 k++;
2225 }
2226
Patrick McHardyf6469682013-04-19 02:04:27 +00002227 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002228
2229 ndev->netdev_ops = &cpsw_netdev_ops;
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00002230 ndev->ethtool_ops = &cpsw_ethtool_ops;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002231 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2232
2233 /* register the network device */
2234 SET_NETDEV_DEV(ndev, &pdev->dev);
2235 ret = register_netdev(ndev);
2236 if (ret) {
2237 dev_err(priv->dev, "error registering net device\n");
2238 ret = -ENODEV;
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302239 goto clean_ale_ret;
Mugunthan V Ndf828592012-03-18 20:17:54 +00002240 }
2241
Olof Johansson1a3b5052013-12-11 15:58:07 -08002242 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2243 &ss_res->start, ndev->irq);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002244
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002245 if (priv->data.dual_emac) {
2246 ret = cpsw_probe_dual_emac(pdev, priv);
2247 if (ret) {
2248 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302249 goto clean_ale_ret;
Mugunthan V Nd9ba8f92013-02-11 09:52:20 +00002250 }
2251 }
2252
Mugunthan V Ndf828592012-03-18 20:17:54 +00002253 return 0;
2254
Mugunthan V Ndf828592012-03-18 20:17:54 +00002255clean_ale_ret:
2256 cpsw_ale_destroy(priv->ale);
2257clean_dma_ret:
2258 cpdma_chan_destroy(priv->txch);
2259 cpdma_chan_destroy(priv->rxch);
2260 cpdma_ctlr_destroy(priv->dma);
Daniel Mackaa1a15e2013-09-21 00:50:38 +05302261clean_runtime_disable_ret:
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002262 pm_runtime_disable(&pdev->dev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002263clean_ndev_ret:
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002264 free_netdev(priv->ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002265 return ret;
2266}
2267
Bill Pemberton663e12e2012-12-03 09:23:45 -05002268static int cpsw_remove(struct platform_device *pdev)
Mugunthan V Ndf828592012-03-18 20:17:54 +00002269{
2270 struct net_device *ndev = platform_get_drvdata(pdev);
2271 struct cpsw_priv *priv = netdev_priv(ndev);
2272
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002273 if (priv->data.dual_emac)
2274 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2275 unregister_netdev(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002276
Mugunthan V Ndf828592012-03-18 20:17:54 +00002277 cpsw_ale_destroy(priv->ale);
2278 cpdma_chan_destroy(priv->txch);
2279 cpdma_chan_destroy(priv->rxch);
2280 cpdma_ctlr_destroy(priv->dma);
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002281 pm_runtime_disable(&pdev->dev);
Sebastian Siewiord1bd9ac2013-04-24 08:48:23 +00002282 if (priv->data.dual_emac)
2283 free_netdev(cpsw_get_slave_ndev(priv, 1));
Mugunthan V Ndf828592012-03-18 20:17:54 +00002284 free_netdev(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002285 return 0;
2286}
2287
2288static int cpsw_suspend(struct device *dev)
2289{
2290 struct platform_device *pdev = to_platform_device(dev);
2291 struct net_device *ndev = platform_get_drvdata(pdev);
Mugunthan V Nb90fc272013-06-21 19:15:09 +05302292 struct cpsw_priv *priv = netdev_priv(ndev);
Mugunthan V Ndf828592012-03-18 20:17:54 +00002293
2294 if (netif_running(ndev))
2295 cpsw_ndo_stop(ndev);
Daniel Mack1e7a2e22013-11-15 08:29:16 +01002296
2297 for_each_slave(priv, soft_reset_slave);
2298
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002299 pm_runtime_put_sync(&pdev->dev);
2300
Mugunthan V N739683b2013-06-06 23:45:14 +05302301 /* Select sleep pin state */
2302 pinctrl_pm_select_sleep_state(&pdev->dev);
2303
Mugunthan V Ndf828592012-03-18 20:17:54 +00002304 return 0;
2305}
2306
2307static int cpsw_resume(struct device *dev)
2308{
2309 struct platform_device *pdev = to_platform_device(dev);
2310 struct net_device *ndev = platform_get_drvdata(pdev);
2311
Mugunthan V Nf150bd72012-07-17 08:09:50 +00002312 pm_runtime_get_sync(&pdev->dev);
Mugunthan V N739683b2013-06-06 23:45:14 +05302313
2314 /* Select default pin state */
2315 pinctrl_pm_select_default_state(&pdev->dev);
2316
Mugunthan V Ndf828592012-03-18 20:17:54 +00002317 if (netif_running(ndev))
2318 cpsw_ndo_open(ndev);
2319 return 0;
2320}
2321
2322static const struct dev_pm_ops cpsw_pm_ops = {
2323 .suspend = cpsw_suspend,
2324 .resume = cpsw_resume,
2325};
2326
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002327static const struct of_device_id cpsw_of_mtable[] = {
2328 { .compatible = "ti,cpsw", },
2329 { /* sentinel */ },
2330};
Sebastian Siewior4bc21d42013-04-24 08:48:22 +00002331MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
Mugunthan V N2eb32b02012-07-30 10:17:14 +00002332
Mugunthan V Ndf828592012-03-18 20:17:54 +00002333static struct platform_driver cpsw_driver = {
2334 .driver = {
2335 .name = "cpsw",
2336 .owner = THIS_MODULE,
2337 .pm = &cpsw_pm_ops,
Sachin Kamat1e5c76d2013-09-30 09:55:12 +05302338 .of_match_table = cpsw_of_mtable,
Mugunthan V Ndf828592012-03-18 20:17:54 +00002339 },
2340 .probe = cpsw_probe,
Bill Pemberton663e12e2012-12-03 09:23:45 -05002341 .remove = cpsw_remove,
Mugunthan V Ndf828592012-03-18 20:17:54 +00002342};
2343
2344static int __init cpsw_init(void)
2345{
2346 return platform_driver_register(&cpsw_driver);
2347}
2348late_initcall(cpsw_init);
2349
2350static void __exit cpsw_exit(void)
2351{
2352 platform_driver_unregister(&cpsw_driver);
2353}
2354module_exit(cpsw_exit);
2355
2356MODULE_LICENSE("GPL");
2357MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2358MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2359MODULE_DESCRIPTION("TI CPSW Ethernet driver");