blob: 03a9c5cad222ab97748196ce699136ccbaceb129 [file] [log] [blame]
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/ktime.h>
Stephen Rothwell568d7c72016-03-17 15:30:49 +110029#include <linux/pagemap.h>
Alex Deucherd38ceaf2015-04-20 16:55:21 -040030#include <drm/drmP.h>
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33
34void amdgpu_gem_object_free(struct drm_gem_object *gobj)
35{
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
37
38 if (robj) {
39 if (robj->gem_base.import_attach)
40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
Christian König9298e522015-06-03 21:31:20 +020041 amdgpu_mn_unregister(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -040042 amdgpu_bo_unref(&robj);
43 }
44}
45
46int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47 int alignment, u32 initial_domain,
48 u64 flags, bool kernel,
49 struct drm_gem_object **obj)
50{
51 struct amdgpu_bo *robj;
52 unsigned long max_size;
53 int r;
54
55 *obj = NULL;
56 /* At least align on page size */
57 if (alignment < PAGE_SIZE) {
58 alignment = PAGE_SIZE;
59 }
60
61 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
62 /* Maximum bo size is the unpinned gtt size since we use the gtt to
63 * handle vram to system pool migrations.
64 */
65 max_size = adev->mc.gtt_size - adev->gart_pin_size;
66 if (size > max_size) {
67 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
68 size >> 20, max_size >> 20);
69 return -ENOMEM;
70 }
71 }
72retry:
Christian König72d76682015-09-03 17:34:59 +020073 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
74 flags, NULL, NULL, &robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -040075 if (r) {
76 if (r != -ERESTARTSYS) {
77 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
78 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
79 goto retry;
80 }
81 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
82 size, initial_domain, alignment, r);
83 }
84 return r;
85 }
86 *obj = &robj->gem_base;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040087
Alex Deucherd38ceaf2015-04-20 16:55:21 -040088 return 0;
89}
90
Christian König418aa0c2016-02-15 16:59:57 +010091void amdgpu_gem_force_release(struct amdgpu_device *adev)
Alex Deucherd38ceaf2015-04-20 16:55:21 -040092{
Christian König418aa0c2016-02-15 16:59:57 +010093 struct drm_device *ddev = adev->ddev;
94 struct drm_file *file;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040095
Daniel Vetter1d2ac402016-04-26 19:29:41 +020096 mutex_lock(&ddev->filelist_mutex);
Christian König418aa0c2016-02-15 16:59:57 +010097
98 list_for_each_entry(file, &ddev->filelist, lhead) {
99 struct drm_gem_object *gobj;
100 int handle;
101
102 WARN_ONCE(1, "Still active user space clients!\n");
103 spin_lock(&file->table_lock);
104 idr_for_each_entry(&file->object_idr, gobj, handle) {
105 WARN_ONCE(1, "And also active allocations!\n");
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200106 drm_gem_object_unreference_unlocked(gobj);
Christian König418aa0c2016-02-15 16:59:57 +0100107 }
108 idr_destroy(&file->object_idr);
109 spin_unlock(&file->table_lock);
110 }
111
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200112 mutex_unlock(&ddev->filelist_mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400113}
114
115/*
116 * Call from drm_gem_handle_create which appear in both new and open ioctl
117 * case.
118 */
Christian Königa7d64de2016-09-15 14:58:48 +0200119int amdgpu_gem_object_open(struct drm_gem_object *obj,
120 struct drm_file *file_priv)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400121{
Christian König765e7fb2016-09-15 15:06:50 +0200122 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
Christian Königa7d64de2016-09-15 14:58:48 +0200123 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400124 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
125 struct amdgpu_vm *vm = &fpriv->vm;
126 struct amdgpu_bo_va *bo_va;
127 int r;
Christian König765e7fb2016-09-15 15:06:50 +0200128 r = amdgpu_bo_reserve(abo, false);
Chunming Zhoue98c1b02015-11-13 15:22:04 +0800129 if (r)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400130 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400131
Christian König765e7fb2016-09-15 15:06:50 +0200132 bo_va = amdgpu_vm_bo_find(vm, abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400133 if (!bo_va) {
Christian König765e7fb2016-09-15 15:06:50 +0200134 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400135 } else {
136 ++bo_va->ref_count;
137 }
Christian König765e7fb2016-09-15 15:06:50 +0200138 amdgpu_bo_unreserve(abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400139 return 0;
140}
141
142void amdgpu_gem_object_close(struct drm_gem_object *obj,
143 struct drm_file *file_priv)
144{
Christian Königb5a5ec52016-03-08 17:47:46 +0100145 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
Christian Königa7d64de2016-09-15 14:58:48 +0200146 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400147 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
148 struct amdgpu_vm *vm = &fpriv->vm;
Christian Königb5a5ec52016-03-08 17:47:46 +0100149
150 struct amdgpu_bo_list_entry vm_pd;
151 struct list_head list, duplicates;
152 struct ttm_validate_buffer tv;
153 struct ww_acquire_ctx ticket;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400154 struct amdgpu_bo_va *bo_va;
Nicolai Hähnle23e05632017-03-23 19:34:11 +0100155 struct dma_fence *fence = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400156 int r;
Christian Königb5a5ec52016-03-08 17:47:46 +0100157
158 INIT_LIST_HEAD(&list);
159 INIT_LIST_HEAD(&duplicates);
160
161 tv.bo = &bo->tbo;
162 tv.shared = true;
163 list_add(&tv.head, &list);
164
165 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
166
Christian König35264f62016-03-17 17:14:10 +0100167 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400168 if (r) {
169 dev_err(adev->dev, "leaking bo va because "
170 "we fail to reserve bo (%d)\n", r);
171 return;
172 }
Christian Königb5a5ec52016-03-08 17:47:46 +0100173 bo_va = amdgpu_vm_bo_find(vm, bo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400174 if (bo_va) {
175 if (--bo_va->ref_count == 0) {
176 amdgpu_vm_bo_rmv(adev, bo_va);
Nicolai Hähnle23e05632017-03-23 19:34:11 +0100177
178 r = amdgpu_vm_clear_freed(adev, vm, &fence);
179 if (unlikely(r)) {
180 dev_err(adev->dev, "failed to clear page "
181 "tables on GEM object close (%d)\n", r);
182 }
183
184 if (fence) {
185 amdgpu_bo_fence(bo, fence, true);
186 dma_fence_put(fence);
187 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400188 }
189 }
Christian Königb5a5ec52016-03-08 17:47:46 +0100190 ttm_eu_backoff_reservation(&ticket, &list);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400191}
192
193static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
194{
195 if (r == -EDEADLK) {
196 r = amdgpu_gpu_reset(adev);
197 if (!r)
198 r = -EAGAIN;
199 }
200 return r;
201}
202
203/*
204 * GEM ioctls.
205 */
206int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
207 struct drm_file *filp)
208{
209 struct amdgpu_device *adev = dev->dev_private;
210 union drm_amdgpu_gem_create *args = data;
211 uint64_t size = args->in.bo_size;
212 struct drm_gem_object *gobj;
213 uint32_t handle;
214 bool kernel = false;
215 int r;
216
Alex Deucher834e0f82017-03-08 17:40:17 -0500217 /* reject invalid gem flags */
218 if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
219 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
220 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
221 AMDGPU_GEM_CREATE_VRAM_CLEARED|
222 AMDGPU_GEM_CREATE_SHADOW |
223 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
224 r = -EINVAL;
225 goto error_unlock;
226 }
227 /* reject invalid gem domains */
228 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
229 AMDGPU_GEM_DOMAIN_GTT |
230 AMDGPU_GEM_DOMAIN_VRAM |
231 AMDGPU_GEM_DOMAIN_GDS |
232 AMDGPU_GEM_DOMAIN_GWS |
233 AMDGPU_GEM_DOMAIN_OA)) {
234 r = -EINVAL;
235 goto error_unlock;
236 }
237
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400238 /* create a gem object to contain this object in */
239 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
240 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
241 kernel = true;
242 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
243 size = size << AMDGPU_GDS_SHIFT;
244 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
245 size = size << AMDGPU_GWS_SHIFT;
246 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
247 size = size << AMDGPU_OA_SHIFT;
248 else {
249 r = -EINVAL;
250 goto error_unlock;
251 }
252 }
253 size = roundup(size, PAGE_SIZE);
254
255 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
256 (u32)(0xffffffff & args->in.domains),
257 args->in.domain_flags,
258 kernel, &gobj);
259 if (r)
260 goto error_unlock;
261
262 r = drm_gem_handle_create(filp, gobj, &handle);
263 /* drop reference from allocate - handle holds it now */
264 drm_gem_object_unreference_unlocked(gobj);
265 if (r)
266 goto error_unlock;
267
268 memset(args, 0, sizeof(*args));
269 args->out.handle = handle;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400270 return 0;
271
272error_unlock:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400273 r = amdgpu_gem_handle_lockup(adev, r);
274 return r;
275}
276
277int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
278 struct drm_file *filp)
279{
280 struct amdgpu_device *adev = dev->dev_private;
281 struct drm_amdgpu_gem_userptr *args = data;
282 struct drm_gem_object *gobj;
283 struct amdgpu_bo *bo;
284 uint32_t handle;
285 int r;
286
287 if (offset_in_page(args->addr | args->size))
288 return -EINVAL;
289
290 /* reject unknown flag values */
291 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
292 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
293 AMDGPU_GEM_USERPTR_REGISTER))
294 return -EINVAL;
295
Christian König358c2582016-03-11 15:29:27 +0100296 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
297 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400298
Christian König358c2582016-03-11 15:29:27 +0100299 /* if we want to write to it we must install a MMU notifier */
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400300 return -EACCES;
301 }
302
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400303 /* create a gem object to contain this object in */
304 r = amdgpu_gem_object_create(adev, args->size, 0,
305 AMDGPU_GEM_DOMAIN_CPU, 0,
306 0, &gobj);
307 if (r)
308 goto handle_lockup;
309
310 bo = gem_to_amdgpu_bo(gobj);
Christian König1ea863f2015-12-18 22:13:12 +0100311 bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
312 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400313 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
314 if (r)
315 goto release_object;
316
317 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
318 r = amdgpu_mn_register(bo, args->addr);
319 if (r)
320 goto release_object;
321 }
322
323 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
324 down_read(&current->mm->mmap_sem);
Christian König2f568db2016-02-23 12:36:59 +0100325
326 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
327 bo->tbo.ttm->pages);
328 if (r)
329 goto unlock_mmap_sem;
330
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400331 r = amdgpu_bo_reserve(bo, true);
Christian König2f568db2016-02-23 12:36:59 +0100332 if (r)
333 goto free_pages;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400334
335 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
336 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
337 amdgpu_bo_unreserve(bo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400338 if (r)
Christian König2f568db2016-02-23 12:36:59 +0100339 goto free_pages;
340
341 up_read(&current->mm->mmap_sem);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400342 }
343
344 r = drm_gem_handle_create(filp, gobj, &handle);
345 /* drop reference from allocate - handle holds it now */
346 drm_gem_object_unreference_unlocked(gobj);
347 if (r)
348 goto handle_lockup;
349
350 args->handle = handle;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400351 return 0;
352
Christian König2f568db2016-02-23 12:36:59 +0100353free_pages:
354 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
355
356unlock_mmap_sem:
357 up_read(&current->mm->mmap_sem);
358
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400359release_object:
360 drm_gem_object_unreference_unlocked(gobj);
361
362handle_lockup:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400363 r = amdgpu_gem_handle_lockup(adev, r);
364
365 return r;
366}
367
368int amdgpu_mode_dumb_mmap(struct drm_file *filp,
369 struct drm_device *dev,
370 uint32_t handle, uint64_t *offset_p)
371{
372 struct drm_gem_object *gobj;
373 struct amdgpu_bo *robj;
374
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100375 gobj = drm_gem_object_lookup(filp, handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400376 if (gobj == NULL) {
377 return -ENOENT;
378 }
379 robj = gem_to_amdgpu_bo(gobj);
Christian Königcc325d12016-02-08 11:08:35 +0100380 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
Christian König271c8122015-05-13 14:30:53 +0200381 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400382 drm_gem_object_unreference_unlocked(gobj);
383 return -EPERM;
384 }
385 *offset_p = amdgpu_bo_mmap_offset(robj);
386 drm_gem_object_unreference_unlocked(gobj);
387 return 0;
388}
389
390int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
391 struct drm_file *filp)
392{
393 union drm_amdgpu_gem_mmap *args = data;
394 uint32_t handle = args->in.handle;
395 memset(args, 0, sizeof(*args));
396 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
397}
398
399/**
400 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
401 *
402 * @timeout_ns: timeout in ns
403 *
404 * Calculate the timeout in jiffies from an absolute timeout in ns.
405 */
406unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
407{
408 unsigned long timeout_jiffies;
409 ktime_t timeout;
410
411 /* clamp timeout if it's to large */
412 if (((int64_t)timeout_ns) < 0)
413 return MAX_SCHEDULE_TIMEOUT;
414
Christian König0f117702015-07-08 16:58:48 +0200415 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400416 if (ktime_to_ns(timeout) < 0)
417 return 0;
418
419 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
420 /* clamp timeout to avoid unsigned-> signed overflow */
421 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
422 return MAX_SCHEDULE_TIMEOUT - 1;
423
424 return timeout_jiffies;
425}
426
427int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
428 struct drm_file *filp)
429{
430 struct amdgpu_device *adev = dev->dev_private;
431 union drm_amdgpu_gem_wait_idle *args = data;
432 struct drm_gem_object *gobj;
433 struct amdgpu_bo *robj;
434 uint32_t handle = args->in.handle;
435 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
436 int r = 0;
437 long ret;
438
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100439 gobj = drm_gem_object_lookup(filp, handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400440 if (gobj == NULL) {
441 return -ENOENT;
442 }
443 robj = gem_to_amdgpu_bo(gobj);
Chris Wilson0fea2ed2016-08-29 08:08:24 +0100444 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
445 timeout);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400446
447 /* ret == 0 means not signaled,
448 * ret > 0 means signaled
449 * ret < 0 means interrupted before timeout
450 */
451 if (ret >= 0) {
452 memset(args, 0, sizeof(*args));
453 args->out.status = (ret == 0);
454 } else
455 r = ret;
456
457 drm_gem_object_unreference_unlocked(gobj);
458 r = amdgpu_gem_handle_lockup(adev, r);
459 return r;
460}
461
462int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
463 struct drm_file *filp)
464{
465 struct drm_amdgpu_gem_metadata *args = data;
466 struct drm_gem_object *gobj;
467 struct amdgpu_bo *robj;
468 int r = -1;
469
470 DRM_DEBUG("%d \n", args->handle);
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100471 gobj = drm_gem_object_lookup(filp, args->handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400472 if (gobj == NULL)
473 return -ENOENT;
474 robj = gem_to_amdgpu_bo(gobj);
475
476 r = amdgpu_bo_reserve(robj, false);
477 if (unlikely(r != 0))
478 goto out;
479
480 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
481 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
482 r = amdgpu_bo_get_metadata(robj, args->data.data,
483 sizeof(args->data.data),
484 &args->data.data_size_bytes,
485 &args->data.flags);
486 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
Dan Carpenter0913eab2015-09-23 14:00:35 +0300487 if (args->data.data_size_bytes > sizeof(args->data.data)) {
488 r = -EINVAL;
489 goto unreserve;
490 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400491 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
492 if (!r)
493 r = amdgpu_bo_set_metadata(robj, args->data.data,
494 args->data.data_size_bytes,
495 args->data.flags);
496 }
497
Dan Carpenter0913eab2015-09-23 14:00:35 +0300498unreserve:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400499 amdgpu_bo_unreserve(robj);
500out:
501 drm_gem_object_unreference_unlocked(gobj);
502 return r;
503}
504
Christian Königf7da30d2016-09-28 12:03:04 +0200505static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo)
506{
Christian Königf7da30d2016-09-28 12:03:04 +0200507 /* if anything is swapped out don't swap it in here,
508 just abort and wait for the next CS */
Nicolai Hähnle3e19e692016-12-12 11:53:11 +0100509 if (!amdgpu_bo_gpu_accessible(bo))
510 return -ERESTARTSYS;
Christian Königf7da30d2016-09-28 12:03:04 +0200511
Nicolai Hähnle3e19e692016-12-12 11:53:11 +0100512 if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
513 return -ERESTARTSYS;
514
515 return 0;
Christian Königf7da30d2016-09-28 12:03:04 +0200516}
517
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400518/**
519 * amdgpu_gem_va_update_vm -update the bo_va in its VM
520 *
521 * @adev: amdgpu_device pointer
Christian Königdc54d3d2017-03-13 10:13:38 +0100522 * @vm: vm to update
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400523 * @bo_va: bo_va to update
Christian König2ffdaaf2017-01-27 15:58:43 +0100524 * @list: validation list
Christian Königdc54d3d2017-03-13 10:13:38 +0100525 * @operation: map, unmap or clear
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400526 *
Christian König2ffdaaf2017-01-27 15:58:43 +0100527 * Update the bo_va directly after setting its address. Errors are not
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400528 * vital here, so they are not reported back to userspace.
529 */
530static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
Christian Königdc54d3d2017-03-13 10:13:38 +0100531 struct amdgpu_vm *vm,
Christian Königf7da30d2016-09-28 12:03:04 +0200532 struct amdgpu_bo_va *bo_va,
Christian König2ffdaaf2017-01-27 15:58:43 +0100533 struct list_head *list,
Christian Königf7da30d2016-09-28 12:03:04 +0200534 uint32_t operation)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400535{
Christian König2ffdaaf2017-01-27 15:58:43 +0100536 struct ttm_validate_buffer *entry;
537 int r = -ERESTARTSYS;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400538
Christian König2ffdaaf2017-01-27 15:58:43 +0100539 list_for_each_entry(entry, list, head) {
Nicolai Hähnled1144b82016-12-12 12:09:12 +0100540 struct amdgpu_bo *bo =
541 container_of(entry->bo, struct amdgpu_bo, tbo);
Samuel Pitoiseta73effa2017-02-09 23:28:24 +0100542 if (amdgpu_gem_va_check(NULL, bo))
Christian König2ffdaaf2017-01-27 15:58:43 +0100543 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400544 }
Nicolai Hähnled1144b82016-12-12 12:09:12 +0100545
Christian Königdc54d3d2017-03-13 10:13:38 +0100546 r = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_va_check,
Christian Königf7da30d2016-09-28 12:03:04 +0200547 NULL);
548 if (r)
Christian König2ffdaaf2017-01-27 15:58:43 +0100549 goto error;
Chunming Zhoue410b5c2015-12-07 15:02:52 +0800550
Christian König194d2162016-10-12 15:13:52 +0200551 r = amdgpu_vm_update_directories(adev, vm);
Chunming Zhou43c27fb2015-11-12 15:33:09 +0800552 if (r)
Christian König2ffdaaf2017-01-27 15:58:43 +0100553 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400554
Nicolai Hähnlef3467812017-03-23 19:36:31 +0100555 r = amdgpu_vm_clear_freed(adev, vm, NULL);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400556 if (r)
Christian König2ffdaaf2017-01-27 15:58:43 +0100557 goto error;
monk.liu194a3362015-07-22 13:29:28 +0800558
Christian König80f95c52017-03-13 10:13:39 +0100559 if (operation == AMDGPU_VA_OP_MAP ||
560 operation == AMDGPU_VA_OP_REPLACE)
Flora Cui05dcb5c2016-09-22 11:34:47 +0800561 r = amdgpu_vm_bo_update(adev, bo_va, false);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400562
Christian König2ffdaaf2017-01-27 15:58:43 +0100563error:
Christian König68fdd3d2015-06-16 14:50:02 +0200564 if (r && r != -ERESTARTSYS)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400565 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
566}
567
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400568int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
569 struct drm_file *filp)
570{
Junwei Zhangb85891b2017-01-16 13:59:01 +0800571 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
572 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
Alex Xie66e02bc2017-02-14 12:04:52 -0500573 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
Junwei Zhangb85891b2017-01-16 13:59:01 +0800574 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
575 AMDGPU_VM_PAGE_PRT;
576
Christian König34b5f6a2015-06-08 15:03:00 +0200577 struct drm_amdgpu_gem_va *args = data;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400578 struct drm_gem_object *gobj;
579 struct amdgpu_device *adev = dev->dev_private;
580 struct amdgpu_fpriv *fpriv = filp->driver_priv;
Christian König765e7fb2016-09-15 15:06:50 +0200581 struct amdgpu_bo *abo;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400582 struct amdgpu_bo_va *bo_va;
Christian Königb88c8792016-09-28 16:33:01 +0200583 struct amdgpu_bo_list_entry vm_pd;
584 struct ttm_validate_buffer tv;
Chunming Zhou49b02b12015-11-13 14:18:38 +0800585 struct ww_acquire_ctx ticket;
Christian Königd7d29552017-01-30 10:24:13 +0100586 struct list_head list;
Alex Xie54635452017-02-14 12:22:57 -0500587 uint64_t va_flags;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400588 int r = 0;
589
Christian König34b5f6a2015-06-08 15:03:00 +0200590 if (!adev->vm_manager.enabled)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400591 return -ENOTTY;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400592
Christian König34b5f6a2015-06-08 15:03:00 +0200593 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400594 dev_err(&dev->pdev->dev,
595 "va_address 0x%lX is in reserved area 0x%X\n",
Christian König34b5f6a2015-06-08 15:03:00 +0200596 (unsigned long)args->va_address,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400597 AMDGPU_VA_RESERVED_SIZE);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400598 return -EINVAL;
599 }
600
Junwei Zhangb85891b2017-01-16 13:59:01 +0800601 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
602 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
603 args->flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400604 return -EINVAL;
605 }
606
Christian König34b5f6a2015-06-08 15:03:00 +0200607 switch (args->operation) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400608 case AMDGPU_VA_OP_MAP:
609 case AMDGPU_VA_OP_UNMAP:
Christian Königdc54d3d2017-03-13 10:13:38 +0100610 case AMDGPU_VA_OP_CLEAR:
Christian König80f95c52017-03-13 10:13:39 +0100611 case AMDGPU_VA_OP_REPLACE:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400612 break;
613 default:
614 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
Christian König34b5f6a2015-06-08 15:03:00 +0200615 args->operation);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400616 return -EINVAL;
617 }
618
Chunming Zhou49b02b12015-11-13 14:18:38 +0800619 INIT_LIST_HEAD(&list);
Christian Königdc54d3d2017-03-13 10:13:38 +0100620 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
621 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
Junwei Zhangb85891b2017-01-16 13:59:01 +0800622 gobj = drm_gem_object_lookup(filp, args->handle);
623 if (gobj == NULL)
624 return -ENOENT;
625 abo = gem_to_amdgpu_bo(gobj);
626 tv.bo = &abo->tbo;
627 tv.shared = false;
628 list_add(&tv.head, &list);
629 } else {
630 gobj = NULL;
631 abo = NULL;
632 }
Chunming Zhou49b02b12015-11-13 14:18:38 +0800633
Christian Königb88c8792016-09-28 16:33:01 +0200634 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
Christian Königb5a5ec52016-03-08 17:47:46 +0100635
Christian Königd7d29552017-01-30 10:24:13 +0100636 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
Junwei Zhangb85891b2017-01-16 13:59:01 +0800637 if (r)
638 goto error_unref;
Christian König34b5f6a2015-06-08 15:03:00 +0200639
Junwei Zhangb85891b2017-01-16 13:59:01 +0800640 if (abo) {
641 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
642 if (!bo_va) {
643 r = -ENOENT;
644 goto error_backoff;
645 }
Christian Königdc54d3d2017-03-13 10:13:38 +0100646 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
Junwei Zhangb85891b2017-01-16 13:59:01 +0800647 bo_va = fpriv->prt_va;
Christian Königdc54d3d2017-03-13 10:13:38 +0100648 } else {
649 bo_va = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400650 }
651
Christian König34b5f6a2015-06-08 15:03:00 +0200652 switch (args->operation) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400653 case AMDGPU_VA_OP_MAP:
Christian König663e4572017-03-13 10:13:37 +0100654 r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address,
655 args->map_size);
656 if (r)
657 goto error_backoff;
Alex Xie54635452017-02-14 12:22:57 -0500658
Christian König663e4572017-03-13 10:13:37 +0100659 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
Christian König34b5f6a2015-06-08 15:03:00 +0200660 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
661 args->offset_in_bo, args->map_size,
Christian König9f7eb532015-05-18 16:05:57 +0200662 va_flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400663 break;
664 case AMDGPU_VA_OP_UNMAP:
Christian König34b5f6a2015-06-08 15:03:00 +0200665 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400666 break;
Christian Königdc54d3d2017-03-13 10:13:38 +0100667
668 case AMDGPU_VA_OP_CLEAR:
669 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
670 args->va_address,
671 args->map_size);
672 break;
Christian König80f95c52017-03-13 10:13:39 +0100673 case AMDGPU_VA_OP_REPLACE:
674 r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address,
675 args->map_size);
676 if (r)
677 goto error_backoff;
678
679 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
680 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
681 args->offset_in_bo, args->map_size,
682 va_flags);
683 break;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400684 default:
685 break;
686 }
Junwei Zhangb85891b2017-01-16 13:59:01 +0800687 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
Christian Königdc54d3d2017-03-13 10:13:38 +0100688 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
689 args->operation);
Junwei Zhangb85891b2017-01-16 13:59:01 +0800690
691error_backoff:
Christian König2ffdaaf2017-01-27 15:58:43 +0100692 ttm_eu_backoff_reservation(&ticket, &list);
Chunming Zhoue98c1b02015-11-13 15:22:04 +0800693
Junwei Zhangb85891b2017-01-16 13:59:01 +0800694error_unref:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400695 drm_gem_object_unreference_unlocked(gobj);
696 return r;
697}
698
699int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
700 struct drm_file *filp)
701{
702 struct drm_amdgpu_gem_op *args = data;
703 struct drm_gem_object *gobj;
704 struct amdgpu_bo *robj;
705 int r;
706
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100707 gobj = drm_gem_object_lookup(filp, args->handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400708 if (gobj == NULL) {
709 return -ENOENT;
710 }
711 robj = gem_to_amdgpu_bo(gobj);
712
713 r = amdgpu_bo_reserve(robj, false);
714 if (unlikely(r))
715 goto out;
716
717 switch (args->op) {
718 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
719 struct drm_amdgpu_gem_create_in info;
Alex Xieec2c4672017-04-05 16:33:00 -0400720 void __user *out = (void __user *)(uintptr_t)args->value;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400721
722 info.bo_size = robj->gem_base.size;
723 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
Christian König1ea863f2015-12-18 22:13:12 +0100724 info.domains = robj->prefered_domains;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400725 info.domain_flags = robj->flags;
Christian König4c28fb02015-08-28 17:27:54 +0200726 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400727 if (copy_to_user(out, &info, sizeof(info)))
728 r = -EFAULT;
729 break;
730 }
Marek Olšákd8f65a22015-05-27 14:30:38 +0200731 case AMDGPU_GEM_OP_SET_PLACEMENT:
Christopher James Halse Rogers803d89a2017-04-03 13:31:22 +1000732 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
733 r = -EINVAL;
734 amdgpu_bo_unreserve(robj);
735 break;
736 }
Christian Königcc325d12016-02-08 11:08:35 +0100737 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400738 r = -EPERM;
Christian König4c28fb02015-08-28 17:27:54 +0200739 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400740 break;
741 }
Christian König1ea863f2015-12-18 22:13:12 +0100742 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
743 AMDGPU_GEM_DOMAIN_GTT |
744 AMDGPU_GEM_DOMAIN_CPU);
745 robj->allowed_domains = robj->prefered_domains;
746 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
747 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
748
Christian König4c28fb02015-08-28 17:27:54 +0200749 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400750 break;
751 default:
Christian König4c28fb02015-08-28 17:27:54 +0200752 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400753 r = -EINVAL;
754 }
755
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400756out:
757 drm_gem_object_unreference_unlocked(gobj);
758 return r;
759}
760
761int amdgpu_mode_dumb_create(struct drm_file *file_priv,
762 struct drm_device *dev,
763 struct drm_mode_create_dumb *args)
764{
765 struct amdgpu_device *adev = dev->dev_private;
766 struct drm_gem_object *gobj;
767 uint32_t handle;
768 int r;
769
Laurent Pinchart8e911ab2016-10-18 01:41:17 +0300770 args->pitch = amdgpu_align_pitch(adev, args->width,
771 DIV_ROUND_UP(args->bpp, 8), 0);
Dan Carpenter54ef0b52015-09-23 14:00:59 +0300772 args->size = (u64)args->pitch * args->height;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400773 args->size = ALIGN(args->size, PAGE_SIZE);
774
775 r = amdgpu_gem_object_create(adev, args->size, 0,
776 AMDGPU_GEM_DOMAIN_VRAM,
Alex Deucher857d9132015-08-27 00:14:16 -0400777 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
778 ttm_bo_type_device,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400779 &gobj);
780 if (r)
781 return -ENOMEM;
782
783 r = drm_gem_handle_create(file_priv, gobj, &handle);
784 /* drop reference from allocate - handle holds it now */
785 drm_gem_object_unreference_unlocked(gobj);
786 if (r) {
787 return r;
788 }
789 args->handle = handle;
790 return 0;
791}
792
793#if defined(CONFIG_DEBUG_FS)
Christian König7ea23562016-02-15 15:23:00 +0100794static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
795{
796 struct drm_gem_object *gobj = ptr;
797 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
798 struct seq_file *m = data;
799
800 unsigned domain;
801 const char *placement;
802 unsigned pin_count;
803
804 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
805 switch (domain) {
806 case AMDGPU_GEM_DOMAIN_VRAM:
807 placement = "VRAM";
808 break;
809 case AMDGPU_GEM_DOMAIN_GTT:
810 placement = " GTT";
811 break;
812 case AMDGPU_GEM_DOMAIN_CPU:
813 default:
814 placement = " CPU";
815 break;
816 }
817 seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
818 id, amdgpu_bo_size(bo), placement,
819 amdgpu_bo_gpu_offset(bo));
820
821 pin_count = ACCESS_ONCE(bo->pin_count);
822 if (pin_count)
823 seq_printf(m, " pin count %d", pin_count);
824 seq_printf(m, "\n");
825
826 return 0;
827}
828
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400829static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
830{
831 struct drm_info_node *node = (struct drm_info_node *)m->private;
832 struct drm_device *dev = node->minor->dev;
Christian König7ea23562016-02-15 15:23:00 +0100833 struct drm_file *file;
834 int r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400835
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200836 r = mutex_lock_interruptible(&dev->filelist_mutex);
Christian König7ea23562016-02-15 15:23:00 +0100837 if (r)
838 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400839
Christian König7ea23562016-02-15 15:23:00 +0100840 list_for_each_entry(file, &dev->filelist, lhead) {
841 struct task_struct *task;
Christian Königb22e3ce2016-02-15 12:41:37 +0100842
Christian König7ea23562016-02-15 15:23:00 +0100843 /*
844 * Although we have a valid reference on file->pid, that does
845 * not guarantee that the task_struct who called get_pid() is
846 * still alive (e.g. get_pid(current) => fork() => exit()).
847 * Therefore, we need to protect this ->comm access using RCU.
848 */
849 rcu_read_lock();
850 task = pid_task(file->pid, PIDTYPE_PID);
851 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
852 task ? task->comm : "<unknown>");
853 rcu_read_unlock();
854
855 spin_lock(&file->table_lock);
856 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
857 spin_unlock(&file->table_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400858 }
Christian König7ea23562016-02-15 15:23:00 +0100859
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200860 mutex_unlock(&dev->filelist_mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400861 return 0;
862}
863
Nils Wallménius06ab6832016-05-02 12:46:15 -0400864static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400865 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
866};
867#endif
868
869int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
870{
871#if defined(CONFIG_DEBUG_FS)
872 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
873#endif
874 return 0;
875}