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gerrit-public.fairphone.software / kernel / msm-4.19 / 8080699a3649cb0a0aed2c650a7a3a76c2025b30 / . / sound / soc / codecs / rt5663.c
blob: b036c9dc0c8cf1883dd550a6755ae61c7a81e87d [file] [log] [blame]
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1/*
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/acpi.h>
20#include <linux/workqueue.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5663.h"
31#include "rl6231.h"
32
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]33#define RT5663_DEVICE_ID_2 0x6451
34#define RT5663_DEVICE_ID_1 0x6406
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]35
36enum {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]37 CODEC_VER_1,
38 CODEC_VER_0,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]39};
40
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]41struct impedance_mapping_table {
42 unsigned int imp_min;
43 unsigned int imp_max;
44 unsigned int vol;
45 unsigned int dc_offset_l_manual;
46 unsigned int dc_offset_r_manual;
47 unsigned int dc_offset_l_manual_mic;
48 unsigned int dc_offset_r_manual_mic;
49};
50
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]51struct rt5663_priv {
52 struct snd_soc_codec *codec;
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]53 struct rt5663_platform_data pdata;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]54 struct regmap *regmap;
oder_chiou@realtek.comde6ae8a2017-11-10 13:16:44 +0800[diff] [blame]55 struct delayed_work jack_detect_work, jd_unplug_work;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]56 struct snd_soc_jack *hs_jack;
57 struct timer_list btn_check_timer;
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]58 struct impedance_mapping_table *imp_table;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]59
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]60 int codec_ver;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]61 int sysclk;
62 int sysclk_src;
63 int lrck;
64
65 int pll_src;
66 int pll_in;
67 int pll_out;
68
69 int jack_type;
70};
71
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]72static const struct reg_sequence rt5663_patch_list[] = {
oder_chiou@realtek.com1d5c5b62017-07-19 10:20:23 +0800[diff] [blame]73 { 0x002a, 0x8020 },
oder_chiou@realtek.comd26ed932017-07-18 10:12:58 +0800[diff] [blame]74 { 0x0086, 0x0028 },
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]75};
76
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]77static const struct reg_default rt5663_v2_reg[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]78 { 0x0000, 0x0000 },
79 { 0x0001, 0xc8c8 },
80 { 0x0002, 0x8080 },
81 { 0x0003, 0x8000 },
82 { 0x0004, 0xc80a },
83 { 0x0005, 0x0000 },
84 { 0x0006, 0x0000 },
85 { 0x0007, 0x0000 },
86 { 0x000a, 0x0000 },
87 { 0x000b, 0x0000 },
88 { 0x000c, 0x0000 },
89 { 0x000d, 0x0000 },
90 { 0x000f, 0x0808 },
91 { 0x0010, 0x4000 },
92 { 0x0011, 0x0000 },
93 { 0x0012, 0x1404 },
94 { 0x0013, 0x1000 },
95 { 0x0014, 0xa00a },
96 { 0x0015, 0x0404 },
97 { 0x0016, 0x0404 },
98 { 0x0017, 0x0011 },
99 { 0x0018, 0xafaf },
100 { 0x0019, 0xafaf },
101 { 0x001a, 0xafaf },
102 { 0x001b, 0x0011 },
103 { 0x001c, 0x2f2f },
104 { 0x001d, 0x2f2f },
105 { 0x001e, 0x2f2f },
106 { 0x001f, 0x0000 },
107 { 0x0020, 0x0000 },
108 { 0x0021, 0x0000 },
109 { 0x0022, 0x5757 },
110 { 0x0023, 0x0039 },
111 { 0x0024, 0x000b },
112 { 0x0026, 0xc0c0 },
113 { 0x0027, 0xc0c0 },
114 { 0x0028, 0xc0c0 },
115 { 0x0029, 0x8080 },
116 { 0x002a, 0xaaaa },
117 { 0x002b, 0xaaaa },
118 { 0x002c, 0xaba8 },
119 { 0x002d, 0x0000 },
120 { 0x002e, 0x0000 },
121 { 0x002f, 0x0000 },
122 { 0x0030, 0x0000 },
123 { 0x0031, 0x5000 },
124 { 0x0032, 0x0000 },
125 { 0x0033, 0x0000 },
126 { 0x0034, 0x0000 },
127 { 0x0035, 0x0000 },
128 { 0x003a, 0x0000 },
129 { 0x003b, 0x0000 },
130 { 0x003c, 0x00ff },
131 { 0x003d, 0x0000 },
132 { 0x003e, 0x00ff },
133 { 0x003f, 0x0000 },
134 { 0x0040, 0x0000 },
135 { 0x0041, 0x00ff },
136 { 0x0042, 0x0000 },
137 { 0x0043, 0x00ff },
138 { 0x0044, 0x0c0c },
139 { 0x0049, 0xc00b },
140 { 0x004a, 0x0000 },
141 { 0x004b, 0x031f },
142 { 0x004d, 0x0000 },
143 { 0x004e, 0x001f },
144 { 0x004f, 0x0000 },
145 { 0x0050, 0x001f },
146 { 0x0052, 0xf000 },
147 { 0x0061, 0x0000 },
148 { 0x0062, 0x0000 },
149 { 0x0063, 0x003e },
150 { 0x0064, 0x0000 },
151 { 0x0065, 0x0000 },
152 { 0x0066, 0x003f },
153 { 0x0067, 0x0000 },
154 { 0x006b, 0x0000 },
155 { 0x006d, 0xff00 },
156 { 0x006e, 0x2808 },
157 { 0x006f, 0x000a },
158 { 0x0070, 0x8000 },
159 { 0x0071, 0x8000 },
160 { 0x0072, 0x8000 },
161 { 0x0073, 0x7000 },
162 { 0x0074, 0x7770 },
163 { 0x0075, 0x0002 },
164 { 0x0076, 0x0001 },
165 { 0x0078, 0x00f0 },
166 { 0x0079, 0x0000 },
167 { 0x007a, 0x0000 },
168 { 0x007b, 0x0000 },
169 { 0x007c, 0x0000 },
170 { 0x007d, 0x0123 },
171 { 0x007e, 0x4500 },
172 { 0x007f, 0x8003 },
173 { 0x0080, 0x0000 },
174 { 0x0081, 0x0000 },
175 { 0x0082, 0x0000 },
176 { 0x0083, 0x0000 },
177 { 0x0084, 0x0000 },
178 { 0x0085, 0x0000 },
179 { 0x0086, 0x0008 },
180 { 0x0087, 0x0000 },
181 { 0x0088, 0x0000 },
182 { 0x0089, 0x0000 },
183 { 0x008a, 0x0000 },
184 { 0x008b, 0x0000 },
185 { 0x008c, 0x0003 },
186 { 0x008e, 0x0060 },
187 { 0x008f, 0x1000 },
188 { 0x0091, 0x0c26 },
189 { 0x0092, 0x0073 },
190 { 0x0093, 0x0000 },
191 { 0x0094, 0x0080 },
192 { 0x0098, 0x0000 },
193 { 0x0099, 0x0000 },
194 { 0x009a, 0x0007 },
195 { 0x009f, 0x0000 },
196 { 0x00a0, 0x0000 },
197 { 0x00a1, 0x0002 },
198 { 0x00a2, 0x0001 },
199 { 0x00a3, 0x0002 },
200 { 0x00a4, 0x0001 },
201 { 0x00ae, 0x2040 },
202 { 0x00af, 0x0000 },
203 { 0x00b6, 0x0000 },
204 { 0x00b7, 0x0000 },
205 { 0x00b8, 0x0000 },
206 { 0x00b9, 0x0000 },
207 { 0x00ba, 0x0002 },
208 { 0x00bb, 0x0000 },
209 { 0x00be, 0x0000 },
210 { 0x00c0, 0x0000 },
211 { 0x00c1, 0x0aaa },
212 { 0x00c2, 0xaa80 },
213 { 0x00c3, 0x0003 },
214 { 0x00c4, 0x0000 },
215 { 0x00d0, 0x0000 },
216 { 0x00d1, 0x2244 },
217 { 0x00d2, 0x0000 },
218 { 0x00d3, 0x3300 },
219 { 0x00d4, 0x2200 },
220 { 0x00d9, 0x0809 },
221 { 0x00da, 0x0000 },
222 { 0x00db, 0x0008 },
223 { 0x00dc, 0x00c0 },
224 { 0x00dd, 0x6724 },
225 { 0x00de, 0x3131 },
226 { 0x00df, 0x0008 },
227 { 0x00e0, 0x4000 },
228 { 0x00e1, 0x3131 },
229 { 0x00e2, 0x600c },
230 { 0x00ea, 0xb320 },
231 { 0x00eb, 0x0000 },
232 { 0x00ec, 0xb300 },
233 { 0x00ed, 0x0000 },
234 { 0x00ee, 0xb320 },
235 { 0x00ef, 0x0000 },
236 { 0x00f0, 0x0201 },
237 { 0x00f1, 0x0ddd },
238 { 0x00f2, 0x0ddd },
239 { 0x00f6, 0x0000 },
240 { 0x00f7, 0x0000 },
241 { 0x00f8, 0x0000 },
242 { 0x00fa, 0x0000 },
243 { 0x00fb, 0x0000 },
244 { 0x00fc, 0x0000 },
245 { 0x00fd, 0x0000 },
246 { 0x00fe, 0x10ec },
247 { 0x00ff, 0x6451 },
248 { 0x0100, 0xaaaa },
249 { 0x0101, 0x000a },
250 { 0x010a, 0xaaaa },
251 { 0x010b, 0xa0a0 },
252 { 0x010c, 0xaeae },
253 { 0x010d, 0xaaaa },
254 { 0x010e, 0xaaaa },
255 { 0x010f, 0xaaaa },
256 { 0x0110, 0xe002 },
257 { 0x0111, 0xa602 },
258 { 0x0112, 0xaaaa },
259 { 0x0113, 0x2000 },
260 { 0x0117, 0x0f00 },
261 { 0x0125, 0x0420 },
262 { 0x0132, 0x0000 },
263 { 0x0133, 0x0000 },
264 { 0x0136, 0x5555 },
265 { 0x0137, 0x5540 },
266 { 0x0138, 0x3700 },
267 { 0x0139, 0x79a1 },
268 { 0x013a, 0x2020 },
269 { 0x013b, 0x2020 },
270 { 0x013c, 0x2005 },
271 { 0x013f, 0x0000 },
272 { 0x0145, 0x0002 },
273 { 0x0146, 0x0000 },
274 { 0x0147, 0x0000 },
275 { 0x0148, 0x0000 },
276 { 0x0160, 0x4ec0 },
277 { 0x0161, 0x0080 },
278 { 0x0162, 0x0200 },
279 { 0x0163, 0x0800 },
280 { 0x0164, 0x0000 },
281 { 0x0165, 0x0000 },
282 { 0x0166, 0x0000 },
283 { 0x0167, 0x000f },
284 { 0x0168, 0x000f },
285 { 0x0170, 0x4e80 },
286 { 0x0171, 0x0080 },
287 { 0x0172, 0x0200 },
288 { 0x0173, 0x0800 },
289 { 0x0174, 0x00ff },
290 { 0x0175, 0x0000 },
291 { 0x0190, 0x4131 },
292 { 0x0191, 0x4131 },
293 { 0x0192, 0x4131 },
294 { 0x0193, 0x4131 },
295 { 0x0194, 0x0000 },
296 { 0x0195, 0x0000 },
297 { 0x0196, 0x0000 },
298 { 0x0197, 0x0000 },
299 { 0x0198, 0x0000 },
300 { 0x0199, 0x0000 },
301 { 0x01a0, 0x1e64 },
302 { 0x01a1, 0x06a3 },
303 { 0x01a2, 0x0000 },
304 { 0x01a3, 0x0000 },
305 { 0x01a4, 0x0000 },
306 { 0x01a5, 0x0000 },
307 { 0x01a6, 0x0000 },
308 { 0x01a7, 0x0000 },
309 { 0x01a8, 0x0000 },
310 { 0x01a9, 0x0000 },
311 { 0x01aa, 0x0000 },
312 { 0x01ab, 0x0000 },
313 { 0x01b5, 0x0000 },
314 { 0x01b6, 0x01c3 },
315 { 0x01b7, 0x02a0 },
316 { 0x01b8, 0x03e9 },
317 { 0x01b9, 0x1389 },
318 { 0x01ba, 0xc351 },
319 { 0x01bb, 0x0009 },
320 { 0x01bc, 0x0018 },
321 { 0x01bd, 0x002a },
322 { 0x01be, 0x004c },
323 { 0x01bf, 0x0097 },
324 { 0x01c0, 0x433d },
325 { 0x01c1, 0x0000 },
326 { 0x01c2, 0x0000 },
327 { 0x01c3, 0x0000 },
328 { 0x01c4, 0x0000 },
329 { 0x01c5, 0x0000 },
330 { 0x01c6, 0x0000 },
331 { 0x01c7, 0x0000 },
332 { 0x01c8, 0x40af },
333 { 0x01c9, 0x0702 },
334 { 0x01ca, 0x0000 },
335 { 0x01cb, 0x0000 },
336 { 0x01cc, 0x5757 },
337 { 0x01cd, 0x5757 },
338 { 0x01ce, 0x5757 },
339 { 0x01cf, 0x5757 },
340 { 0x01d0, 0x5757 },
341 { 0x01d1, 0x5757 },
342 { 0x01d2, 0x5757 },
343 { 0x01d3, 0x5757 },
344 { 0x01d4, 0x5757 },
345 { 0x01d5, 0x5757 },
346 { 0x01d6, 0x003c },
347 { 0x01da, 0x0000 },
348 { 0x01db, 0x0000 },
349 { 0x01dc, 0x0000 },
350 { 0x01de, 0x7c00 },
351 { 0x01df, 0x0320 },
352 { 0x01e0, 0x06a1 },
353 { 0x01e1, 0x0000 },
354 { 0x01e2, 0x0000 },
355 { 0x01e3, 0x0000 },
356 { 0x01e4, 0x0000 },
357 { 0x01e5, 0x0000 },
358 { 0x01e6, 0x0001 },
359 { 0x01e7, 0x0000 },
360 { 0x01e8, 0x0000 },
361 { 0x01ea, 0x0000 },
362 { 0x01eb, 0x0000 },
363 { 0x01ec, 0x0000 },
364 { 0x01ed, 0x0000 },
365 { 0x01ee, 0x0000 },
366 { 0x01ef, 0x0000 },
367 { 0x01f0, 0x0000 },
368 { 0x01f1, 0x0000 },
369 { 0x01f2, 0x0000 },
370 { 0x01f3, 0x0000 },
371 { 0x01f4, 0x0000 },
372 { 0x0200, 0x0000 },
373 { 0x0201, 0x0000 },
374 { 0x0202, 0x0000 },
375 { 0x0203, 0x0000 },
376 { 0x0204, 0x0000 },
377 { 0x0205, 0x0000 },
378 { 0x0206, 0x0000 },
379 { 0x0207, 0x0000 },
380 { 0x0208, 0x0000 },
381 { 0x0210, 0x60b1 },
382 { 0x0211, 0xa000 },
383 { 0x0212, 0x024c },
384 { 0x0213, 0xf7ff },
385 { 0x0214, 0x024c },
386 { 0x0215, 0x0102 },
387 { 0x0216, 0x00a3 },
388 { 0x0217, 0x0048 },
389 { 0x0218, 0x92c0 },
390 { 0x0219, 0x0000 },
391 { 0x021a, 0x00c8 },
392 { 0x021b, 0x0020 },
393 { 0x02fa, 0x0000 },
394 { 0x02fb, 0x0000 },
395 { 0x02fc, 0x0000 },
396 { 0x02ff, 0x0110 },
397 { 0x0300, 0x001f },
398 { 0x0301, 0x032c },
399 { 0x0302, 0x5f21 },
400 { 0x0303, 0x4000 },
401 { 0x0304, 0x4000 },
402 { 0x0305, 0x06d5 },
403 { 0x0306, 0x8000 },
404 { 0x0307, 0x0700 },
405 { 0x0310, 0x4560 },
406 { 0x0311, 0xa4a8 },
407 { 0x0312, 0x7418 },
408 { 0x0313, 0x0000 },
409 { 0x0314, 0x0006 },
410 { 0x0315, 0xffff },
411 { 0x0316, 0xc400 },
412 { 0x0317, 0x0000 },
413 { 0x0330, 0x00a6 },
414 { 0x0331, 0x04c3 },
415 { 0x0332, 0x27c8 },
416 { 0x0333, 0xbf50 },
417 { 0x0334, 0x0045 },
418 { 0x0335, 0x0007 },
419 { 0x0336, 0x7418 },
420 { 0x0337, 0x0501 },
421 { 0x0338, 0x0000 },
422 { 0x0339, 0x0010 },
423 { 0x033a, 0x1010 },
424 { 0x03c0, 0x7e00 },
425 { 0x03c1, 0x8000 },
426 { 0x03c2, 0x8000 },
427 { 0x03c3, 0x8000 },
428 { 0x03c4, 0x8000 },
429 { 0x03c5, 0x8000 },
430 { 0x03c6, 0x8000 },
431 { 0x03c7, 0x8000 },
432 { 0x03c8, 0x8000 },
433 { 0x03c9, 0x8000 },
434 { 0x03ca, 0x8000 },
435 { 0x03cb, 0x8000 },
436 { 0x03cc, 0x8000 },
437 { 0x03d0, 0x0000 },
438 { 0x03d1, 0x0000 },
439 { 0x03d2, 0x0000 },
440 { 0x03d3, 0x0000 },
441 { 0x03d4, 0x2000 },
442 { 0x03d5, 0x2000 },
443 { 0x03d6, 0x0000 },
444 { 0x03d7, 0x0000 },
445 { 0x03d8, 0x2000 },
446 { 0x03d9, 0x2000 },
447 { 0x03da, 0x2000 },
448 { 0x03db, 0x2000 },
449 { 0x03dc, 0x0000 },
450 { 0x03dd, 0x0000 },
451 { 0x03de, 0x0000 },
452 { 0x03df, 0x2000 },
453 { 0x03e0, 0x0000 },
454 { 0x03e1, 0x0000 },
455 { 0x03e2, 0x0000 },
456 { 0x03e3, 0x0000 },
457 { 0x03e4, 0x0000 },
458 { 0x03e5, 0x0000 },
459 { 0x03e6, 0x0000 },
460 { 0x03e7, 0x0000 },
461 { 0x03e8, 0x0000 },
462 { 0x03e9, 0x0000 },
463 { 0x03ea, 0x0000 },
464 { 0x03eb, 0x0000 },
465 { 0x03ec, 0x0000 },
466 { 0x03ed, 0x0000 },
467 { 0x03ee, 0x0000 },
468 { 0x03ef, 0x0000 },
469 { 0x03f0, 0x0800 },
470 { 0x03f1, 0x0800 },
471 { 0x03f2, 0x0800 },
472 { 0x03f3, 0x0800 },
473 { 0x03fe, 0x0000 },
474 { 0x03ff, 0x0000 },
475 { 0x07f0, 0x0000 },
476 { 0x07fa, 0x0000 },
477};
478
479static const struct reg_default rt5663_reg[] = {
480 { 0x0000, 0x0000 },
481 { 0x0002, 0x0008 },
482 { 0x0005, 0x1000 },
483 { 0x0006, 0x1000 },
484 { 0x000a, 0x0000 },
485 { 0x0010, 0x000f },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]486 { 0x0015, 0x42f1 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]487 { 0x0016, 0x0000 },
488 { 0x0018, 0x000b },
489 { 0x0019, 0xafaf },
490 { 0x001c, 0x2f2f },
491 { 0x001f, 0x0000 },
492 { 0x0022, 0x5757 },
493 { 0x0023, 0x0039 },
494 { 0x0026, 0xc0c0 },
495 { 0x0029, 0x8080 },
oder_chiou@realtek.com1d5c5b62017-07-19 10:20:23 +0800[diff] [blame]496 { 0x002a, 0x8020 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]497 { 0x002c, 0x000c },
498 { 0x002d, 0x0000 },
499 { 0x0040, 0x0808 },
500 { 0x0061, 0x0000 },
501 { 0x0062, 0x0000 },
502 { 0x0063, 0x003e },
503 { 0x0064, 0x0000 },
504 { 0x0065, 0x0000 },
505 { 0x0066, 0x0000 },
506 { 0x006b, 0x0000 },
507 { 0x006e, 0x0000 },
508 { 0x006f, 0x0000 },
509 { 0x0070, 0x8020 },
510 { 0x0073, 0x1000 },
511 { 0x0074, 0xe400 },
512 { 0x0075, 0x0002 },
513 { 0x0076, 0x0001 },
514 { 0x0077, 0x00f0 },
515 { 0x0078, 0x0000 },
516 { 0x0079, 0x0000 },
517 { 0x007a, 0x0123 },
518 { 0x007b, 0x8003 },
519 { 0x0080, 0x0000 },
520 { 0x0081, 0x0000 },
521 { 0x0082, 0x0000 },
522 { 0x0083, 0x0000 },
523 { 0x0084, 0x0000 },
oder_chiou@realtek.comd26ed932017-07-18 10:12:58 +0800[diff] [blame]524 { 0x0086, 0x0028 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]525 { 0x0087, 0x0000 },
526 { 0x008a, 0x0000 },
527 { 0x008b, 0x0000 },
528 { 0x008c, 0x0003 },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]529 { 0x008e, 0x0008 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]530 { 0x008f, 0x1000 },
531 { 0x0090, 0x0646 },
532 { 0x0091, 0x0e3e },
533 { 0x0092, 0x1071 },
534 { 0x0093, 0x0000 },
535 { 0x0094, 0x0080 },
536 { 0x0097, 0x0000 },
537 { 0x0098, 0x0000 },
538 { 0x009a, 0x0000 },
539 { 0x009f, 0x0000 },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]540 { 0x00ae, 0x6000 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]541 { 0x00af, 0x0000 },
542 { 0x00b6, 0x0000 },
543 { 0x00b7, 0x0000 },
544 { 0x00b8, 0x0000 },
545 { 0x00ba, 0x0000 },
546 { 0x00bb, 0x0000 },
547 { 0x00be, 0x0000 },
548 { 0x00bf, 0x0000 },
549 { 0x00c0, 0x0000 },
550 { 0x00c1, 0x0000 },
551 { 0x00c5, 0x0000 },
552 { 0x00cb, 0xa02f },
553 { 0x00cc, 0x0000 },
554 { 0x00cd, 0x0e02 },
555 { 0x00d9, 0x08f9 },
556 { 0x00db, 0x0008 },
557 { 0x00dc, 0x00c0 },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]558 { 0x00dd, 0x6729 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]559 { 0x00de, 0x3131 },
560 { 0x00df, 0x0008 },
561 { 0x00e0, 0x4000 },
562 { 0x00e1, 0x3131 },
563 { 0x00e2, 0x0043 },
564 { 0x00e4, 0x400b },
565 { 0x00e5, 0x8031 },
566 { 0x00e6, 0x3080 },
567 { 0x00e7, 0x4100 },
568 { 0x00e8, 0x1400 },
569 { 0x00e9, 0xe00a },
570 { 0x00ea, 0x0404 },
571 { 0x00eb, 0x0404 },
572 { 0x00ec, 0xb320 },
573 { 0x00ed, 0x0000 },
574 { 0x00f4, 0x0000 },
575 { 0x00f6, 0x0000 },
576 { 0x00f8, 0x0000 },
577 { 0x00fa, 0x8000 },
578 { 0x00fd, 0x0001 },
579 { 0x00fe, 0x10ec },
580 { 0x00ff, 0x6406 },
581 { 0x0100, 0xa0a0 },
582 { 0x0108, 0x4444 },
583 { 0x0109, 0x4444 },
584 { 0x010a, 0xaaaa },
585 { 0x010b, 0x00a0 },
586 { 0x010c, 0x8aaa },
587 { 0x010d, 0xaaaa },
588 { 0x010e, 0x2aaa },
589 { 0x010f, 0x002a },
590 { 0x0110, 0xa0a4 },
591 { 0x0111, 0x4602 },
592 { 0x0112, 0x0101 },
593 { 0x0113, 0x2000 },
594 { 0x0114, 0x0000 },
595 { 0x0116, 0x0000 },
596 { 0x0117, 0x0f00 },
597 { 0x0118, 0x0006 },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]598 { 0x0125, 0x2424 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]599 { 0x0126, 0x5550 },
600 { 0x0127, 0x0400 },
601 { 0x0128, 0x7711 },
602 { 0x0132, 0x0004 },
603 { 0x0137, 0x5441 },
604 { 0x0139, 0x79a1 },
605 { 0x013a, 0x30c0 },
606 { 0x013b, 0x2000 },
607 { 0x013c, 0x2005 },
608 { 0x013d, 0x30c0 },
609 { 0x013e, 0x0000 },
610 { 0x0140, 0x3700 },
611 { 0x0141, 0x1f00 },
612 { 0x0144, 0x0000 },
613 { 0x0145, 0x0002 },
614 { 0x0146, 0x0000 },
615 { 0x0160, 0x0e80 },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]616 { 0x0161, 0x0080 },
617 { 0x0162, 0x0200 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]618 { 0x0163, 0x0800 },
619 { 0x0164, 0x0000 },
620 { 0x0165, 0x0000 },
621 { 0x0166, 0x0000 },
622 { 0x0167, 0x1417 },
623 { 0x0168, 0x0017 },
624 { 0x0169, 0x0017 },
625 { 0x0180, 0x2000 },
626 { 0x0181, 0x0000 },
627 { 0x0182, 0x0000 },
628 { 0x0183, 0x2000 },
629 { 0x0184, 0x0000 },
630 { 0x0185, 0x0000 },
631 { 0x01b0, 0x4b30 },
632 { 0x01b1, 0x0000 },
633 { 0x01b2, 0xd870 },
634 { 0x01b3, 0x0000 },
635 { 0x01b4, 0x0030 },
636 { 0x01b5, 0x5757 },
637 { 0x01b6, 0x5757 },
638 { 0x01b7, 0x5757 },
639 { 0x01b8, 0x5757 },
640 { 0x01c0, 0x433d },
641 { 0x01c1, 0x0540 },
642 { 0x01c2, 0x0000 },
643 { 0x01c3, 0x0000 },
644 { 0x01c4, 0x0000 },
645 { 0x01c5, 0x0009 },
646 { 0x01c6, 0x0018 },
647 { 0x01c7, 0x002a },
648 { 0x01c8, 0x004c },
649 { 0x01c9, 0x0097 },
650 { 0x01ca, 0x01c3 },
651 { 0x01cb, 0x03e9 },
652 { 0x01cc, 0x1389 },
653 { 0x01cd, 0xc351 },
654 { 0x01ce, 0x0000 },
655 { 0x01cf, 0x0000 },
656 { 0x01d0, 0x0000 },
657 { 0x01d1, 0x0000 },
658 { 0x01d2, 0x0000 },
659 { 0x01d3, 0x003c },
660 { 0x01d4, 0x5757 },
661 { 0x01d5, 0x5757 },
662 { 0x01d6, 0x5757 },
663 { 0x01d7, 0x5757 },
664 { 0x01d8, 0x5757 },
665 { 0x01d9, 0x5757 },
666 { 0x01da, 0x0000 },
667 { 0x01db, 0x0000 },
668 { 0x01dd, 0x0009 },
669 { 0x01de, 0x7f00 },
670 { 0x01df, 0x00c8 },
671 { 0x01e0, 0x0691 },
672 { 0x01e1, 0x0000 },
673 { 0x01e2, 0x0000 },
674 { 0x01e3, 0x0000 },
675 { 0x01e4, 0x0000 },
676 { 0x01e5, 0x0040 },
677 { 0x01e6, 0x0000 },
678 { 0x01e7, 0x0000 },
679 { 0x01e8, 0x0000 },
680 { 0x01ea, 0x0000 },
681 { 0x01eb, 0x0000 },
682 { 0x01ec, 0x0000 },
683 { 0x01ed, 0x0000 },
684 { 0x01ee, 0x0000 },
685 { 0x01ef, 0x0000 },
686 { 0x01f0, 0x0000 },
687 { 0x01f1, 0x0000 },
688 { 0x01f2, 0x0000 },
689 { 0x0200, 0x0000 },
690 { 0x0201, 0x2244 },
691 { 0x0202, 0xaaaa },
692 { 0x0250, 0x8010 },
693 { 0x0251, 0x0000 },
694 { 0x0252, 0x028a },
695 { 0x02fa, 0x0000 },
oder_chiou@realtek.com9f8f5b52017-07-10 11:14:57 +0800[diff] [blame]696 { 0x02fb, 0x00a4 },
697 { 0x02fc, 0x0300 },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]698 { 0x0300, 0x0000 },
699 { 0x03d0, 0x0000 },
700 { 0x03d1, 0x0000 },
701 { 0x03d2, 0x0000 },
702 { 0x03d3, 0x0000 },
703 { 0x03d4, 0x2000 },
704 { 0x03d5, 0x2000 },
705 { 0x03d6, 0x0000 },
706 { 0x03d7, 0x0000 },
707 { 0x03d8, 0x2000 },
708 { 0x03d9, 0x2000 },
709 { 0x03da, 0x2000 },
710 { 0x03db, 0x2000 },
711 { 0x03dc, 0x0000 },
712 { 0x03dd, 0x0000 },
713 { 0x03de, 0x0000 },
714 { 0x03df, 0x2000 },
715 { 0x03e0, 0x0000 },
716 { 0x03e1, 0x0000 },
717 { 0x03e2, 0x0000 },
718 { 0x03e3, 0x0000 },
719 { 0x03e4, 0x0000 },
720 { 0x03e5, 0x0000 },
721 { 0x03e6, 0x0000 },
722 { 0x03e7, 0x0000 },
723 { 0x03e8, 0x0000 },
724 { 0x03e9, 0x0000 },
725 { 0x03ea, 0x0000 },
726 { 0x03eb, 0x0000 },
727 { 0x03ec, 0x0000 },
728 { 0x03ed, 0x0000 },
729 { 0x03ee, 0x0000 },
730 { 0x03ef, 0x0000 },
731 { 0x03f0, 0x0800 },
732 { 0x03f1, 0x0800 },
733 { 0x03f2, 0x0800 },
734 { 0x03f3, 0x0800 },
735};
736
737static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
738{
739 switch (reg) {
740 case RT5663_RESET:
741 case RT5663_SIL_DET_CTL:
742 case RT5663_HP_IMP_GAIN_2:
743 case RT5663_AD_DA_MIXER:
744 case RT5663_FRAC_DIV_2:
745 case RT5663_MICBIAS_1:
746 case RT5663_ASRC_11_2:
747 case RT5663_ADC_EQ_1:
748 case RT5663_INT_ST_1:
749 case RT5663_INT_ST_2:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]750 case RT5663_GPIO_STA1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]751 case RT5663_SIN_GEN_1:
752 case RT5663_IL_CMD_1:
753 case RT5663_IL_CMD_5:
754 case RT5663_IL_CMD_PWRSAV1:
755 case RT5663_EM_JACK_TYPE_1:
756 case RT5663_EM_JACK_TYPE_2:
757 case RT5663_EM_JACK_TYPE_3:
758 case RT5663_JD_CTRL2:
759 case RT5663_VENDOR_ID:
760 case RT5663_VENDOR_ID_1:
761 case RT5663_VENDOR_ID_2:
762 case RT5663_PLL_INT_REG:
763 case RT5663_SOFT_RAMP:
764 case RT5663_STO_DRE_1:
765 case RT5663_STO_DRE_5:
766 case RT5663_STO_DRE_6:
767 case RT5663_STO_DRE_7:
768 case RT5663_MIC_DECRO_1:
769 case RT5663_MIC_DECRO_4:
770 case RT5663_HP_IMP_SEN_1:
771 case RT5663_HP_IMP_SEN_3:
772 case RT5663_HP_IMP_SEN_4:
773 case RT5663_HP_IMP_SEN_5:
774 case RT5663_HP_CALIB_1_1:
775 case RT5663_HP_CALIB_9:
776 case RT5663_HP_CALIB_ST1:
777 case RT5663_HP_CALIB_ST2:
778 case RT5663_HP_CALIB_ST3:
779 case RT5663_HP_CALIB_ST4:
780 case RT5663_HP_CALIB_ST5:
781 case RT5663_HP_CALIB_ST6:
782 case RT5663_HP_CALIB_ST7:
783 case RT5663_HP_CALIB_ST8:
784 case RT5663_HP_CALIB_ST9:
785 case RT5663_ANA_JD:
786 return true;
787 default:
788 return false;
789 }
790}
791
792static bool rt5663_readable_register(struct device *dev, unsigned int reg)
793{
794 switch (reg) {
795 case RT5663_RESET:
796 case RT5663_HP_OUT_EN:
797 case RT5663_HP_LCH_DRE:
798 case RT5663_HP_RCH_DRE:
799 case RT5663_CALIB_BST:
800 case RT5663_RECMIX:
801 case RT5663_SIL_DET_CTL:
802 case RT5663_PWR_SAV_SILDET:
803 case RT5663_SIDETONE_CTL:
804 case RT5663_STO1_DAC_DIG_VOL:
805 case RT5663_STO1_ADC_DIG_VOL:
806 case RT5663_STO1_BOOST:
807 case RT5663_HP_IMP_GAIN_1:
808 case RT5663_HP_IMP_GAIN_2:
809 case RT5663_STO1_ADC_MIXER:
810 case RT5663_AD_DA_MIXER:
811 case RT5663_STO_DAC_MIXER:
812 case RT5663_DIG_SIDE_MIXER:
813 case RT5663_BYPASS_STO_DAC:
814 case RT5663_CALIB_REC_MIX:
815 case RT5663_PWR_DIG_1:
816 case RT5663_PWR_DIG_2:
817 case RT5663_PWR_ANLG_1:
818 case RT5663_PWR_ANLG_2:
819 case RT5663_PWR_ANLG_3:
820 case RT5663_PWR_MIXER:
821 case RT5663_SIG_CLK_DET:
822 case RT5663_PRE_DIV_GATING_1:
823 case RT5663_PRE_DIV_GATING_2:
824 case RT5663_I2S1_SDP:
825 case RT5663_ADDA_CLK_1:
826 case RT5663_ADDA_RST:
827 case RT5663_FRAC_DIV_1:
828 case RT5663_FRAC_DIV_2:
829 case RT5663_TDM_1:
830 case RT5663_TDM_2:
831 case RT5663_TDM_3:
832 case RT5663_TDM_4:
833 case RT5663_TDM_5:
834 case RT5663_GLB_CLK:
835 case RT5663_PLL_1:
836 case RT5663_PLL_2:
837 case RT5663_ASRC_1:
838 case RT5663_ASRC_2:
839 case RT5663_ASRC_4:
840 case RT5663_DUMMY_REG:
841 case RT5663_ASRC_8:
842 case RT5663_ASRC_9:
843 case RT5663_ASRC_11:
844 case RT5663_DEPOP_1:
845 case RT5663_DEPOP_2:
846 case RT5663_DEPOP_3:
847 case RT5663_HP_CHARGE_PUMP_1:
848 case RT5663_HP_CHARGE_PUMP_2:
849 case RT5663_MICBIAS_1:
850 case RT5663_RC_CLK:
851 case RT5663_ASRC_11_2:
852 case RT5663_DUMMY_REG_2:
853 case RT5663_REC_PATH_GAIN:
854 case RT5663_AUTO_1MRC_CLK:
855 case RT5663_ADC_EQ_1:
856 case RT5663_ADC_EQ_2:
857 case RT5663_IRQ_1:
858 case RT5663_IRQ_2:
859 case RT5663_IRQ_3:
860 case RT5663_IRQ_4:
861 case RT5663_IRQ_5:
862 case RT5663_INT_ST_1:
863 case RT5663_INT_ST_2:
864 case RT5663_GPIO_1:
865 case RT5663_GPIO_2:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]866 case RT5663_GPIO_STA1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]867 case RT5663_SIN_GEN_1:
868 case RT5663_SIN_GEN_2:
869 case RT5663_SIN_GEN_3:
870 case RT5663_SOF_VOL_ZC1:
871 case RT5663_IL_CMD_1:
872 case RT5663_IL_CMD_2:
873 case RT5663_IL_CMD_3:
874 case RT5663_IL_CMD_4:
875 case RT5663_IL_CMD_5:
876 case RT5663_IL_CMD_6:
877 case RT5663_IL_CMD_7:
878 case RT5663_IL_CMD_8:
879 case RT5663_IL_CMD_PWRSAV1:
880 case RT5663_IL_CMD_PWRSAV2:
881 case RT5663_EM_JACK_TYPE_1:
882 case RT5663_EM_JACK_TYPE_2:
883 case RT5663_EM_JACK_TYPE_3:
884 case RT5663_EM_JACK_TYPE_4:
885 case RT5663_EM_JACK_TYPE_5:
886 case RT5663_EM_JACK_TYPE_6:
887 case RT5663_STO1_HPF_ADJ1:
888 case RT5663_STO1_HPF_ADJ2:
889 case RT5663_FAST_OFF_MICBIAS:
890 case RT5663_JD_CTRL1:
891 case RT5663_JD_CTRL2:
892 case RT5663_DIG_MISC:
893 case RT5663_VENDOR_ID:
894 case RT5663_VENDOR_ID_1:
895 case RT5663_VENDOR_ID_2:
896 case RT5663_DIG_VOL_ZCD:
897 case RT5663_ANA_BIAS_CUR_1:
898 case RT5663_ANA_BIAS_CUR_2:
899 case RT5663_ANA_BIAS_CUR_3:
900 case RT5663_ANA_BIAS_CUR_4:
901 case RT5663_ANA_BIAS_CUR_5:
902 case RT5663_ANA_BIAS_CUR_6:
903 case RT5663_BIAS_CUR_5:
904 case RT5663_BIAS_CUR_6:
905 case RT5663_BIAS_CUR_7:
906 case RT5663_BIAS_CUR_8:
907 case RT5663_DACREF_LDO:
908 case RT5663_DUMMY_REG_3:
909 case RT5663_BIAS_CUR_9:
910 case RT5663_DUMMY_REG_4:
911 case RT5663_VREFADJ_OP:
912 case RT5663_VREF_RECMIX:
913 case RT5663_CHARGE_PUMP_1:
914 case RT5663_CHARGE_PUMP_1_2:
915 case RT5663_CHARGE_PUMP_1_3:
916 case RT5663_CHARGE_PUMP_2:
917 case RT5663_DIG_IN_PIN1:
918 case RT5663_PAD_DRV_CTL:
919 case RT5663_PLL_INT_REG:
920 case RT5663_CHOP_DAC_L:
921 case RT5663_CHOP_ADC:
922 case RT5663_CALIB_ADC:
923 case RT5663_CHOP_DAC_R:
924 case RT5663_DUMMY_CTL_DACLR:
925 case RT5663_DUMMY_REG_5:
926 case RT5663_SOFT_RAMP:
927 case RT5663_TEST_MODE_1:
928 case RT5663_TEST_MODE_2:
929 case RT5663_TEST_MODE_3:
930 case RT5663_STO_DRE_1:
931 case RT5663_STO_DRE_2:
932 case RT5663_STO_DRE_3:
933 case RT5663_STO_DRE_4:
934 case RT5663_STO_DRE_5:
935 case RT5663_STO_DRE_6:
936 case RT5663_STO_DRE_7:
937 case RT5663_STO_DRE_8:
938 case RT5663_STO_DRE_9:
939 case RT5663_STO_DRE_10:
940 case RT5663_MIC_DECRO_1:
941 case RT5663_MIC_DECRO_2:
942 case RT5663_MIC_DECRO_3:
943 case RT5663_MIC_DECRO_4:
944 case RT5663_MIC_DECRO_5:
945 case RT5663_MIC_DECRO_6:
946 case RT5663_HP_DECRO_1:
947 case RT5663_HP_DECRO_2:
948 case RT5663_HP_DECRO_3:
949 case RT5663_HP_DECRO_4:
950 case RT5663_HP_DECOUP:
951 case RT5663_HP_IMP_SEN_MAP8:
952 case RT5663_HP_IMP_SEN_MAP9:
953 case RT5663_HP_IMP_SEN_MAP10:
954 case RT5663_HP_IMP_SEN_MAP11:
955 case RT5663_HP_IMP_SEN_1:
956 case RT5663_HP_IMP_SEN_2:
957 case RT5663_HP_IMP_SEN_3:
958 case RT5663_HP_IMP_SEN_4:
959 case RT5663_HP_IMP_SEN_5:
960 case RT5663_HP_IMP_SEN_6:
961 case RT5663_HP_IMP_SEN_7:
962 case RT5663_HP_IMP_SEN_8:
963 case RT5663_HP_IMP_SEN_9:
964 case RT5663_HP_IMP_SEN_10:
965 case RT5663_HP_IMP_SEN_11:
966 case RT5663_HP_IMP_SEN_12:
967 case RT5663_HP_IMP_SEN_13:
968 case RT5663_HP_IMP_SEN_14:
969 case RT5663_HP_IMP_SEN_15:
970 case RT5663_HP_IMP_SEN_16:
971 case RT5663_HP_IMP_SEN_17:
972 case RT5663_HP_IMP_SEN_18:
973 case RT5663_HP_IMP_SEN_19:
974 case RT5663_HP_IMPSEN_DIG5:
975 case RT5663_HP_IMPSEN_MAP1:
976 case RT5663_HP_IMPSEN_MAP2:
977 case RT5663_HP_IMPSEN_MAP3:
978 case RT5663_HP_IMPSEN_MAP4:
979 case RT5663_HP_IMPSEN_MAP5:
980 case RT5663_HP_IMPSEN_MAP7:
981 case RT5663_HP_LOGIC_1:
982 case RT5663_HP_LOGIC_2:
983 case RT5663_HP_CALIB_1:
984 case RT5663_HP_CALIB_1_1:
985 case RT5663_HP_CALIB_2:
986 case RT5663_HP_CALIB_3:
987 case RT5663_HP_CALIB_4:
988 case RT5663_HP_CALIB_5:
989 case RT5663_HP_CALIB_5_1:
990 case RT5663_HP_CALIB_6:
991 case RT5663_HP_CALIB_7:
992 case RT5663_HP_CALIB_9:
993 case RT5663_HP_CALIB_10:
994 case RT5663_HP_CALIB_11:
995 case RT5663_HP_CALIB_ST1:
996 case RT5663_HP_CALIB_ST2:
997 case RT5663_HP_CALIB_ST3:
998 case RT5663_HP_CALIB_ST4:
999 case RT5663_HP_CALIB_ST5:
1000 case RT5663_HP_CALIB_ST6:
1001 case RT5663_HP_CALIB_ST7:
1002 case RT5663_HP_CALIB_ST8:
1003 case RT5663_HP_CALIB_ST9:
1004 case RT5663_HP_AMP_DET:
1005 case RT5663_DUMMY_REG_6:
1006 case RT5663_HP_BIAS:
1007 case RT5663_CBJ_1:
1008 case RT5663_CBJ_2:
1009 case RT5663_CBJ_3:
1010 case RT5663_DUMMY_1:
1011 case RT5663_DUMMY_2:
1012 case RT5663_DUMMY_3:
1013 case RT5663_ANA_JD:
1014 case RT5663_ADC_LCH_LPF1_A1:
1015 case RT5663_ADC_RCH_LPF1_A1:
1016 case RT5663_ADC_LCH_LPF1_H0:
1017 case RT5663_ADC_RCH_LPF1_H0:
1018 case RT5663_ADC_LCH_BPF1_A1:
1019 case RT5663_ADC_RCH_BPF1_A1:
1020 case RT5663_ADC_LCH_BPF1_A2:
1021 case RT5663_ADC_RCH_BPF1_A2:
1022 case RT5663_ADC_LCH_BPF1_H0:
1023 case RT5663_ADC_RCH_BPF1_H0:
1024 case RT5663_ADC_LCH_BPF2_A1:
1025 case RT5663_ADC_RCH_BPF2_A1:
1026 case RT5663_ADC_LCH_BPF2_A2:
1027 case RT5663_ADC_RCH_BPF2_A2:
1028 case RT5663_ADC_LCH_BPF2_H0:
1029 case RT5663_ADC_RCH_BPF2_H0:
1030 case RT5663_ADC_LCH_BPF3_A1:
1031 case RT5663_ADC_RCH_BPF3_A1:
1032 case RT5663_ADC_LCH_BPF3_A2:
1033 case RT5663_ADC_RCH_BPF3_A2:
1034 case RT5663_ADC_LCH_BPF3_H0:
1035 case RT5663_ADC_RCH_BPF3_H0:
1036 case RT5663_ADC_LCH_BPF4_A1:
1037 case RT5663_ADC_RCH_BPF4_A1:
1038 case RT5663_ADC_LCH_BPF4_A2:
1039 case RT5663_ADC_RCH_BPF4_A2:
1040 case RT5663_ADC_LCH_BPF4_H0:
1041 case RT5663_ADC_RCH_BPF4_H0:
1042 case RT5663_ADC_LCH_HPF1_A1:
1043 case RT5663_ADC_RCH_HPF1_A1:
1044 case RT5663_ADC_LCH_HPF1_H0:
1045 case RT5663_ADC_RCH_HPF1_H0:
1046 case RT5663_ADC_EQ_PRE_VOL_L:
1047 case RT5663_ADC_EQ_PRE_VOL_R:
1048 case RT5663_ADC_EQ_POST_VOL_L:
1049 case RT5663_ADC_EQ_POST_VOL_R:
1050 return true;
1051 default:
1052 return false;
1053 }
1054}
1055
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1056static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1057{
1058 switch (reg) {
1059 case RT5663_RESET:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1060 case RT5663_CBJ_TYPE_2:
1061 case RT5663_PDM_OUT_CTL:
1062 case RT5663_PDM_I2C_DATA_CTL1:
1063 case RT5663_PDM_I2C_DATA_CTL4:
1064 case RT5663_ALC_BK_GAIN:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1065 case RT5663_PLL_2:
1066 case RT5663_MICBIAS_1:
1067 case RT5663_ADC_EQ_1:
1068 case RT5663_INT_ST_1:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1069 case RT5663_GPIO_STA2:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1070 case RT5663_IL_CMD_1:
1071 case RT5663_IL_CMD_5:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1072 case RT5663_A_JD_CTRL:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1073 case RT5663_JD_CTRL2:
1074 case RT5663_VENDOR_ID:
1075 case RT5663_VENDOR_ID_1:
1076 case RT5663_VENDOR_ID_2:
1077 case RT5663_STO_DRE_1:
1078 case RT5663_STO_DRE_5:
1079 case RT5663_STO_DRE_6:
1080 case RT5663_STO_DRE_7:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1081 case RT5663_MONO_DYNA_6:
1082 case RT5663_STO1_SIL_DET:
1083 case RT5663_MONOL_SIL_DET:
1084 case RT5663_MONOR_SIL_DET:
1085 case RT5663_STO2_DAC_SIL:
1086 case RT5663_MONO_AMP_CAL_ST1:
1087 case RT5663_MONO_AMP_CAL_ST2:
1088 case RT5663_MONO_AMP_CAL_ST3:
1089 case RT5663_MONO_AMP_CAL_ST4:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1090 case RT5663_HP_IMP_SEN_2:
1091 case RT5663_HP_IMP_SEN_3:
1092 case RT5663_HP_IMP_SEN_4:
1093 case RT5663_HP_IMP_SEN_10:
1094 case RT5663_HP_CALIB_1:
1095 case RT5663_HP_CALIB_10:
1096 case RT5663_HP_CALIB_ST1:
1097 case RT5663_HP_CALIB_ST4:
1098 case RT5663_HP_CALIB_ST5:
1099 case RT5663_HP_CALIB_ST6:
1100 case RT5663_HP_CALIB_ST7:
1101 case RT5663_HP_CALIB_ST8:
1102 case RT5663_HP_CALIB_ST9:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1103 case RT5663_HP_CALIB_ST10:
1104 case RT5663_HP_CALIB_ST11:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1105 return true;
1106 default:
1107 return false;
1108 }
1109}
1110
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1111static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1112{
1113 switch (reg) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1114 case RT5663_LOUT_CTRL:
1115 case RT5663_HP_AMP_2:
1116 case RT5663_MONO_OUT:
1117 case RT5663_MONO_GAIN:
1118 case RT5663_AEC_BST:
1119 case RT5663_IN1_IN2:
1120 case RT5663_IN3_IN4:
1121 case RT5663_INL1_INR1:
1122 case RT5663_CBJ_TYPE_2:
1123 case RT5663_CBJ_TYPE_3:
1124 case RT5663_CBJ_TYPE_4:
1125 case RT5663_CBJ_TYPE_5:
1126 case RT5663_CBJ_TYPE_8:
1127 case RT5663_DAC3_DIG_VOL:
1128 case RT5663_DAC3_CTRL:
1129 case RT5663_MONO_ADC_DIG_VOL:
1130 case RT5663_STO2_ADC_DIG_VOL:
1131 case RT5663_MONO_ADC_BST_GAIN:
1132 case RT5663_STO2_ADC_BST_GAIN:
1133 case RT5663_SIDETONE_CTRL:
1134 case RT5663_MONO1_ADC_MIXER:
1135 case RT5663_STO2_ADC_MIXER:
1136 case RT5663_MONO_DAC_MIXER:
1137 case RT5663_DAC2_SRC_CTRL:
1138 case RT5663_IF_3_4_DATA_CTL:
1139 case RT5663_IF_5_DATA_CTL:
1140 case RT5663_PDM_OUT_CTL:
1141 case RT5663_PDM_I2C_DATA_CTL1:
1142 case RT5663_PDM_I2C_DATA_CTL2:
1143 case RT5663_PDM_I2C_DATA_CTL3:
1144 case RT5663_PDM_I2C_DATA_CTL4:
1145 case RT5663_RECMIX1_NEW:
1146 case RT5663_RECMIX1L_0:
1147 case RT5663_RECMIX1L:
1148 case RT5663_RECMIX1R_0:
1149 case RT5663_RECMIX1R:
1150 case RT5663_RECMIX2_NEW:
1151 case RT5663_RECMIX2_L_2:
1152 case RT5663_RECMIX2_R:
1153 case RT5663_RECMIX2_R_2:
1154 case RT5663_CALIB_REC_LR:
1155 case RT5663_ALC_BK_GAIN:
1156 case RT5663_MONOMIX_GAIN:
1157 case RT5663_MONOMIX_IN_GAIN:
1158 case RT5663_OUT_MIXL_GAIN:
1159 case RT5663_OUT_LMIX_IN_GAIN:
1160 case RT5663_OUT_RMIX_IN_GAIN:
1161 case RT5663_OUT_RMIX_IN_GAIN1:
1162 case RT5663_LOUT_MIXER_CTRL:
1163 case RT5663_PWR_VOL:
1164 case RT5663_ADCDAC_RST:
1165 case RT5663_I2S34_SDP:
1166 case RT5663_I2S5_SDP:
1167 case RT5663_TDM_6:
1168 case RT5663_TDM_7:
1169 case RT5663_TDM_8:
1170 case RT5663_TDM_9:
1171 case RT5663_ASRC_3:
1172 case RT5663_ASRC_6:
1173 case RT5663_ASRC_7:
1174 case RT5663_PLL_TRK_13:
1175 case RT5663_I2S_M_CLK_CTL:
1176 case RT5663_FDIV_I2S34_M_CLK:
1177 case RT5663_FDIV_I2S34_M_CLK2:
1178 case RT5663_FDIV_I2S5_M_CLK:
1179 case RT5663_FDIV_I2S5_M_CLK2:
1180 case RT5663_V2_IRQ_4:
1181 case RT5663_GPIO_3:
1182 case RT5663_GPIO_4:
1183 case RT5663_GPIO_STA2:
1184 case RT5663_HP_AMP_DET1:
1185 case RT5663_HP_AMP_DET2:
1186 case RT5663_HP_AMP_DET3:
1187 case RT5663_MID_BD_HP_AMP:
1188 case RT5663_LOW_BD_HP_AMP:
1189 case RT5663_SOF_VOL_ZC2:
1190 case RT5663_ADC_STO2_ADJ1:
1191 case RT5663_ADC_STO2_ADJ2:
1192 case RT5663_A_JD_CTRL:
1193 case RT5663_JD1_TRES_CTRL:
1194 case RT5663_JD2_TRES_CTRL:
1195 case RT5663_V2_JD_CTRL2:
1196 case RT5663_DUM_REG_2:
1197 case RT5663_DUM_REG_3:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1198 case RT5663_VENDOR_ID:
1199 case RT5663_VENDOR_ID_1:
1200 case RT5663_VENDOR_ID_2:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1201 case RT5663_DACADC_DIG_VOL2:
1202 case RT5663_DIG_IN_PIN2:
1203 case RT5663_PAD_DRV_CTL1:
1204 case RT5663_SOF_RAM_DEPOP:
1205 case RT5663_VOL_TEST:
1206 case RT5663_TEST_MODE_4:
1207 case RT5663_TEST_MODE_5:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1208 case RT5663_STO_DRE_9:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1209 case RT5663_MONO_DYNA_1:
1210 case RT5663_MONO_DYNA_2:
1211 case RT5663_MONO_DYNA_3:
1212 case RT5663_MONO_DYNA_4:
1213 case RT5663_MONO_DYNA_5:
1214 case RT5663_MONO_DYNA_6:
1215 case RT5663_STO1_SIL_DET:
1216 case RT5663_MONOL_SIL_DET:
1217 case RT5663_MONOR_SIL_DET:
1218 case RT5663_STO2_DAC_SIL:
1219 case RT5663_PWR_SAV_CTL1:
1220 case RT5663_PWR_SAV_CTL2:
1221 case RT5663_PWR_SAV_CTL3:
1222 case RT5663_PWR_SAV_CTL4:
1223 case RT5663_PWR_SAV_CTL5:
1224 case RT5663_PWR_SAV_CTL6:
1225 case RT5663_MONO_AMP_CAL1:
1226 case RT5663_MONO_AMP_CAL2:
1227 case RT5663_MONO_AMP_CAL3:
1228 case RT5663_MONO_AMP_CAL4:
1229 case RT5663_MONO_AMP_CAL5:
1230 case RT5663_MONO_AMP_CAL6:
1231 case RT5663_MONO_AMP_CAL7:
1232 case RT5663_MONO_AMP_CAL_ST1:
1233 case RT5663_MONO_AMP_CAL_ST2:
1234 case RT5663_MONO_AMP_CAL_ST3:
1235 case RT5663_MONO_AMP_CAL_ST4:
1236 case RT5663_MONO_AMP_CAL_ST5:
1237 case RT5663_V2_HP_IMP_SEN_13:
1238 case RT5663_V2_HP_IMP_SEN_14:
1239 case RT5663_V2_HP_IMP_SEN_6:
1240 case RT5663_V2_HP_IMP_SEN_7:
1241 case RT5663_V2_HP_IMP_SEN_8:
1242 case RT5663_V2_HP_IMP_SEN_9:
1243 case RT5663_V2_HP_IMP_SEN_10:
1244 case RT5663_HP_LOGIC_3:
1245 case RT5663_HP_CALIB_ST10:
1246 case RT5663_HP_CALIB_ST11:
1247 case RT5663_PRO_REG_TBL_4:
1248 case RT5663_PRO_REG_TBL_5:
1249 case RT5663_PRO_REG_TBL_6:
1250 case RT5663_PRO_REG_TBL_7:
1251 case RT5663_PRO_REG_TBL_8:
1252 case RT5663_PRO_REG_TBL_9:
1253 case RT5663_SAR_ADC_INL_1:
1254 case RT5663_SAR_ADC_INL_2:
1255 case RT5663_SAR_ADC_INL_3:
1256 case RT5663_SAR_ADC_INL_4:
1257 case RT5663_SAR_ADC_INL_5:
1258 case RT5663_SAR_ADC_INL_6:
1259 case RT5663_SAR_ADC_INL_7:
1260 case RT5663_SAR_ADC_INL_8:
1261 case RT5663_SAR_ADC_INL_9:
1262 case RT5663_SAR_ADC_INL_10:
1263 case RT5663_SAR_ADC_INL_11:
1264 case RT5663_SAR_ADC_INL_12:
1265 case RT5663_DRC_CTRL_1:
1266 case RT5663_DRC1_CTRL_2:
1267 case RT5663_DRC1_CTRL_3:
1268 case RT5663_DRC1_CTRL_4:
1269 case RT5663_DRC1_CTRL_5:
1270 case RT5663_DRC1_CTRL_6:
1271 case RT5663_DRC1_HD_CTRL_1:
1272 case RT5663_DRC1_HD_CTRL_2:
1273 case RT5663_DRC1_PRI_REG_1:
1274 case RT5663_DRC1_PRI_REG_2:
1275 case RT5663_DRC1_PRI_REG_3:
1276 case RT5663_DRC1_PRI_REG_4:
1277 case RT5663_DRC1_PRI_REG_5:
1278 case RT5663_DRC1_PRI_REG_6:
1279 case RT5663_DRC1_PRI_REG_7:
1280 case RT5663_DRC1_PRI_REG_8:
1281 case RT5663_ALC_PGA_CTL_1:
1282 case RT5663_ALC_PGA_CTL_2:
1283 case RT5663_ALC_PGA_CTL_3:
1284 case RT5663_ALC_PGA_CTL_4:
1285 case RT5663_ALC_PGA_CTL_5:
1286 case RT5663_ALC_PGA_CTL_6:
1287 case RT5663_ALC_PGA_CTL_7:
1288 case RT5663_ALC_PGA_CTL_8:
1289 case RT5663_ALC_PGA_REG_1:
1290 case RT5663_ALC_PGA_REG_2:
1291 case RT5663_ALC_PGA_REG_3:
1292 case RT5663_ADC_EQ_RECOV_1:
1293 case RT5663_ADC_EQ_RECOV_2:
1294 case RT5663_ADC_EQ_RECOV_3:
1295 case RT5663_ADC_EQ_RECOV_4:
1296 case RT5663_ADC_EQ_RECOV_5:
1297 case RT5663_ADC_EQ_RECOV_6:
1298 case RT5663_ADC_EQ_RECOV_7:
1299 case RT5663_ADC_EQ_RECOV_8:
1300 case RT5663_ADC_EQ_RECOV_9:
1301 case RT5663_ADC_EQ_RECOV_10:
1302 case RT5663_ADC_EQ_RECOV_11:
1303 case RT5663_ADC_EQ_RECOV_12:
1304 case RT5663_ADC_EQ_RECOV_13:
1305 case RT5663_VID_HIDDEN:
1306 case RT5663_VID_CUSTOMER:
1307 case RT5663_SCAN_MODE:
1308 case RT5663_I2C_BYPA:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1309 return true;
1310 case RT5663_TDM_1:
1311 case RT5663_DEPOP_3:
1312 case RT5663_ASRC_11_2:
1313 case RT5663_INT_ST_2:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1314 case RT5663_GPIO_STA1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1315 case RT5663_SIN_GEN_1:
1316 case RT5663_SIN_GEN_2:
1317 case RT5663_SIN_GEN_3:
1318 case RT5663_IL_CMD_PWRSAV1:
1319 case RT5663_IL_CMD_PWRSAV2:
1320 case RT5663_EM_JACK_TYPE_1:
1321 case RT5663_EM_JACK_TYPE_2:
1322 case RT5663_EM_JACK_TYPE_3:
1323 case RT5663_EM_JACK_TYPE_4:
1324 case RT5663_FAST_OFF_MICBIAS:
1325 case RT5663_ANA_BIAS_CUR_1:
1326 case RT5663_ANA_BIAS_CUR_2:
1327 case RT5663_BIAS_CUR_9:
1328 case RT5663_DUMMY_REG_4:
1329 case RT5663_VREF_RECMIX:
1330 case RT5663_CHARGE_PUMP_1_2:
1331 case RT5663_CHARGE_PUMP_1_3:
1332 case RT5663_CHARGE_PUMP_2:
1333 case RT5663_CHOP_DAC_R:
1334 case RT5663_DUMMY_CTL_DACLR:
1335 case RT5663_DUMMY_REG_5:
1336 case RT5663_SOFT_RAMP:
1337 case RT5663_TEST_MODE_1:
1338 case RT5663_STO_DRE_10:
1339 case RT5663_MIC_DECRO_1:
1340 case RT5663_MIC_DECRO_2:
1341 case RT5663_MIC_DECRO_3:
1342 case RT5663_MIC_DECRO_4:
1343 case RT5663_MIC_DECRO_5:
1344 case RT5663_MIC_DECRO_6:
1345 case RT5663_HP_DECRO_1:
1346 case RT5663_HP_DECRO_2:
1347 case RT5663_HP_DECRO_3:
1348 case RT5663_HP_DECRO_4:
1349 case RT5663_HP_DECOUP:
1350 case RT5663_HP_IMPSEN_MAP4:
1351 case RT5663_HP_IMPSEN_MAP5:
1352 case RT5663_HP_IMPSEN_MAP7:
1353 case RT5663_HP_CALIB_1:
1354 case RT5663_CBJ_1:
1355 case RT5663_CBJ_2:
1356 case RT5663_CBJ_3:
1357 return false;
1358 default:
1359 return rt5663_readable_register(dev, reg);
1360 }
1361}
1362
1363static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1364static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1365static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1366static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1367
1368/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1369static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1370 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1371 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1372 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1373 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1374 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1375 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1376 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1377);
1378
1379/* Interface data select */
1380static const char * const rt5663_if1_adc_data_select[] = {
1381 "L/R", "R/L", "L/L", "R/R"
1382};
1383
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]1384static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1385 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1386
1387static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1388 bool enable)
1389{
1390 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1391
1392 if (enable) {
1393 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1394 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1395 /* reset in-line command */
1396 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1397 RT5663_RESET_4BTN_INL_MASK,
1398 RT5663_RESET_4BTN_INL_RESET);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1399 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1400 RT5663_RESET_4BTN_INL_MASK,
1401 RT5663_RESET_4BTN_INL_NOR);
1402 switch (rt5663->codec_ver) {
1403 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1404 snd_soc_update_bits(codec, RT5663_IRQ_3,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1405 RT5663_V2_EN_IRQ_INLINE_MASK,
1406 RT5663_V2_EN_IRQ_INLINE_NOR);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1407 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1408 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1409 snd_soc_update_bits(codec, RT5663_IRQ_2,
1410 RT5663_EN_IRQ_INLINE_MASK,
1411 RT5663_EN_IRQ_INLINE_NOR);
1412 break;
1413 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1414 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1415 }
1416 } else {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1417 switch (rt5663->codec_ver) {
1418 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1419 snd_soc_update_bits(codec, RT5663_IRQ_3,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1420 RT5663_V2_EN_IRQ_INLINE_MASK,
1421 RT5663_V2_EN_IRQ_INLINE_BYP);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1422 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1423 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1424 snd_soc_update_bits(codec, RT5663_IRQ_2,
1425 RT5663_EN_IRQ_INLINE_MASK,
1426 RT5663_EN_IRQ_INLINE_BYP);
1427 break;
1428 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1429 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1430 }
1431 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1432 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1433 /* reset in-line command */
1434 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1435 RT5663_RESET_4BTN_INL_MASK,
1436 RT5663_RESET_4BTN_INL_RESET);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1437 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1438 RT5663_RESET_4BTN_INL_MASK,
1439 RT5663_RESET_4BTN_INL_NOR);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1440 }
1441}
1442
1443/**
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1444 * rt5663_v2_jack_detect - Detect headset.
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1445 * @codec: SoC audio codec device.
1446 * @jack_insert: Jack insert or not.
1447 *
1448 * Detect whether is headset or not when jack inserted.
1449 *
1450 * Returns detect status.
1451 */
1452
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1453static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1454{
1455 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1456 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1457 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1458
1459 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1460 if (jack_insert) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1461 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1462 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1463
1464 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1465 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1466 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1467 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1468 snd_soc_dapm_sync(dapm);
1469 snd_soc_update_bits(codec, RT5663_RC_CLK,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1470 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1471 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1472
1473 while (i < 5) {
1474 msleep(sleep_time[i]);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1475 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1476 if (val == 0x1 || val == 0x2 || val == 0x3)
1477 break;
1478 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1479 __func__, val, sleep_time[i]);
1480 i++;
1481 }
1482 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1483 switch (val) {
1484 case 1:
1485 case 2:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1486 rt5663->jack_type = SND_JACK_HEADSET;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1487 rt5663_enable_push_button_irq(codec, true);
1488 break;
1489 default:
1490 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1491 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1492 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1493 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1494 snd_soc_dapm_sync(dapm);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1495 rt5663->jack_type = SND_JACK_HEADPHONE;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1496 break;
1497 }
1498 } else {
1499 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1500
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1501 if (rt5663->jack_type == SND_JACK_HEADSET) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1502 rt5663_enable_push_button_irq(codec, false);
1503 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1504 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1505 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1506 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1507 snd_soc_dapm_sync(dapm);
1508 }
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1509 rt5663->jack_type = 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1510 }
1511
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1512 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1513 return rt5663->jack_type;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1514}
1515
1516/**
1517 * rt5663_jack_detect - Detect headset.
1518 * @codec: SoC audio codec device.
1519 * @jack_insert: Jack insert or not.
1520 *
1521 * Detect whether is headset or not when jack inserted.
1522 *
1523 * Returns detect status.
1524 */
1525static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1526{
1527 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1528 int val, i = 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1529
1530 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1531
1532 if (jack_insert) {
1533 snd_soc_update_bits(codec, RT5663_DIG_MISC,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1534 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1535 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1536 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1537 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1538 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1539 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1540 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1541 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1542 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1543 snd_soc_update_bits(codec, RT5663_CBJ_1,
1544 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1545 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1546 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1547 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1548 /* BST1 power on for JD */
1549 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1550 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1551 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1552 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1553 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1554 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1555 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1556 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1557 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1558 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1559 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1560 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1561 snd_soc_update_bits(codec, RT5663_IRQ_1,
1562 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1563
1564 while (true) {
1565 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1566 if (!(val & 0x80))
1567 usleep_range(10000, 10005);
1568 else
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1569 break;
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1570
1571 if (i > 200)
1572 break;
1573 i++;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1574 }
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1575
1576 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1577 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
oder_chiou@realtek.com8f244122017-07-07 16:58:58 +0800[diff] [blame]1578
oder_chiou@realtek.comc5755fb2017-08-14 09:46:59 +0800[diff] [blame]1579 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1580 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1581 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1582
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1583 switch (val) {
1584 case 1:
1585 case 2:
1586 rt5663->jack_type = SND_JACK_HEADSET;
1587 rt5663_enable_push_button_irq(codec, true);
oder_chiou@realtek.com278982b2017-08-02 16:01:27 +0800[diff] [blame]1588
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]1589 if (rt5663->pdata.impedance_sensing_num)
1590 break;
1591
oder_chiou@realtek.com278982b2017-08-02 16:01:27 +0800[diff] [blame]1592 if (rt5663->pdata.dc_offset_l_manual_mic) {
1593 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1594 rt5663->pdata.dc_offset_l_manual_mic >>
1595 16);
1596 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1597 rt5663->pdata.dc_offset_l_manual_mic &
1598 0xffff);
1599 }
1600
1601 if (rt5663->pdata.dc_offset_r_manual_mic) {
1602 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1603 rt5663->pdata.dc_offset_r_manual_mic >>
1604 16);
1605 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1606 rt5663->pdata.dc_offset_r_manual_mic &
1607 0xffff);
1608 }
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1609 break;
1610 default:
1611 rt5663->jack_type = SND_JACK_HEADPHONE;
oder_chiou@realtek.com278982b2017-08-02 16:01:27 +0800[diff] [blame]1612
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]1613 if (rt5663->pdata.impedance_sensing_num)
1614 break;
1615
oder_chiou@realtek.com278982b2017-08-02 16:01:27 +0800[diff] [blame]1616 if (rt5663->pdata.dc_offset_l_manual) {
1617 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1618 rt5663->pdata.dc_offset_l_manual >> 16);
1619 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1620 rt5663->pdata.dc_offset_l_manual &
1621 0xffff);
1622 }
1623
1624 if (rt5663->pdata.dc_offset_r_manual) {
1625 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1626 rt5663->pdata.dc_offset_r_manual >> 16);
1627 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1628 rt5663->pdata.dc_offset_r_manual &
1629 0xffff);
1630 }
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1631 break;
1632 }
1633 } else {
1634 if (rt5663->jack_type == SND_JACK_HEADSET)
1635 rt5663_enable_push_button_irq(codec, false);
1636 rt5663->jack_type = 0;
1637 }
1638
1639 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1640 return rt5663->jack_type;
1641}
1642
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]1643static int rt5663_impedance_sensing(struct snd_soc_codec *codec)
1644{
1645 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1646 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1647
1648 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1649 if (rt5663->imp_table[i].vol == 7)
1650 break;
1651 }
1652
1653 if (rt5663->jack_type == SND_JACK_HEADSET) {
1654 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1655 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1656 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1657 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1658 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1659 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1660 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1661 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1662 } else {
1663 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1664 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1665 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1666 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1667 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1668 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1669 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1670 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1671 }
1672
1673 reg84 = snd_soc_read(codec, RT5663_ASRC_2);
1674 reg26 = snd_soc_read(codec, RT5663_STO1_ADC_MIXER);
1675 reg2fa = snd_soc_read(codec, RT5663_DUMMY_1);
1676 reg91 = snd_soc_read(codec, RT5663_HP_CHARGE_PUMP_1);
1677 reg10 = snd_soc_read(codec, RT5663_RECMIX);
1678 reg80 = snd_soc_read(codec, RT5663_GLB_CLK);
1679
1680 snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000, 0);
1681 snd_soc_write(codec, RT5663_ASRC_2, 0);
1682 snd_soc_write(codec, RT5663_STO1_ADC_MIXER, 0x4040);
1683 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1684 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1685 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1686 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1687 usleep_range(10000, 10005);
1688 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1689 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1690 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1691 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1692 RT5663_SCLK_SRC_RCCLK);
1693 snd_soc_update_bits(codec, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1694 RT5663_DIG_25M_CLK_EN);
1695 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1696 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
1697 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
1698 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1699 snd_soc_write(codec, RT5663_HP_LOGIC_2, 0x0005);
1700 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
1701 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0030);
1702 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0x0003);
1703 snd_soc_update_bits(codec, RT5663_PWR_DIG_2,
1704 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1705 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1706 snd_soc_update_bits(codec, RT5663_PWR_DIG_1,
1707 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1708 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1709 RT5663_PWR_ADC_R1,
1710 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1711 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1712 RT5663_PWR_ADC_R1);
1713 msleep(40);
1714 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1715 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1716 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1717 msleep(30);
1718 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1719 snd_soc_write(codec, RT5663_STO_DAC_MIXER, 0);
1720 snd_soc_write(codec, RT5663_BYPASS_STO_DAC, 0x000c);
1721 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
1722 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
1723 snd_soc_write(codec, RT5663_HP_OUT_EN, 0x8088);
1724 snd_soc_write(codec, RT5663_CHOP_ADC, 0x3000);
1725 snd_soc_write(codec, RT5663_ADDA_RST, 0xc000);
1726 snd_soc_write(codec, RT5663_STO1_HPF_ADJ1, 0x3320);
1727 snd_soc_write(codec, RT5663_HP_CALIB_2, 0x00c9);
1728 snd_soc_write(codec, RT5663_DUMMY_1, 0x004c);
1729 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7733);
1730 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
1731 snd_soc_write(codec, RT5663_STO_DRE_9, 0x0007);
1732 snd_soc_write(codec, RT5663_STO_DRE_10, 0x0007);
1733 snd_soc_write(codec, RT5663_DUMMY_2, 0x02a4);
1734 snd_soc_write(codec, RT5663_RECMIX, 0x0005);
1735 snd_soc_write(codec, RT5663_HP_IMP_SEN_1, 0x4334);
1736 snd_soc_update_bits(codec, RT5663_IRQ_3, 0x0004, 0x0004);
1737 snd_soc_write(codec, RT5663_HP_LOGIC_1, 0x2200);
1738 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x3000);
1739 snd_soc_write(codec, RT5663_HP_LOGIC_1, 0x6200);
1740
1741 for (i = 0; i < 100; i++) {
1742 msleep(20);
1743 if (snd_soc_read(codec, RT5663_INT_ST_1) & 0x2)
1744 break;
1745 }
1746
1747 value = snd_soc_read(codec, RT5663_HP_IMP_SEN_4);
1748
1749 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0);
1750 snd_soc_write(codec, RT5663_INT_ST_1, 0);
1751 snd_soc_write(codec, RT5663_HP_LOGIC_1, 0);
1752 snd_soc_update_bits(codec, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1753 RT5663_DIG_25M_CLK_DIS);
1754 snd_soc_write(codec, RT5663_GLB_CLK, reg80);
1755 snd_soc_write(codec, RT5663_RECMIX, reg10);
1756 snd_soc_write(codec, RT5663_DUMMY_2, 0x00a4);
1757 snd_soc_write(codec, RT5663_DUMMY_1, reg2fa);
1758 snd_soc_write(codec, RT5663_HP_CALIB_2, 0x00c8);
1759 snd_soc_write(codec, RT5663_STO1_HPF_ADJ1, 0xb320);
1760 snd_soc_write(codec, RT5663_ADDA_RST, 0xe400);
1761 snd_soc_write(codec, RT5663_CHOP_ADC, 0x2000);
1762 snd_soc_write(codec, RT5663_HP_OUT_EN, 0x0008);
1763 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1764 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1765 snd_soc_update_bits(codec, RT5663_PWR_DIG_1,
1766 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1767 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1768 RT5663_PWR_ADC_R1, 0);
1769 snd_soc_update_bits(codec, RT5663_PWR_DIG_2,
1770 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1771 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0);
1772 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0);
1773 snd_soc_write(codec, RT5663_HP_LOGIC_2, 0);
1774 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_1, reg91);
1775 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1776 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1777 snd_soc_write(codec, RT5663_STO1_ADC_MIXER, reg26);
1778 snd_soc_write(codec, RT5663_ASRC_2, reg84);
1779
1780 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1781 if (value >= rt5663->imp_table[i].imp_min &&
1782 value <= rt5663->imp_table[i].imp_max)
1783 break;
1784 }
1785
1786 snd_soc_update_bits(codec, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1787 rt5663->imp_table[i].vol);
1788 snd_soc_update_bits(codec, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1789 rt5663->imp_table[i].vol);
1790
1791 if (rt5663->jack_type == SND_JACK_HEADSET) {
1792 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1793 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1794 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1795 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1796 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1797 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1798 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1799 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1800 } else {
1801 snd_soc_write(codec, RT5663_MIC_DECRO_2,
1802 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1803 snd_soc_write(codec, RT5663_MIC_DECRO_3,
1804 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1805 snd_soc_write(codec, RT5663_MIC_DECRO_5,
1806 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1807 snd_soc_write(codec, RT5663_MIC_DECRO_6,
1808 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1809 }
1810
1811 return 0;
1812}
1813
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]1814static int rt5663_button_detect(struct snd_soc_codec *codec)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1815{
1816 int btn_type, val;
1817
1818 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1819 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1820 btn_type = val & 0xfff0;
1821 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1822
1823 return btn_type;
1824}
1825
1826static irqreturn_t rt5663_irq(int irq, void *data)
1827{
1828 struct rt5663_priv *rt5663 = data;
1829
oder_chiou@realtek.coma16cc632017-09-25 11:11:05 +0800[diff] [blame]1830 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1831 __func__);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1832
1833 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1834 msecs_to_jiffies(250));
1835
1836 return IRQ_HANDLED;
1837}
1838
1839int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1840 struct snd_soc_jack *hs_jack)
1841{
1842 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1843
1844 rt5663->hs_jack = hs_jack;
1845
1846 rt5663_irq(0, rt5663);
1847
1848 return 0;
1849}
1850EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1851
1852static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1853{
1854 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1855 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1856
1857 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1858
1859 /* JD1 */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1860 switch (rt5663->codec_ver) {
1861 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1862 return !(val & 0x2000);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1863 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1864 return !(val & 0x1000);
1865 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1866 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1867 }
1868
1869 return false;
1870}
1871
1872static void rt5663_jack_detect_work(struct work_struct *work)
1873{
1874 struct rt5663_priv *rt5663 =
1875 container_of(work, struct rt5663_priv, jack_detect_work.work);
1876 struct snd_soc_codec *codec = rt5663->codec;
1877 int btn_type, report = 0;
1878
1879 if (!codec)
1880 return;
1881
1882 if (rt5663_check_jd_status(codec)) {
1883 /* jack in */
1884 if (rt5663->jack_type == 0) {
1885 /* jack was out, report jack type */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1886 switch (rt5663->codec_ver) {
1887 case CODEC_VER_1:
1888 report = rt5663_v2_jack_detect(
1889 rt5663->codec, 1);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1890 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1891 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1892 report = rt5663_jack_detect(rt5663->codec, 1);
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]1893 if (rt5663->pdata.impedance_sensing_num)
1894 rt5663_impedance_sensing(rt5663->codec);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1895 break;
1896 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1897 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1898 }
oder_chiou@realtek.com9c324af2017-08-30 13:08:31 +0800[diff] [blame]1899
1900 /* Delay the jack insert report to avoid pop noise */
1901 msleep(30);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1902 } else {
1903 /* jack is already in, report button event */
1904 report = SND_JACK_HEADSET;
1905 btn_type = rt5663_button_detect(rt5663->codec);
1906 /**
1907 * rt5663 can report three kinds of button behavior,
1908 * one click, double click and hold. However,
1909 * currently we will report button pressed/released
1910 * event. So all the three button behaviors are
1911 * treated as button pressed.
1912 */
1913 switch (btn_type) {
1914 case 0x8000:
1915 case 0x4000:
1916 case 0x2000:
1917 report |= SND_JACK_BTN_0;
1918 break;
1919 case 0x1000:
1920 case 0x0800:
1921 case 0x0400:
1922 report |= SND_JACK_BTN_1;
1923 break;
1924 case 0x0200:
1925 case 0x0100:
1926 case 0x0080:
1927 report |= SND_JACK_BTN_2;
1928 break;
1929 case 0x0040:
1930 case 0x0020:
1931 case 0x0010:
1932 report |= SND_JACK_BTN_3;
1933 break;
1934 case 0x0000: /* unpressed */
1935 break;
1936 default:
1937 btn_type = 0;
1938 dev_err(rt5663->codec->dev,
1939 "Unexpected button code 0x%04x\n",
1940 btn_type);
1941 break;
1942 }
1943 /* button release or spurious interrput*/
oder_chiou@realtek.comde6ae8a2017-11-10 13:16:44 +0800[diff] [blame]1944 if (btn_type == 0) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1945 report = rt5663->jack_type;
oder_chiou@realtek.comde6ae8a2017-11-10 13:16:44 +0800[diff] [blame]1946 cancel_delayed_work_sync(
1947 &rt5663->jd_unplug_work);
1948 } else {
1949 queue_delayed_work(system_wq,
1950 &rt5663->jd_unplug_work,
1951 msecs_to_jiffies(500));
1952 }
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1953 }
1954 } else {
1955 /* jack out */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1956 switch (rt5663->codec_ver) {
1957 case CODEC_VER_1:
1958 report = rt5663_v2_jack_detect(rt5663->codec, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1959 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1960 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1961 report = rt5663_jack_detect(rt5663->codec, 0);
1962 break;
1963 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]1964 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]1965 }
1966 }
1967 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1968 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1969 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1970 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1971}
1972
oder_chiou@realtek.comde6ae8a2017-11-10 13:16:44 +0800[diff] [blame]1973static void rt5663_jd_unplug_work(struct work_struct *work)
1974{
1975 struct rt5663_priv *rt5663 =
1976 container_of(work, struct rt5663_priv, jd_unplug_work.work);
1977 struct snd_soc_codec *codec = rt5663->codec;
1978
1979 if (!codec)
1980 return;
1981
1982 if (!rt5663_check_jd_status(codec)) {
1983 /* jack out */
1984 switch (rt5663->codec_ver) {
1985 case CODEC_VER_1:
1986 rt5663_v2_jack_detect(rt5663->codec, 0);
1987 break;
1988 case CODEC_VER_0:
1989 rt5663_jack_detect(rt5663->codec, 0);
1990 break;
1991 default:
1992 dev_err(codec->dev, "Unknown CODEC Version\n");
1993 }
1994
1995 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
1996 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1997 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1998 } else {
1999 queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2000 msecs_to_jiffies(500));
2001 }
2002}
2003
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2004static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2005 /* DAC Digital Volume */
2006 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2007 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2008 87, 0, dac_vol_tlv),
2009 /* ADC Digital Volume Control */
2010 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2011 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2012 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2013 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2014 63, 0, adc_vol_tlv),
2015};
2016
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2017static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2018 /* Headphone Output Volume */
2019 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2020 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2021 rt5663_v2_hp_vol_tlv),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2022 /* Mic Boost Volume */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2023 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2024 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2025};
2026
2027static const struct snd_kcontrol_new rt5663_specific_controls[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2028 /* Mic Boost Volume*/
2029 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2030 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2031 /* Data Swap for Slot0/1 in ADCDAT1 */
2032 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2033};
2034
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]2035static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2036 /* Headphone Output Volume */
2037 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2038 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2039 rt5663_hp_vol_tlv),
2040};
2041
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2042static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2043 struct snd_soc_dapm_widget *sink)
2044{
2045 unsigned int val;
2046 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2047
2048 val = snd_soc_read(codec, RT5663_GLB_CLK);
2049 val &= RT5663_SCLK_SRC_MASK;
2050 if (val == RT5663_SCLK_SRC_PLL1)
2051 return 1;
2052 else
2053 return 0;
2054}
2055
2056static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2057 struct snd_soc_dapm_widget *sink)
2058{
2059 unsigned int reg, shift, val;
2060 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2061 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2062
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2063 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2064 switch (w->shift) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2065 case RT5663_ADC_STO1_ASRC_SHIFT:
2066 reg = RT5663_ASRC_3;
2067 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2068 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2069 case RT5663_DAC_STO1_ASRC_SHIFT:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2070 reg = RT5663_ASRC_2;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2071 shift = RT5663_DA_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2072 break;
2073 default:
2074 return 0;
2075 }
2076 } else {
2077 switch (w->shift) {
2078 case RT5663_ADC_STO1_ASRC_SHIFT:
2079 reg = RT5663_ASRC_2;
2080 shift = RT5663_AD_STO1_TRACK_SHIFT;
2081 break;
2082 case RT5663_DAC_STO1_ASRC_SHIFT:
2083 reg = RT5663_ASRC_2;
2084 shift = RT5663_DA_STO1_TRACK_SHIFT;
2085 break;
2086 default:
2087 return 0;
2088 }
2089 }
2090
2091 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
2092
2093 if (val)
2094 return 1;
2095
2096 return 0;
2097}
2098
2099static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2100 struct snd_soc_dapm_widget *sink)
2101{
2102 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
2103 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2104 int da_asrc_en, ad_asrc_en;
2105
2106 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
2107 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2108 switch (rt5663->codec_ver) {
2109 case CODEC_VER_1:
2110 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
2111 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2112 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2113 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2114 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
2115 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2116 break;
2117 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2118 dev_err(codec->dev, "Unknown CODEC Version\n");
Arnd Bergmann56efaed2016-09-15 17:42:21 +0200[diff] [blame]2119 return 1;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2120 }
2121
2122 if (da_asrc_en || ad_asrc_en)
2123 if (rt5663->sysclk > rt5663->lrck * 384)
2124 return 1;
2125
2126 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2127
2128 return 0;
2129}
2130
2131/**
2132 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2133 * @codec: SoC audio codec device.
2134 * @filter_mask: mask of filters.
2135 * @clk_src: clock source
2136 *
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2137 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2138 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2139 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2140 * ASRC function will track i2s clock and generate a corresponding system clock
2141 * for codec. This function provides an API to select the clock source for a
2142 * set of filters specified by the mask. And the codec driver will turn on ASRC
2143 * for these filters if ASRC is selected as their clock source.
2144 */
2145int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
2146 unsigned int filter_mask, unsigned int clk_src)
2147{
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2148 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2149 unsigned int asrc2_mask = 0;
2150 unsigned int asrc2_value = 0;
2151 unsigned int asrc3_mask = 0;
2152 unsigned int asrc3_value = 0;
2153
2154 switch (clk_src) {
2155 case RT5663_CLK_SEL_SYS:
2156 case RT5663_CLK_SEL_I2S1_ASRC:
2157 break;
2158
2159 default:
2160 return -EINVAL;
2161 }
2162
2163 if (filter_mask & RT5663_DA_STEREO_FILTER) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2164 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2165 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2166 }
2167
2168 if (filter_mask & RT5663_AD_STEREO_FILTER) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2169 switch (rt5663->codec_ver) {
2170 case CODEC_VER_1:
2171 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2172 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2173 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2174 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2175 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2176 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2177 break;
2178 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2179 dev_err(codec->dev, "Unknown CODEC Version\n");
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2180 }
2181 }
2182
2183 if (asrc2_mask)
2184 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
2185 asrc2_value);
2186
2187 if (asrc3_mask)
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2188 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2189 asrc3_value);
2190
2191 return 0;
2192}
2193EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2194
2195/* Analog Mixer */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2196static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2197 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2198 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2199 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2200 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2201};
2202
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2203static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2204 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2205 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2206};
2207
2208/* Digital Mixer */
2209static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2210 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2211 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2212 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2213 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2214};
2215
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2216static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2217 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2218 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2219 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2220 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2221};
2222
2223static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2224 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2225 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2226 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2227 RT5663_M_DAC1_L_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2228};
2229
2230static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2231 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2232 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2233 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2234 RT5663_M_DAC1_R_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2235};
2236
2237static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2238 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2239 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2240};
2241
2242static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2243 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2244 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2245};
2246
2247/* Out Switch */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2248static const struct snd_kcontrol_new rt5663_hpo_switch =
2249 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2250 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2251
2252/* Stereo ADC source */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2253static const char * const rt5663_sto1_adc_src[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2254 "ADC L", "ADC R"
2255};
2256
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2257static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2258 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2259
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2260static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2261 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2262
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2263static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2264 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2265
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2266static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2267 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2268
2269/* RT5663: Analog DACL1 input source */
2270static const char * const rt5663_alg_dacl_src[] = {
2271 "DAC L", "STO DAC MIXL"
2272};
2273
2274static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2275 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2276
2277static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2278 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2279
2280/* RT5663: Analog DACR1 input source */
2281static const char * const rt5663_alg_dacr_src[] = {
2282 "DAC R", "STO DAC MIXR"
2283};
2284
2285static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2286 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2287
2288static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2289 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2290
2291static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2292 struct snd_kcontrol *kcontrol, int event)
2293{
2294 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2295 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2296
2297 switch (event) {
2298 case SND_SOC_DAPM_POST_PMU:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2299 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2300 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2301 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2302 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2303 RT5663_HP_SIG_SRC1_MASK,
2304 RT5663_HP_SIG_SRC1_SILENCE);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2305 } else {
2306 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2307 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2308 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2309 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2310 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2311 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2312 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2313 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2314 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
oder_chiou@realtek.comc5755fb2017-08-14 09:46:59 +0800[diff] [blame]2315 snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000,
2316 0x8000);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2317 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2318 0x3000);
2319 }
2320 break;
2321
2322 case SND_SOC_DAPM_PRE_PMD:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2323 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2324 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2325 RT5663_HP_SIG_SRC1_MASK,
2326 RT5663_HP_SIG_SRC1_REG);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2327 } else {
2328 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2329 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2330 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2331 }
2332 break;
2333
2334 default:
2335 return 0;
2336 }
2337
2338 return 0;
2339}
2340
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2341static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2342 struct snd_kcontrol *kcontrol, int event)
2343{
2344 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2345 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2346
2347 switch (event) {
2348 case SND_SOC_DAPM_PRE_PMU:
oder_chiou@realtek.comc5755fb2017-08-14 09:46:59 +0800[diff] [blame]2349 if (rt5663->codec_ver == CODEC_VER_0) {
2350 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2351 0x0030);
2352 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003,
2353 0x0003);
2354 }
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2355 break;
2356
2357 case SND_SOC_DAPM_POST_PMD:
oder_chiou@realtek.comc5755fb2017-08-14 09:46:59 +0800[diff] [blame]2358 if (rt5663->codec_ver == CODEC_VER_0) {
2359 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0);
2360 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2361 }
2362 break;
2363
2364 default:
2365 return 0;
2366 }
2367
2368 return 0;
2369}
2370
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2371static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2372 struct snd_kcontrol *kcontrol, int event)
2373{
2374 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2375
2376 switch (event) {
2377 case SND_SOC_DAPM_POST_PMU:
2378 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2379 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2380 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2381 break;
2382
2383 case SND_SOC_DAPM_PRE_PMD:
2384 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2385 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2386 break;
2387
2388 default:
2389 return 0;
2390 }
2391
2392 return 0;
2393}
2394
2395static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2396 struct snd_kcontrol *kcontrol, int event)
2397{
2398 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2399
2400 switch (event) {
2401 case SND_SOC_DAPM_POST_PMU:
2402 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2403 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2404 break;
2405
2406 case SND_SOC_DAPM_PRE_PMD:
2407 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2408 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2409 break;
2410
2411 default:
2412 return 0;
2413 }
2414
2415 return 0;
2416}
2417
2418static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2419 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2420 NULL, 0),
2421
2422 /* micbias */
2423 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2424 RT5663_PWR_MB1_SHIFT, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2425 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2426 RT5663_PWR_MB2_SHIFT, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2427
2428 /* Input Lines */
2429 SND_SOC_DAPM_INPUT("IN1P"),
2430 SND_SOC_DAPM_INPUT("IN1N"),
2431
2432 /* REC Mixer Power */
2433 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2434 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2435
2436 /* ADCs */
2437 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2438 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2439 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2440 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2441 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2442
2443 /* ADC Mixer */
2444 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2445 0, 0, rt5663_sto1_adc_l_mix,
2446 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2447
2448 /* ADC Filter Power */
2449 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2450 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2451
2452 /* Digital Interface */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2453 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2454 NULL, 0),
2455 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2456 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2457 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2458 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2459 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2460
2461 /* Audio Interface */
2462 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2463 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2464
2465 /* DAC mixer before sound effect */
2466 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2467 ARRAY_SIZE(rt5663_adda_l_mix)),
2468 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2469 ARRAY_SIZE(rt5663_adda_r_mix)),
2470 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2471 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2472
2473 /* DAC Mixer */
2474 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2475 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2476 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2477 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2478 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2479 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2480
2481 /* DACs */
2482 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2483 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2484 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2485 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2486 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2487 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2488
2489 /* Headphone*/
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2490 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2491 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2492 SND_SOC_DAPM_POST_PMD),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2493 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2494 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2495
2496 /* Output Lines */
2497 SND_SOC_DAPM_OUTPUT("HPOL"),
2498 SND_SOC_DAPM_OUTPUT("HPOR"),
2499};
2500
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2501static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2502 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2503 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2504 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2505 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2506 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2507 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2508
2509 /* ASRC */
2510 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2511 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2512 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2513 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2514 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2515 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2516
2517 /* Input Lines */
2518 SND_SOC_DAPM_INPUT("IN2P"),
2519 SND_SOC_DAPM_INPUT("IN2N"),
2520
2521 /* Boost */
2522 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2523 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2524 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2525 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2526 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2527 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2528 SND_SOC_DAPM_POST_PMU),
2529
2530 /* REC Mixer */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2531 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2532 ARRAY_SIZE(rt5663_recmix1l)),
2533 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2534 ARRAY_SIZE(rt5663_recmix1r)),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2535 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2536 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2537
2538 /* ADC */
2539 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2540 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2541 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2542
2543 /* ADC Mux */
2544 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2545 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2546 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2547 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2548 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2549 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2550 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2551 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2552
2553 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2554 &rt5663_sto1_adcl_mux),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2555 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2556 &rt5663_sto1_adcr_mux),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2557
2558 /* ADC Mix */
2559 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2560 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2561
2562 /* Analog DAC Clock */
2563 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2564 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2565
2566 /* Headphone out */
2567 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2568 &rt5663_hpo_switch),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2569};
2570
2571static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2572 /* System Clock Pre Divider Gating */
2573 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2574 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2575 SND_SOC_DAPM_PRE_PMD),
2576
2577 /* LDO */
2578 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2579 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2580
2581 /* ASRC */
2582 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2583 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2584 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2585 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2586 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2587 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2588
2589 /* Boost */
2590 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2591
2592 /* STO ADC */
2593 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2594 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2595
2596 /* Analog DAC source */
2597 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2598 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2599};
2600
2601static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2602 /* PLL */
2603 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2604
2605 /* ASRC */
2606 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2607 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2608 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2609
2610 { "ADC L", NULL, "ADC L Power" },
2611 { "ADC L", NULL, "ADC Clock" },
2612
2613 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2614
2615 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2616 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2617 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2618
2619 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2620 { "IF ADC", NULL, "IF1 ADC1" },
2621 { "AIFTX", NULL, "IF ADC" },
2622 { "AIFTX", NULL, "I2S" },
2623
2624 { "AIFRX", NULL, "I2S" },
2625 { "IF DAC", NULL, "AIFRX" },
2626 { "IF1 DAC1 L", NULL, "IF DAC" },
2627 { "IF1 DAC1 R", NULL, "IF DAC" },
2628
2629 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2630 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2631 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2632 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2633 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2634 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2635 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2636
2637 { "DAC L1", NULL, "ADDA MIXL" },
2638 { "DAC R1", NULL, "ADDA MIXR" },
2639
2640 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2641 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2642 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2643 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2644 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2645 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2646
oder_chiou@realtek.com13257342017-07-07 16:58:59 +0800[diff] [blame]2647 { "HP Amp", NULL, "HP Charge Pump" },
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2648 { "HP Amp", NULL, "DAC L" },
2649 { "HP Amp", NULL, "DAC R" },
2650};
2651
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2652static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2653 { "MICBIAS1", NULL, "LDO2" },
2654 { "MICBIAS2", NULL, "LDO2" },
2655
2656 { "BST1 CBJ", NULL, "IN1P" },
2657 { "BST1 CBJ", NULL, "IN1N" },
2658 { "BST1 CBJ", NULL, "CBJ Power" },
2659
2660 { "BST2", NULL, "IN2P" },
2661 { "BST2", NULL, "IN2N" },
2662 { "BST2", NULL, "BST2 Power" },
2663
2664 { "RECMIX1L", "BST2 Switch", "BST2" },
2665 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2666 { "RECMIX1L", NULL, "RECMIX1L Power" },
2667 { "RECMIX1R", "BST2 Switch", "BST2" },
2668 { "RECMIX1R", NULL, "RECMIX1R Power" },
2669
2670 { "ADC L", NULL, "RECMIX1L" },
2671 { "ADC R", NULL, "RECMIX1R" },
2672 { "ADC R", NULL, "ADC R Power" },
2673 { "ADC R", NULL, "ADC Clock" },
2674
2675 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2676 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2677 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2678
2679 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2680 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2681 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2682 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2683
2684 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2685 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2686 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2687
2688 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2689
2690 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2691
2692 { "DAC L", NULL, "STO1 DAC MIXL" },
2693 { "DAC L", NULL, "LDO DAC" },
2694 { "DAC L", NULL, "DAC Clock" },
2695 { "DAC R", NULL, "STO1 DAC MIXR" },
2696 { "DAC R", NULL, "LDO DAC" },
2697 { "DAC R", NULL, "DAC Clock" },
2698
2699 { "HPO Playback", "Switch", "HP Amp" },
2700 { "HPOL", NULL, "HPO Playback" },
2701 { "HPOR", NULL, "HPO Playback" },
2702};
2703
2704static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2705 { "I2S", NULL, "Pre Div Power" },
2706
2707 { "BST1", NULL, "IN1P" },
2708 { "BST1", NULL, "IN1N" },
2709 { "BST1", NULL, "RECMIX1L Power" },
2710
2711 { "ADC L", NULL, "BST1" },
2712
2713 { "STO1 ADC L1", NULL, "ADC L" },
2714
2715 { "DAC L Mux", "DAC L", "DAC L1" },
2716 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2717 { "DAC R Mux", "DAC R", "DAC R1"},
2718 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2719
2720 { "DAC L", NULL, "DAC L Mux" },
2721 { "DAC R", NULL, "DAC R Mux" },
2722
2723 { "HPOL", NULL, "HP Amp" },
2724 { "HPOR", NULL, "HP Amp" },
2725};
2726
2727static int rt5663_hw_params(struct snd_pcm_substream *substream,
2728 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2729{
2730 struct snd_soc_codec *codec = dai->codec;
2731 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2732 unsigned int val_len = 0;
2733 int pre_div;
2734
2735 rt5663->lrck = params_rate(params);
2736
2737 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2738 rt5663->lrck, rt5663->sysclk);
2739
2740 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2741 if (pre_div < 0) {
2742 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2743 rt5663->lrck, dai->id);
2744 return -EINVAL;
2745 }
2746
2747 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2748
2749 switch (params_width(params)) {
2750 case 8:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2751 val_len = RT5663_I2S_DL_8;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2752 break;
2753 case 16:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2754 val_len = RT5663_I2S_DL_16;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2755 break;
2756 case 20:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2757 val_len = RT5663_I2S_DL_20;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2758 break;
2759 case 24:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2760 val_len = RT5663_I2S_DL_24;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2761 break;
2762 default:
2763 return -EINVAL;
2764 }
2765
2766 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2767 RT5663_I2S_DL_MASK, val_len);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2768
2769 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2770 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2771
2772 return 0;
2773}
2774
2775static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2776{
2777 struct snd_soc_codec *codec = dai->codec;
2778 unsigned int reg_val = 0;
2779
2780 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2781 case SND_SOC_DAIFMT_CBM_CFM:
2782 break;
2783 case SND_SOC_DAIFMT_CBS_CFS:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2784 reg_val |= RT5663_I2S_MS_S;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2785 break;
2786 default:
2787 return -EINVAL;
2788 }
2789
2790 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2791 case SND_SOC_DAIFMT_NB_NF:
2792 break;
2793 case SND_SOC_DAIFMT_IB_NF:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2794 reg_val |= RT5663_I2S_BP_INV;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2795 break;
2796 default:
2797 return -EINVAL;
2798 }
2799
2800 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2801 case SND_SOC_DAIFMT_I2S:
2802 break;
2803 case SND_SOC_DAIFMT_LEFT_J:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2804 reg_val |= RT5663_I2S_DF_LEFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2805 break;
2806 case SND_SOC_DAIFMT_DSP_A:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2807 reg_val |= RT5663_I2S_DF_PCM_A;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2808 break;
2809 case SND_SOC_DAIFMT_DSP_B:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2810 reg_val |= RT5663_I2S_DF_PCM_B;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2811 break;
2812 default:
2813 return -EINVAL;
2814 }
2815
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2816 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2817 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2818
2819 return 0;
2820}
2821
2822static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2823 unsigned int freq, int dir)
2824{
2825 struct snd_soc_codec *codec = dai->codec;
2826 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2827 unsigned int reg_val = 0;
2828
2829 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2830 return 0;
2831
2832 switch (clk_id) {
2833 case RT5663_SCLK_S_MCLK:
2834 reg_val |= RT5663_SCLK_SRC_MCLK;
2835 break;
2836 case RT5663_SCLK_S_PLL1:
2837 reg_val |= RT5663_SCLK_SRC_PLL1;
2838 break;
2839 case RT5663_SCLK_S_RCCLK:
2840 reg_val |= RT5663_SCLK_SRC_RCCLK;
2841 break;
2842 default:
2843 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2844 return -EINVAL;
2845 }
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2846 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2847 reg_val);
2848 rt5663->sysclk = freq;
2849 rt5663->sysclk_src = clk_id;
2850
2851 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2852 freq, clk_id);
2853
2854 return 0;
2855}
2856
2857static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2858 unsigned int freq_in, unsigned int freq_out)
2859{
2860 struct snd_soc_codec *codec = dai->codec;
2861 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2862 struct rl6231_pll_code pll_code;
2863 int ret;
2864 int mask, shift, val;
2865
2866 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2867 freq_out == rt5663->pll_out)
2868 return 0;
2869
2870 if (!freq_in || !freq_out) {
2871 dev_dbg(codec->dev, "PLL disabled\n");
2872
2873 rt5663->pll_in = 0;
2874 rt5663->pll_out = 0;
2875 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2876 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2877 return 0;
2878 }
2879
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2880 switch (rt5663->codec_ver) {
2881 case CODEC_VER_1:
2882 mask = RT5663_V2_PLL1_SRC_MASK;
2883 shift = RT5663_V2_PLL1_SRC_SHIFT;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2884 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2885 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2886 mask = RT5663_PLL1_SRC_MASK;
2887 shift = RT5663_PLL1_SRC_SHIFT;
2888 break;
2889 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2890 dev_err(codec->dev, "Unknown CODEC Version\n");
Arnd Bergmann56efaed2016-09-15 17:42:21 +0200[diff] [blame]2891 return -EINVAL;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2892 }
2893
2894 switch (source) {
2895 case RT5663_PLL1_S_MCLK:
2896 val = 0x0;
2897 break;
2898 case RT5663_PLL1_S_BCLK1:
2899 val = 0x1;
2900 break;
2901 default:
2902 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2903 return -EINVAL;
2904 }
2905 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2906
2907 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2908 if (ret < 0) {
2909 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2910 return ret;
2911 }
2912
2913 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2914 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2915 pll_code.k_code);
2916
2917 snd_soc_write(codec, RT5663_PLL_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2918 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2919 snd_soc_write(codec, RT5663_PLL_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2920 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2921 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2922
2923 rt5663->pll_in = freq_in;
2924 rt5663->pll_out = freq_out;
2925 rt5663->pll_src = source;
2926
2927 return 0;
2928}
2929
2930static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2931 unsigned int rx_mask, int slots, int slot_width)
2932{
2933 struct snd_soc_codec *codec = dai->codec;
2934 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2935 unsigned int val = 0, reg;
2936
2937 if (rx_mask || tx_mask)
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2938 val |= RT5663_TDM_MODE_TDM;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2939
2940 switch (slots) {
2941 case 4:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2942 val |= RT5663_TDM_IN_CH_4;
2943 val |= RT5663_TDM_OUT_CH_4;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2944 break;
2945 case 6:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2946 val |= RT5663_TDM_IN_CH_6;
2947 val |= RT5663_TDM_OUT_CH_6;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2948 break;
2949 case 8:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2950 val |= RT5663_TDM_IN_CH_8;
2951 val |= RT5663_TDM_OUT_CH_8;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2952 break;
2953 case 2:
2954 break;
2955 default:
2956 return -EINVAL;
2957 }
2958
2959 switch (slot_width) {
2960 case 20:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2961 val |= RT5663_TDM_IN_LEN_20;
2962 val |= RT5663_TDM_OUT_LEN_20;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2963 break;
2964 case 24:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2965 val |= RT5663_TDM_IN_LEN_24;
2966 val |= RT5663_TDM_OUT_LEN_24;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2967 break;
2968 case 32:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2969 val |= RT5663_TDM_IN_LEN_32;
2970 val |= RT5663_TDM_OUT_LEN_32;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2971 break;
2972 case 16:
2973 break;
2974 default:
2975 return -EINVAL;
2976 }
2977
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2978 switch (rt5663->codec_ver) {
2979 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2980 reg = RT5663_TDM_2;
2981 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2982 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2983 reg = RT5663_TDM_1;
2984 break;
2985 default:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2986 dev_err(codec->dev, "Unknown CODEC Version\n");
Arnd Bergmann56efaed2016-09-15 17:42:21 +0200[diff] [blame]2987 return -EINVAL;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2988 }
2989
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]2990 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2991 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2992 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]2993
2994 return 0;
2995}
2996
2997static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2998{
2999 struct snd_soc_codec *codec = dai->codec;
3000 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3001 unsigned int reg;
3002
3003 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
3004
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3005 if (rt5663->codec_ver == CODEC_VER_1)
3006 reg = RT5663_TDM_9;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3007 else
3008 reg = RT5663_TDM_5;
3009
3010 switch (ratio) {
3011 case 32:
3012 snd_soc_update_bits(codec, reg,
3013 RT5663_TDM_LENGTN_MASK,
3014 RT5663_TDM_LENGTN_16);
3015 break;
3016 case 40:
3017 snd_soc_update_bits(codec, reg,
3018 RT5663_TDM_LENGTN_MASK,
3019 RT5663_TDM_LENGTN_20);
3020 break;
3021 case 48:
3022 snd_soc_update_bits(codec, reg,
3023 RT5663_TDM_LENGTN_MASK,
3024 RT5663_TDM_LENGTN_24);
3025 break;
3026 case 64:
3027 snd_soc_update_bits(codec, reg,
3028 RT5663_TDM_LENGTN_MASK,
3029 RT5663_TDM_LENGTN_32);
3030 break;
3031 default:
3032 dev_err(codec->dev, "Invalid ratio!\n");
3033 return -EINVAL;
3034 }
3035
3036 return 0;
3037}
3038
3039static int rt5663_set_bias_level(struct snd_soc_codec *codec,
3040 enum snd_soc_bias_level level)
3041{
3042 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3043
3044 switch (level) {
3045 case SND_SOC_BIAS_ON:
3046 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3047 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3048 RT5663_PWR_FV1 | RT5663_PWR_FV2);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3049 break;
3050
3051 case SND_SOC_BIAS_PREPARE:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3052 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3053 snd_soc_update_bits(codec, RT5663_DIG_MISC,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3054 RT5663_DIG_GATE_CTRL_MASK,
3055 RT5663_DIG_GATE_CTRL_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3056 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3057 RT5663_EN_ANA_CLK_DET_MASK |
3058 RT5663_PWR_CLK_DET_MASK,
3059 RT5663_EN_ANA_CLK_DET_AUTO |
3060 RT5663_PWR_CLK_DET_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3061 }
3062 break;
3063
3064 case SND_SOC_BIAS_STANDBY:
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3065 if (rt5663->codec_ver == CODEC_VER_1)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3066 snd_soc_update_bits(codec, RT5663_DIG_MISC,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3067 RT5663_DIG_GATE_CTRL_MASK,
3068 RT5663_DIG_GATE_CTRL_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3069 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3070 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3071 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3072 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3073 RT5663_PWR_VREF2 | RT5663_PWR_MB);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3074 usleep_range(10000, 10005);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3075 if (rt5663->codec_ver == CODEC_VER_1) {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3076 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3077 RT5663_EN_ANA_CLK_DET_MASK |
3078 RT5663_PWR_CLK_DET_MASK,
3079 RT5663_EN_ANA_CLK_DET_DIS |
3080 RT5663_PWR_CLK_DET_DIS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3081 }
3082 break;
3083
3084 case SND_SOC_BIAS_OFF:
3085 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3086 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3087 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3088 break;
3089
3090 default:
3091 break;
3092 }
3093
3094 return 0;
3095}
3096
3097static int rt5663_probe(struct snd_soc_codec *codec)
3098{
3099 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
3100 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3101
3102 rt5663->codec = codec;
3103
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3104 switch (rt5663->codec_ver) {
3105 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3106 snd_soc_dapm_new_controls(dapm,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3107 rt5663_v2_specific_dapm_widgets,
3108 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3109 snd_soc_dapm_add_routes(dapm,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3110 rt5663_v2_specific_dapm_routes,
3111 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3112 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
3113 ARRAY_SIZE(rt5663_v2_specific_controls));
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3114 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3115 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3116 snd_soc_dapm_new_controls(dapm,
3117 rt5663_specific_dapm_widgets,
3118 ARRAY_SIZE(rt5663_specific_dapm_widgets));
3119 snd_soc_dapm_add_routes(dapm,
3120 rt5663_specific_dapm_routes,
3121 ARRAY_SIZE(rt5663_specific_dapm_routes));
3122 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
3123 ARRAY_SIZE(rt5663_specific_controls));
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]3124
3125 if (!rt5663->imp_table)
3126 snd_soc_add_codec_controls(codec, rt5663_hpvol_controls,
3127 ARRAY_SIZE(rt5663_hpvol_controls));
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3128 break;
3129 }
3130
3131 return 0;
3132}
3133
3134static int rt5663_remove(struct snd_soc_codec *codec)
3135{
3136 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3137
3138 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3139
3140 return 0;
3141}
3142
3143#ifdef CONFIG_PM
3144static int rt5663_suspend(struct snd_soc_codec *codec)
3145{
3146 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3147
3148 regcache_cache_only(rt5663->regmap, true);
3149 regcache_mark_dirty(rt5663->regmap);
3150
3151 return 0;
3152}
3153
3154static int rt5663_resume(struct snd_soc_codec *codec)
3155{
3156 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
3157
3158 regcache_cache_only(rt5663->regmap, false);
3159 regcache_sync(rt5663->regmap);
3160
Oder Chiou17616ce2017-06-12 11:02:17 +0800[diff] [blame]3161 rt5663_irq(0, rt5663);
3162
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3163 return 0;
3164}
3165#else
3166#define rt5663_suspend NULL
3167#define rt5663_resume NULL
3168#endif
3169
3170#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3171#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3172 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3173
Arvind Yadaveb59d732017-08-18 17:35:59 +0530[diff] [blame]3174static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3175 .hw_params = rt5663_hw_params,
3176 .set_fmt = rt5663_set_dai_fmt,
3177 .set_sysclk = rt5663_set_dai_sysclk,
3178 .set_pll = rt5663_set_dai_pll,
3179 .set_tdm_slot = rt5663_set_tdm_slot,
3180 .set_bclk_ratio = rt5663_set_bclk_ratio,
3181};
3182
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]3183static struct snd_soc_dai_driver rt5663_dai[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3184 {
3185 .name = "rt5663-aif",
3186 .id = RT5663_AIF,
3187 .playback = {
3188 .stream_name = "AIF Playback",
3189 .channels_min = 1,
3190 .channels_max = 2,
3191 .rates = RT5663_STEREO_RATES,
3192 .formats = RT5663_FORMATS,
3193 },
3194 .capture = {
3195 .stream_name = "AIF Capture",
3196 .channels_min = 1,
3197 .channels_max = 2,
3198 .rates = RT5663_STEREO_RATES,
3199 .formats = RT5663_FORMATS,
3200 },
3201 .ops = &rt5663_aif_dai_ops,
3202 },
3203};
3204
Bhumika Goyala180ba42017-08-03 21:30:19 +0530[diff] [blame]3205static const struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3206 .probe = rt5663_probe,
3207 .remove = rt5663_remove,
3208 .suspend = rt5663_suspend,
3209 .resume = rt5663_resume,
3210 .set_bias_level = rt5663_set_bias_level,
3211 .idle_bias_off = true,
3212 .component_driver = {
3213 .controls = rt5663_snd_controls,
3214 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
3215 .dapm_widgets = rt5663_dapm_widgets,
3216 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
3217 .dapm_routes = rt5663_dapm_routes,
3218 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
3219 }
3220};
3221
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3222static const struct regmap_config rt5663_v2_regmap = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3223 .reg_bits = 16,
3224 .val_bits = 16,
3225 .use_single_rw = true,
3226 .max_register = 0x07fa,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3227 .volatile_reg = rt5663_v2_volatile_register,
3228 .readable_reg = rt5663_v2_readable_register,
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3229 .cache_type = REGCACHE_RBTREE,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3230 .reg_defaults = rt5663_v2_reg,
3231 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3232};
3233
3234static const struct regmap_config rt5663_regmap = {
3235 .reg_bits = 16,
3236 .val_bits = 16,
3237 .use_single_rw = true,
3238 .max_register = 0x03f3,
3239 .volatile_reg = rt5663_volatile_register,
3240 .readable_reg = rt5663_readable_register,
3241 .cache_type = REGCACHE_RBTREE,
3242 .reg_defaults = rt5663_reg,
3243 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3244};
3245
3246static const struct regmap_config temp_regmap = {
3247 .name = "nocache",
3248 .reg_bits = 16,
3249 .val_bits = 16,
3250 .use_single_rw = true,
3251 .max_register = 0x03f3,
3252 .cache_type = REGCACHE_NONE,
3253};
3254
3255static const struct i2c_device_id rt5663_i2c_id[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3256 { "rt5663", 0 },
3257 {}
3258};
3259MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3260
3261#if defined(CONFIG_OF)
3262static const struct of_device_id rt5663_of_match[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3263 { .compatible = "realtek,rt5663", },
3264 {},
3265};
3266MODULE_DEVICE_TABLE(of, rt5663_of_match);
3267#endif
3268
3269#ifdef CONFIG_ACPI
Arvind Yadav1d891472017-07-23 22:53:25 +0530[diff] [blame]3270static const struct acpi_device_id rt5663_acpi_match[] = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3271 { "10EC5663", 0},
3272 {},
3273};
3274MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3275#endif
3276
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3277static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3278{
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3279 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3280 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3281 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3282 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3283 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3284 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3285 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3286 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3287 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3288 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3289 msleep(40);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3290 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3291 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3292 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3293 msleep(500);
3294}
3295
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3296static void rt5663_calibrate(struct rt5663_priv *rt5663)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3297{
3298 int value, count;
3299
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3300 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3301 msleep(20);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3302 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3303 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3304 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3305 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3306 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3307 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3308 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3309 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3310 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3311 msleep(30);
3312 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3313 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3314 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3315 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3316 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3317 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3318 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3319 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3320 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3321 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3322
3323 count = 0;
3324 while (true) {
3325 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3326 if (!(value & 0x80))
3327 usleep_range(10000, 10005);
3328 else
3329 break;
3330
Colin Ian King09b88522017-07-10 16:20:45 +0100[diff] [blame]3331 if (++count > 200)
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3332 break;
3333 }
3334
3335 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3336 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3337 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3338 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3339 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3340 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3341 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3342 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3343 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3344 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
oder_chiou@realtek.comc1bbaff2017-08-01 19:14:02 +0800[diff] [blame]3345 msleep(40);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3346 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3347 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3348 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3349 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3350 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3351 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3352 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3353 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3354 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3355 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3356 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3357 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3358 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3359 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3360 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3361 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3362 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3363 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3364 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3365 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3366 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3367 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3368 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3369
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3370 count = 0;
3371 while (true) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3372 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3373 if (value & 0x8000)
3374 usleep_range(10000, 10005);
3375 else
3376 break;
3377
3378 if (count > 200)
3379 return;
3380 count++;
3381 }
oder_chiou@realtek.com7d8e00c2017-07-07 16:58:57 +0800[diff] [blame]3382
3383 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3384 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3385 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3386
3387 count = 0;
3388 while (true) {
3389 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3390 if (value & 0x8000)
3391 usleep_range(10000, 10005);
3392 else
3393 break;
3394
3395 if (count > 200)
3396 return;
3397 count++;
3398 }
3399
3400 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3401 usleep_range(10000, 10005);
3402 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3403 usleep_range(10000, 10005);
3404 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3405 usleep_range(10000, 10005);
3406 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3407 usleep_range(10000, 10005);
3408 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3409 usleep_range(10000, 10005);
3410 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3411 usleep_range(10000, 10005);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3412}
3413
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3414static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3415{
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]3416 int table_size;
3417
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3418 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3419 &rt5663->pdata.dc_offset_l_manual);
3420 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3421 &rt5663->pdata.dc_offset_r_manual);
oder_chiou@realtek.com278982b2017-08-02 16:01:27 +0800[diff] [blame]3422 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3423 &rt5663->pdata.dc_offset_l_manual_mic);
3424 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3425 &rt5663->pdata.dc_offset_r_manual_mic);
Oder Chiou457c25e2017-09-18 18:14:26 +0800[diff] [blame]3426 device_property_read_u32(dev, "realtek,impedance_sensing_num",
3427 &rt5663->pdata.impedance_sensing_num);
3428
3429 if (rt5663->pdata.impedance_sensing_num) {
3430 table_size = sizeof(struct impedance_mapping_table) *
3431 rt5663->pdata.impedance_sensing_num;
3432 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3433 device_property_read_u32_array(dev,
3434 "realtek,impedance_sensing_table",
3435 (u32 *)rt5663->imp_table, table_size);
3436 }
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3437
3438 return 0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3439}
3440
3441static int rt5663_i2c_probe(struct i2c_client *i2c,
3442 const struct i2c_device_id *id)
3443{
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3444 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3445 struct rt5663_priv *rt5663;
3446 int ret;
3447 unsigned int val;
3448 struct regmap *regmap;
3449
3450 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3451 GFP_KERNEL);
3452
3453 if (rt5663 == NULL)
3454 return -ENOMEM;
3455
3456 i2c_set_clientdata(i2c, rt5663);
3457
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3458 if (pdata)
3459 rt5663->pdata = *pdata;
3460 else
3461 rt5663_parse_dp(rt5663, &i2c->dev);
3462
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3463 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3464 if (IS_ERR(regmap)) {
3465 ret = PTR_ERR(regmap);
3466 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3467 ret);
3468 return ret;
3469 }
Oder Chiouba68fa32017-11-09 19:28:10 +0800[diff] [blame]3470
3471 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3472 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3473 dev_err(&i2c->dev,
3474 "Device with ID register %#x is not rt5663, retry one time.\n",
3475 val);
3476 msleep(100);
3477 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3478 }
3479
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3480 switch (val) {
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3481 case RT5663_DEVICE_ID_2:
3482 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3483 rt5663->codec_ver = CODEC_VER_1;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3484 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3485 case RT5663_DEVICE_ID_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3486 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3487 rt5663->codec_ver = CODEC_VER_0;
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3488 break;
3489 default:
3490 dev_err(&i2c->dev,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3491 "Device with ID register %#x is not rt5663\n",
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3492 val);
3493 return -ENODEV;
3494 }
3495
3496 if (IS_ERR(rt5663->regmap)) {
3497 ret = PTR_ERR(rt5663->regmap);
3498 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3499 ret);
3500 return ret;
3501 }
3502
3503 /* reset and calibrate */
3504 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3505 regcache_cache_bypass(rt5663->regmap, true);
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3506 switch (rt5663->codec_ver) {
3507 case CODEC_VER_1:
3508 rt5663_v2_calibrate(rt5663);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3509 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3510 case CODEC_VER_0:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3511 rt5663_calibrate(rt5663);
3512 break;
3513 default:
3514 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3515 }
3516 regcache_cache_bypass(rt5663->regmap, false);
3517 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3518 dev_dbg(&i2c->dev, "calibrate done\n");
3519
oder_chiou@realtek.com450f0f62017-07-10 11:14:56 +0800[diff] [blame]3520 switch (rt5663->codec_ver) {
3521 case CODEC_VER_1:
3522 break;
3523 case CODEC_VER_0:
3524 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3525 ARRAY_SIZE(rt5663_patch_list));
3526 if (ret != 0)
3527 dev_warn(&i2c->dev,
3528 "Failed to apply regmap patch: %d\n", ret);
3529 break;
3530 default:
3531 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3532 }
3533
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3534 /* GPIO1 as IRQ */
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3535 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3536 RT5663_GP1_PIN_IRQ);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3537 /* 4btn inline command debounce */
3538 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3539 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3540
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3541 switch (rt5663->codec_ver) {
3542 case CODEC_VER_1:
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3543 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3544 /* JD1 */
3545 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3546 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3547 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3548 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3549 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3550 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3551 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3552
3553 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3554 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3555 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3556 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3557 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3558 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3559 /* Set GPIO4 and GPIO8 as input for combo jack */
3560 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3561 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3562 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3563 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3564 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3565 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3566 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3567 break;
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3568 case CODEC_VER_0:
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3569 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
Bard Liao734447232016-10-21 11:02:28 +0800[diff] [blame]3570 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3571 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
Oder Chiouaf2728e2017-06-06 14:59:54 +0800[diff] [blame]3572 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3573 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3574 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3575 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3576 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3577 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3578 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3579 msleep(20);
3580 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3581 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
Jack Yu7e7e76b2016-10-03 10:43:27 +0800[diff] [blame]3582 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3583 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3584 /* DACREF LDO control */
3585 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3586 0x3a0a);
3587 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3588 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3589 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3590 RT5663_DATA_SWAP_ADCDAT1_MASK,
3591 RT5663_DATA_SWAP_ADCDAT1_LL);
3592 break;
3593 default:
3594 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3595 }
3596
3597 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
oder_chiou@realtek.comde6ae8a2017-11-10 13:16:44 +0800[diff] [blame]3598 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3599
3600 if (i2c->irq) {
3601 ret = request_irq(i2c->irq, rt5663_irq,
3602 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3603 | IRQF_ONESHOT, "rt5663", rt5663);
3604 if (ret)
3605 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3606 __func__, ret);
3607 }
3608
3609 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3610 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3611
3612 if (ret) {
3613 if (i2c->irq)
3614 free_irq(i2c->irq, rt5663);
3615 }
3616
3617 return ret;
3618}
3619
3620static int rt5663_i2c_remove(struct i2c_client *i2c)
3621{
3622 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3623
3624 if (i2c->irq)
3625 free_irq(i2c->irq, rt5663);
3626
3627 snd_soc_unregister_codec(&i2c->dev);
3628
3629 return 0;
3630}
3631
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]3632static void rt5663_i2c_shutdown(struct i2c_client *client)
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3633{
3634 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3635
3636 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3637}
3638
Wei Yongjun66d7c262016-09-17 01:34:09 +0000[diff] [blame]3639static struct i2c_driver rt5663_i2c_driver = {
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3640 .driver = {
3641 .name = "rt5663",
Bard Liaodf7c5212016-09-09 10:33:10 +0800[diff] [blame]3642 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3643 .of_match_table = of_match_ptr(rt5663_of_match),
3644 },
3645 .probe = rt5663_i2c_probe,
3646 .remove = rt5663_i2c_remove,
3647 .shutdown = rt5663_i2c_shutdown,
3648 .id_table = rt5663_i2c_id,
3649};
3650module_i2c_driver(rt5663_i2c_driver);
3651
3652MODULE_DESCRIPTION("ASoC RT5663 driver");
3653MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3654MODULE_LICENSE("GPL v2");