blob: 871f21783866d5fdb1557ec56e5f13b602ba331a [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Suthikulpanit, Suraveeb6197b92015-06-10 11:08:53 -05003 select ACPI_CCA_REQUIRED if ACPI
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00004 select ACPI_GENERIC_GSI if ACPI
Al Stone6933de02015-03-24 14:02:51 +00005 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01006 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Kees Cook2b68f6c2015-04-14 15:48:00 -07007 select ARCH_HAS_ELF_RANDOMIZE
Riku Voipio957e3fa2014-12-12 16:57:44 -08008 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07009 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010010 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +010011 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +020012 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010013 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000014 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000015 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000016 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000017 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000018 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010019 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000020 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010021 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000022 select ARM_GIC_V3_ITS if PCI_MSI
Mark Rutlandbff60792015-07-31 15:46:16 +010023 select ARM_PSCI_FW
Will Deaconadace892013-05-08 17:29:24 +010024 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000025 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070026 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000027 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000028 select DCACHE_WORD_ACCESS
Catalin Marinasef375662015-07-07 17:15:39 +010029 select EDAC_SUPPORT
Yang Shi2f34f172015-11-09 10:09:55 -080030 select FRAME_POINTER
Laura Abbottd4932f92014-10-09 15:26:44 -070031 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010032 select GENERIC_CLOCKEVENTS
Will Deacon4b3dc962015-05-29 18:28:44 +010033 select GENERIC_CLOCKEVENTS_BROADCAST
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000034 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070035 select GENERIC_EARLY_IOREMAP
Leo Yan2314ee42015-08-21 04:40:22 +010036 select GENERIC_IDLE_POLL_SETUP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
Sudeep Holla6544e672015-04-22 18:16:33 +010039 select GENERIC_IRQ_SHOW_LEVEL
Arnd Bergmanncb61f672014-11-19 14:09:07 +010040 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070041 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010042 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000043 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010045 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010046 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010047 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010048 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010049 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010050 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080051 select HAVE_ARCH_JUMP_LABEL
Andrey Ryabininf1b90322015-11-17 18:47:08 +030052 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
Vijaya Kumar K95292472014-01-28 11:20:22 +000053 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000054 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010055 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070056 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010057 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010058 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010059 select HAVE_CMPXCHG_DOUBLE
Will Deacon95eff6b2015-05-29 14:57:47 +010060 select HAVE_CMPXCHG_LOCAL
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070061 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070062 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010063 select HAVE_DMA_API_DEBUG
64 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000065 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010066 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000067 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010068 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090069 select HAVE_FUNCTION_TRACER
70 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010071 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010073 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000074 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010075 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010076 select HAVE_PERF_REGS
77 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070078 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010079 select HAVE_SYSCALL_TRACEPOINTS
Robin Murphy876945d2015-10-01 20:14:00 +010080 select IOMMU_DMA if IOMMU_SUPPORT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010081 select IRQ_DOMAIN
Anders Roxelle8557d12015-04-27 22:53:09 +020082 select IRQ_FORCED_THREADING
Catalin Marinasfea2aca2012-10-16 11:26:57 +010083 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010084 select NO_BOOTMEM
85 select OF
86 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010087 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010088 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000089 select POWER_RESET
90 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010091 select RTC_LIB
92 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070093 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070094 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010095 help
96 ARM 64-bit (AArch64) Linux support.
97
98config 64BIT
99 def_bool y
100
101config ARCH_PHYS_ADDR_T_64BIT
102 def_bool y
103
104config MMU
105 def_bool y
106
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -0700107config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100108 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100109
110config STACKTRACE_SUPPORT
111 def_bool y
112
Jeff Vander Stoepbf0c4e02015-08-18 20:50:10 +0100113config ILLEGAL_POINTER_VALUE
114 hex
115 default 0xdead000000000000
116
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100117config LOCKDEP_SUPPORT
118 def_bool y
119
120config TRACE_IRQFLAGS_SUPPORT
121 def_bool y
122
Will Deaconc209f792014-03-14 17:47:05 +0000123config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100124 def_bool y
125
Dave P Martin9fb74102015-07-24 16:37:48 +0100126config GENERIC_BUG
127 def_bool y
128 depends on BUG
129
130config GENERIC_BUG_RELATIVE_POINTERS
131 def_bool y
132 depends on GENERIC_BUG
133
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100134config GENERIC_HWEIGHT
135 def_bool y
136
137config GENERIC_CSUM
138 def_bool y
139
140config GENERIC_CALIBRATE_DELAY
141 def_bool y
142
Catalin Marinas19e76402014-02-27 12:09:22 +0000143config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100144 def_bool y
145
Steve Capper29e56942014-10-09 15:29:25 -0700146config HAVE_GENERIC_RCU_GUP
147 def_bool y
148
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100149config ARCH_DMA_ADDR_T_64BIT
150 def_bool y
151
152config NEED_DMA_MAP_STATE
153 def_bool y
154
155config NEED_SG_DMA_LENGTH
156 def_bool y
157
Will Deacon4b3dc962015-05-29 18:28:44 +0100158config SMP
159 def_bool y
160
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100161config SWIOTLB
162 def_bool y
163
164config IOMMU_HELPER
165 def_bool SWIOTLB
166
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100167config KERNEL_MODE_NEON
168 def_bool y
169
Rob Herring92cc15f2014-04-18 17:19:59 -0500170config FIX_EARLYCON_MEM
171 def_bool y
172
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700173config PGTABLE_LEVELS
174 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100175 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700176 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
177 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
178 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100179 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
180 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700181
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100182source "init/Kconfig"
183
184source "kernel/Kconfig.freezer"
185
Olof Johansson6a377492015-07-20 12:09:16 -0700186source "arch/arm64/Kconfig.platforms"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100187
188menu "Bus support"
189
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100190config PCI
191 bool "PCI support"
192 help
193 This feature enables support for PCI bus system. If you say Y
194 here, the kernel will include drivers and infrastructure code
195 to support PCI bus devices.
196
197config PCI_DOMAINS
198 def_bool PCI
199
200config PCI_DOMAINS_GENERIC
201 def_bool PCI
202
203config PCI_SYSCALL
204 def_bool PCI
205
206source "drivers/pci/Kconfig"
207source "drivers/pci/pcie/Kconfig"
208source "drivers/pci/hotplug/Kconfig"
209
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100210endmenu
211
212menu "Kernel Features"
213
Andre Przywarac0a01b82014-11-14 15:54:12 +0000214menu "ARM errata workarounds via the alternatives framework"
215
216config ARM64_ERRATUM_826319
217 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
218 default y
219 help
220 This option adds an alternative code sequence to work around ARM
221 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
222 AXI master interface and an L2 cache.
223
224 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
225 and is unable to accept a certain write via this interface, it will
226 not progress on read data presented on the read data channel and the
227 system can deadlock.
228
229 The workaround promotes data cache clean instructions to
230 data cache clean-and-invalidate.
231 Please note that this does not necessarily enable the workaround,
232 as it depends on the alternative framework, which will only patch
233 the kernel if an affected CPU is detected.
234
235 If unsure, say Y.
236
237config ARM64_ERRATUM_827319
238 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
239 default y
240 help
241 This option adds an alternative code sequence to work around ARM
242 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
243 master interface and an L2 cache.
244
245 Under certain conditions this erratum can cause a clean line eviction
246 to occur at the same time as another transaction to the same address
247 on the AMBA 5 CHI interface, which can cause data corruption if the
248 interconnect reorders the two transactions.
249
250 The workaround promotes data cache clean instructions to
251 data cache clean-and-invalidate.
252 Please note that this does not necessarily enable the workaround,
253 as it depends on the alternative framework, which will only patch
254 the kernel if an affected CPU is detected.
255
256 If unsure, say Y.
257
258config ARM64_ERRATUM_824069
259 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
260 default y
261 help
262 This option adds an alternative code sequence to work around ARM
263 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
264 to a coherent interconnect.
265
266 If a Cortex-A53 processor is executing a store or prefetch for
267 write instruction at the same time as a processor in another
268 cluster is executing a cache maintenance operation to the same
269 address, then this erratum might cause a clean cache line to be
270 incorrectly marked as dirty.
271
272 The workaround promotes data cache clean instructions to
273 data cache clean-and-invalidate.
274 Please note that this option does not necessarily enable the
275 workaround, as it depends on the alternative framework, which will
276 only patch the kernel if an affected CPU is detected.
277
278 If unsure, say Y.
279
280config ARM64_ERRATUM_819472
281 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
282 default y
283 help
284 This option adds an alternative code sequence to work around ARM
285 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
286 present when it is connected to a coherent interconnect.
287
288 If the processor is executing a load and store exclusive sequence at
289 the same time as a processor in another cluster is executing a cache
290 maintenance operation to the same address, then this erratum might
291 cause data corruption.
292
293 The workaround promotes data cache clean instructions to
294 data cache clean-and-invalidate.
295 Please note that this does not necessarily enable the workaround,
296 as it depends on the alternative framework, which will only patch
297 the kernel if an affected CPU is detected.
298
299 If unsure, say Y.
300
301config ARM64_ERRATUM_832075
302 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
303 default y
304 help
305 This option adds an alternative code sequence to work around ARM
306 erratum 832075 on Cortex-A57 parts up to r1p2.
307
308 Affected Cortex-A57 parts might deadlock when exclusive load/store
309 instructions to Write-Back memory are mixed with Device loads.
310
311 The workaround is to promote device loads to use Load-Acquire
312 semantics.
313 Please note that this does not necessarily enable the workaround,
314 as it depends on the alternative framework, which will only patch
315 the kernel if an affected CPU is detected.
316
317 If unsure, say Y.
318
Marc Zyngier498cd5c2015-11-16 10:28:18 +0000319config ARM64_ERRATUM_834220
320 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
321 depends on KVM
322 default y
323 help
324 This option adds an alternative code sequence to work around ARM
325 erratum 834220 on Cortex-A57 parts up to r1p2.
326
327 Affected Cortex-A57 parts might report a Stage 2 translation
328 fault as the result of a Stage 1 fault for load crossing a
329 page boundary when there is a permission or device memory
330 alignment fault at Stage 1 and a translation fault at Stage 2.
331
332 The workaround is to verify that the Stage 1 translation
333 doesn't generate a fault before handling the Stage 2 fault.
334 Please note that this does not necessarily enable the workaround,
335 as it depends on the alternative framework, which will only patch
336 the kernel if an affected CPU is detected.
337
338 If unsure, say Y.
339
Will Deacon905e8c52015-03-23 19:07:02 +0000340config ARM64_ERRATUM_845719
341 bool "Cortex-A53: 845719: a load might read incorrect data"
342 depends on COMPAT
343 default y
344 help
345 This option adds an alternative code sequence to work around ARM
346 erratum 845719 on Cortex-A53 parts up to r0p4.
347
348 When running a compat (AArch32) userspace on an affected Cortex-A53
349 part, a load at EL0 from a virtual address that matches the bottom 32
350 bits of the virtual address used by a recent load at (AArch64) EL1
351 might return incorrect data.
352
353 The workaround is to write the contextidr_el1 register on exception
354 return to a 32-bit task.
355 Please note that this does not necessarily enable the workaround,
356 as it depends on the alternative framework, which will only patch
357 the kernel if an affected CPU is detected.
358
359 If unsure, say Y.
360
Will Deacondf057cc2015-03-17 12:15:02 +0000361config ARM64_ERRATUM_843419
362 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
363 depends on MODULES
364 default y
365 help
366 This option builds kernel modules using the large memory model in
367 order to avoid the use of the ADRP instruction, which can cause
368 a subsequent memory access to use an incorrect address on Cortex-A53
369 parts up to r0p4.
370
371 Note that the kernel itself must be linked with a version of ld
372 which fixes potentially affected ADRP instructions through the
373 use of veneers.
374
375 If unsure, say Y.
376
Robert Richter94100972015-09-21 22:58:38 +0200377config CAVIUM_ERRATUM_22375
378 bool "Cavium erratum 22375, 24313"
379 default y
380 help
381 Enable workaround for erratum 22375, 24313.
382
383 This implements two gicv3-its errata workarounds for ThunderX. Both
384 with small impact affecting only ITS table allocation.
385
386 erratum 22375: only alloc 8MB table size
387 erratum 24313: ignore memory access type
388
389 The fixes are in ITS initialization and basically ignore memory access
390 type and table size provided by the TYPER and BASER registers.
391
392 If unsure, say Y.
393
Robert Richter6d4e11c2015-09-21 22:58:35 +0200394config CAVIUM_ERRATUM_23154
395 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
396 default y
397 help
398 The gicv3 of ThunderX requires a modified version for
399 reading the IAR status to ensure data synchronization
400 (access to icc_iar1_el1 is not sync'ed before and after).
401
402 If unsure, say Y.
403
Andre Przywarac0a01b82014-11-14 15:54:12 +0000404endmenu
405
406
Jungseok Leee41ceed2014-05-12 10:40:38 +0100407choice
408 prompt "Page size"
409 default ARM64_4K_PAGES
410 help
411 Page size (translation granule) configuration.
412
413config ARM64_4K_PAGES
414 bool "4KB"
415 help
416 This feature enables 4KB pages support.
417
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100418config ARM64_16K_PAGES
419 bool "16KB"
420 help
421 The system will use 16KB pages support. AArch32 emulation
422 requires applications compiled with 16K (or a multiple of 16K)
423 aligned segments.
424
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100425config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100426 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100427 help
428 This feature enables 64KB pages support (4KB by default)
429 allowing only two levels of page tables and faster TLB
Suzuki K. Poulosedb488be2015-10-19 14:19:34 +0100430 look-up. AArch32 emulation requires applications compiled
431 with 64K aligned segments.
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100432
Jungseok Leee41ceed2014-05-12 10:40:38 +0100433endchoice
434
435choice
436 prompt "Virtual address space size"
437 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100438 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100439 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
440 help
441 Allows choosing one of multiple possible virtual address
442 space sizes. The level of translation table is determined by
443 a combination of page size and virtual address space size.
444
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100445config ARM64_VA_BITS_36
Catalin Marinas56a3f302015-10-20 14:59:20 +0100446 bool "36-bit" if EXPERT
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100447 depends on ARM64_16K_PAGES
448
Jungseok Leee41ceed2014-05-12 10:40:38 +0100449config ARM64_VA_BITS_39
450 bool "39-bit"
451 depends on ARM64_4K_PAGES
452
453config ARM64_VA_BITS_42
454 bool "42-bit"
455 depends on ARM64_64K_PAGES
456
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100457config ARM64_VA_BITS_47
458 bool "47-bit"
459 depends on ARM64_16K_PAGES
460
Jungseok Leec79b9542014-05-12 18:40:51 +0900461config ARM64_VA_BITS_48
462 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900463
Jungseok Leee41ceed2014-05-12 10:40:38 +0100464endchoice
465
466config ARM64_VA_BITS
467 int
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100468 default 36 if ARM64_VA_BITS_36
Jungseok Leee41ceed2014-05-12 10:40:38 +0100469 default 39 if ARM64_VA_BITS_39
470 default 42 if ARM64_VA_BITS_42
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100471 default 47 if ARM64_VA_BITS_47
Jungseok Leec79b9542014-05-12 18:40:51 +0900472 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100473
Will Deacona8720132013-10-11 14:52:19 +0100474config CPU_BIG_ENDIAN
475 bool "Build big-endian kernel"
476 help
477 Say Y if you plan on running a kernel in big-endian mode.
478
Mark Brownf6e763b2014-03-04 07:51:17 +0000479config SCHED_MC
480 bool "Multi-core scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000481 help
482 Multi-core scheduler support improves the CPU scheduler's decision
483 making when dealing with multi-core CPU chips at a cost of slightly
484 increased overhead in some places. If unsure say N here.
485
486config SCHED_SMT
487 bool "SMT scheduler support"
Mark Brownf6e763b2014-03-04 07:51:17 +0000488 help
489 Improves the CPU scheduler's decision making when dealing with
490 MultiThreading at a cost of slightly increased overhead in some
491 places. If unsure say N here.
492
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100493config NR_CPUS
Ganapatrao Kulkarni62aa9652015-03-18 11:01:18 +0000494 int "Maximum number of CPUs (2-4096)"
495 range 2 4096
Vinayak Kale15942852013-04-24 10:06:57 +0100496 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100497 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100498
Mark Rutland9327e2c2013-10-24 20:30:18 +0100499config HOTPLUG_CPU
500 bool "Support for hot-pluggable CPUs"
Yang Yingliang217d4532015-09-24 17:32:14 +0800501 select GENERIC_IRQ_MIGRATION
Mark Rutland9327e2c2013-10-24 20:30:18 +0100502 help
503 Say Y here to experiment with turning CPUs off and on. CPUs
504 can be controlled through /sys/devices/system/cpu.
505
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100506source kernel/Kconfig.preempt
Kefeng Wangf90df5e2015-10-26 11:48:16 +0800507source kernel/Kconfig.hz
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100508
509config ARCH_HAS_HOLES_MEMORYMODEL
510 def_bool y if SPARSEMEM
511
512config ARCH_SPARSEMEM_ENABLE
513 def_bool y
514 select SPARSEMEM_VMEMMAP_ENABLE
515
516config ARCH_SPARSEMEM_DEFAULT
517 def_bool ARCH_SPARSEMEM_ENABLE
518
519config ARCH_SELECT_MEMORY_MODEL
520 def_bool ARCH_SPARSEMEM_ENABLE
521
522config HAVE_ARCH_PFN_VALID
523 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
524
525config HW_PERF_EVENTS
Mark Rutland6475b2d2015-10-02 10:55:03 +0100526 def_bool y
527 depends on ARM_PMU
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100528
Steve Capper084bd292013-04-10 13:48:00 +0100529config SYS_SUPPORTS_HUGETLBFS
530 def_bool y
531
532config ARCH_WANT_GENERAL_HUGETLB
533 def_bool y
534
535config ARCH_WANT_HUGE_PMD_SHARE
Suzuki K. Poulose21539932015-10-19 14:19:38 +0100536 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
Steve Capper084bd292013-04-10 13:48:00 +0100537
Steve Capperaf074842013-04-19 16:23:57 +0100538config HAVE_ARCH_TRANSPARENT_HUGEPAGE
539 def_bool y
540
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100541config ARCH_HAS_CACHE_LINE_SIZE
542 def_bool y
543
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100544source "mm/Kconfig"
545
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000546config SECCOMP
547 bool "Enable seccomp to safely compute untrusted bytecode"
548 ---help---
549 This kernel feature is useful for number crunching applications
550 that may need to compute untrusted bytecode during their
551 execution. By using pipes or other transports made available to
552 the process as file descriptors supporting the read/write
553 syscalls, it's possible to isolate those applications in
554 their own address space using seccomp. Once seccomp is
555 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
556 and the task is only allowed to execute a few safe syscalls
557 defined by each seccomp mode.
558
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000559config XEN_DOM0
560 def_bool y
561 depends on XEN
562
563config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700564 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000565 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000566 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000567 help
568 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
569
Steve Capperd03bb142013-04-25 15:19:21 +0100570config FORCE_MAX_ZONEORDER
571 int
572 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100573 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
Steve Capperd03bb142013-04-25 15:19:21 +0100574 default "11"
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100575 help
576 The kernel memory allocator divides physically contiguous memory
577 blocks into "zones", where each zone is a power of two number of
578 pages. This option selects the largest power of two that the kernel
579 keeps in the memory allocator. If you need to allocate very large
580 blocks of physically contiguous memory, then you may need to
581 increase this value.
582
583 This config option is actually maximum order plus one. For example,
584 a value of 11 means that the largest free memory block is 2^10 pages.
585
586 We make sure that we can allocate upto a HugePage size for each configuration.
587 Hence we have :
588 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
589
590 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
591 4M allocations matching the default size used by generic code.
Steve Capperd03bb142013-04-25 15:19:21 +0100592
Will Deacon1b907f42014-11-20 16:51:10 +0000593menuconfig ARMV8_DEPRECATED
594 bool "Emulate deprecated/obsolete ARMv8 instructions"
595 depends on COMPAT
596 help
597 Legacy software support may require certain instructions
598 that have been deprecated or obsoleted in the architecture.
599
600 Enable this config to enable selective emulation of these
601 features.
602
603 If unsure, say Y
604
605if ARMV8_DEPRECATED
606
607config SWP_EMULATION
608 bool "Emulate SWP/SWPB instructions"
609 help
610 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
611 they are always undefined. Say Y here to enable software
612 emulation of these instructions for userspace using LDXR/STXR.
613
614 In some older versions of glibc [<=2.8] SWP is used during futex
615 trylock() operations with the assumption that the code will not
616 be preempted. This invalid assumption may be more likely to fail
617 with SWP emulation enabled, leading to deadlock of the user
618 application.
619
620 NOTE: when accessing uncached shared regions, LDXR/STXR rely
621 on an external transaction monitoring block called a global
622 monitor to maintain update atomicity. If your system does not
623 implement a global monitor, this option can cause programs that
624 perform SWP operations to uncached memory to deadlock.
625
626 If unsure, say Y
627
628config CP15_BARRIER_EMULATION
629 bool "Emulate CP15 Barrier instructions"
630 help
631 The CP15 barrier instructions - CP15ISB, CP15DSB, and
632 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
633 strongly recommended to use the ISB, DSB, and DMB
634 instructions instead.
635
636 Say Y here to enable software emulation of these
637 instructions for AArch32 userspace code. When this option is
638 enabled, CP15 barrier usage is traced which can help
639 identify software that needs updating.
640
641 If unsure, say Y
642
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000643config SETEND_EMULATION
644 bool "Emulate SETEND instruction"
645 help
646 The SETEND instruction alters the data-endianness of the
647 AArch32 EL0, and is deprecated in ARMv8.
648
649 Say Y here to enable software emulation of the instruction
650 for AArch32 userspace code.
651
652 Note: All the cpus on the system must have mixed endian support at EL0
653 for this feature to be enabled. If a new CPU - which doesn't support mixed
654 endian - is hotplugged in after this feature has been enabled, there could
655 be unexpected results in the applications.
656
657 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000658endif
659
Will Deacon0e4a0702015-07-27 15:54:13 +0100660menu "ARMv8.1 architectural features"
661
662config ARM64_HW_AFDBM
663 bool "Support for hardware updates of the Access and Dirty page flags"
664 default y
665 help
666 The ARMv8.1 architecture extensions introduce support for
667 hardware updates of the access and dirty information in page
668 table entries. When enabled in TCR_EL1 (HA and HD bits) on
669 capable processors, accesses to pages with PTE_AF cleared will
670 set this bit instead of raising an access flag fault.
671 Similarly, writes to read-only pages with the DBM bit set will
672 clear the read-only bit (AP[2]) instead of raising a
673 permission fault.
674
675 Kernels built with this configuration option enabled continue
676 to work on pre-ARMv8.1 hardware and the performance impact is
677 minimal. If unsure, say Y.
678
679config ARM64_PAN
680 bool "Enable support for Privileged Access Never (PAN)"
681 default y
682 help
683 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
684 prevents the kernel or hypervisor from accessing user-space (EL0)
685 memory directly.
686
687 Choosing this option will cause any unprotected (not using
688 copy_to_user et al) memory access to fail with a permission fault.
689
690 The feature is detected at runtime, and will remain as a 'nop'
691 instruction if the cpu does not implement the feature.
692
693config ARM64_LSE_ATOMICS
694 bool "Atomic instructions"
695 help
696 As part of the Large System Extensions, ARMv8.1 introduces new
697 atomic instructions that are designed specifically to scale in
698 very large systems.
699
700 Say Y here to make use of these instructions for the in-kernel
701 atomic routines. This incurs a small overhead on CPUs that do
702 not support these instructions and requires the kernel to be
703 built with binutils >= 2.25.
704
705endmenu
706
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100707endmenu
708
709menu "Boot options"
710
711config CMDLINE
712 string "Default kernel command string"
713 default ""
714 help
715 Provide a set of default command-line options at build time by
716 entering them here. As a minimum, you should specify the the
717 root device (e.g. root=/dev/nfs).
718
719config CMDLINE_FORCE
720 bool "Always use the default kernel command string"
721 help
722 Always use the default kernel command string, even if the boot
723 loader passes other arguments to the kernel.
724 This is useful if you cannot or don't want to change the
725 command-line options your boot loader passes to the kernel.
726
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200727config EFI_STUB
728 bool
729
Mark Salterf84d0272014-04-15 21:59:30 -0400730config EFI
731 bool "UEFI runtime support"
732 depends on OF && !CPU_BIG_ENDIAN
733 select LIBFDT
734 select UCS2_STRING
735 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200736 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200737 select EFI_STUB
738 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400739 default y
740 help
741 This option provides support for runtime services provided
742 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400743 clock, and platform reset). A UEFI stub is also provided to
744 allow the kernel to be booted as an EFI application. This
745 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400746
Yi Lid1ae8c02014-10-04 23:46:43 +0800747config DMI
748 bool "Enable support for SMBIOS (DMI) tables"
749 depends on EFI
750 default y
751 help
752 This enables SMBIOS/DMI feature for systems.
753
754 This option is only useful on systems that have UEFI firmware.
755 However, even with this option, the resultant kernel should
756 continue to boot on existing non-UEFI platforms.
757
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100758endmenu
759
760menu "Userspace binary formats"
761
762source "fs/Kconfig.binfmt"
763
764config COMPAT
765 bool "Kernel support for 32-bit EL0"
Suzuki K. Poulose755e70b2015-10-19 14:19:32 +0100766 depends on ARM64_4K_PAGES || EXPERT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100767 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700768 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500769 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500770 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100771 help
772 This option enables support for a 32-bit EL0 running under a 64-bit
773 kernel at EL1. AArch32-specific components such as system calls,
774 the user helper functions, VFP support and the ptrace interface are
775 handled appropriately by the kernel.
776
Suzuki K. Poulose44eaacf2015-10-19 14:19:37 +0100777 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
778 that you will only be able to execute AArch32 binaries that were compiled
779 with page size aligned segments.
Alexander Grafa8fcd8b2015-03-16 16:32:23 +0000780
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100781 If you want to execute 32-bit userspace applications, say Y.
782
783config SYSVIPC_COMPAT
784 def_bool y
785 depends on COMPAT && SYSVIPC
786
787endmenu
788
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000789menu "Power management options"
790
791source "kernel/power/Kconfig"
792
793config ARCH_SUSPEND_POSSIBLE
794 def_bool y
795
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000796endmenu
797
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100798menu "CPU Power Management"
799
800source "drivers/cpuidle/Kconfig"
801
Rob Herring52e7e812014-02-24 11:27:57 +0900802source "drivers/cpufreq/Kconfig"
803
804endmenu
805
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100806source "net/Kconfig"
807
808source "drivers/Kconfig"
809
Mark Salterf84d0272014-04-15 21:59:30 -0400810source "drivers/firmware/Kconfig"
811
Graeme Gregoryb6a02172015-03-24 14:02:53 +0000812source "drivers/acpi/Kconfig"
813
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100814source "fs/Kconfig"
815
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100816source "arch/arm64/kvm/Kconfig"
817
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100818source "arch/arm64/Kconfig.debug"
819
820source "security/Kconfig"
821
822source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800823if CRYPTO
824source "arch/arm64/crypto/Kconfig"
825endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100826
827source "lib/Kconfig"