Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | * |
| 3 | * (c) 1999 by Computone Corporation |
| 4 | * |
| 5 | ******************************************************************************** |
| 6 | * |
| 7 | * |
| 8 | * PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport |
| 9 | * serial I/O controllers. |
| 10 | * |
| 11 | * DESCRIPTION: Mainline code for the device driver |
| 12 | * |
| 13 | *******************************************************************************/ |
| 14 | //------------------------------------------------------------------------------ |
| 15 | // i2ellis.h |
| 16 | // |
| 17 | // IntelliPort-II and IntelliPort-IIEX |
| 18 | // |
| 19 | // Extremely |
| 20 | // Low |
| 21 | // Level |
| 22 | // Interface |
| 23 | // Services |
| 24 | // |
| 25 | // Structure Definitions and declarations for "ELLIS" service routines found in |
| 26 | // i2ellis.c |
| 27 | // |
| 28 | // These routines are based on properties of the IntelliPort-II and -IIEX |
| 29 | // hardware and bootstrap firmware, and are not sensitive to particular |
| 30 | // conventions of any particular loadware. |
| 31 | // |
| 32 | // Unlike i2hw.h, which provides IRONCLAD hardware definitions, the material |
| 33 | // here and in i2ellis.c is intended to provice a useful, but not required, |
| 34 | // layer of insulation from the hardware specifics. |
| 35 | //------------------------------------------------------------------------------ |
| 36 | #ifndef I2ELLIS_H /* To prevent multiple includes */ |
| 37 | #define I2ELLIS_H 1 |
| 38 | //------------------------------------------------ |
| 39 | // Revision History: |
| 40 | // |
| 41 | // 30 September 1991 MAG First Draft Started |
| 42 | // 12 October 1991 ...continued... |
| 43 | // |
| 44 | // 20 December 1996 AKM Linux version |
| 45 | //------------------------------------------------- |
| 46 | |
| 47 | //---------------------- |
| 48 | // Mandatory Includes: |
| 49 | //---------------------- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | #include "ip2types.h" |
| 51 | #include "i2hw.h" // The hardware definitions |
| 52 | |
| 53 | //------------------------------------------ |
| 54 | // STAT_BOXIDS packets |
| 55 | //------------------------------------------ |
| 56 | #define MAX_BOX 4 |
| 57 | |
| 58 | typedef struct _bidStat |
| 59 | { |
| 60 | unsigned char bid_value[MAX_BOX]; |
| 61 | } bidStat, *bidStatPtr; |
| 62 | |
| 63 | // This packet is sent in response to a CMD_GET_BOXIDS bypass command. For -IIEX |
| 64 | // boards, reports the hardware-specific "asynchronous resource register" on |
| 65 | // each expansion box. Boxes not present report 0xff. For -II boards, the first |
| 66 | // element contains 0x80 for 8-port, 0x40 for 4-port boards. |
| 67 | |
| 68 | // Box IDs aka ARR or Async Resource Register (more than you want to know) |
| 69 | // 7 6 5 4 3 2 1 0 |
| 70 | // F F N N L S S S |
| 71 | // ============================= |
| 72 | // F F - Product Family Designator |
| 73 | // =====+++++++++++++++++++++++++++++++ |
| 74 | // 0 0 - Intelliport II EX / ISA-8 |
| 75 | // 1 0 - IntelliServer |
| 76 | // 0 1 - SAC - Port Device (Intelliport III ??? ) |
| 77 | // =====+++++++++++++++++++++++++++++++++++++++ |
| 78 | // N N - Number of Ports |
| 79 | // 0 0 - 8 (eight) |
| 80 | // 0 1 - 4 (four) |
| 81 | // 1 0 - 12 (twelve) |
| 82 | // 1 1 - 16 (sixteen) |
| 83 | // =++++++++++++++++++++++++++++++++++ |
| 84 | // L - LCD Display Module Present |
| 85 | // 0 - No |
| 86 | // 1 - LCD module present |
| 87 | // =========+++++++++++++++++++++++++++++++++++++ |
| 88 | // S S S - Async Signals Supported Designator |
| 89 | // 0 0 0 - 8dss, Mod DCE DB25 Female |
| 90 | // 0 0 1 - 6dss, RJ-45 |
| 91 | // 0 1 0 - RS-232/422 dss, DB25 Female |
| 92 | // 0 1 1 - RS-232/422 dss, separate 232/422 DB25 Female |
| 93 | // 1 0 0 - 6dss, 921.6 I/F with ST654's |
| 94 | // 1 0 1 - RS-423/232 8dss, RJ-45 10Pin |
| 95 | // 1 1 0 - 6dss, Mod DCE DB25 Female |
| 96 | // 1 1 1 - NO BOX PRESENT |
| 97 | |
| 98 | #define FF(c) ((c & 0xC0) >> 6) |
| 99 | #define NN(c) ((c & 0x30) >> 4) |
| 100 | #define L(c) ((c & 0x08) >> 3) |
| 101 | #define SSS(c) (c & 0x07) |
| 102 | |
| 103 | #define BID_HAS_654(x) (SSS(x) == 0x04) |
| 104 | #define BID_NO_BOX 0xff /* no box */ |
| 105 | #define BID_8PORT 0x80 /* IP2-8 port */ |
| 106 | #define BID_4PORT 0x81 /* IP2-4 port */ |
| 107 | #define BID_EXP_MASK 0x30 /* IP2-EX */ |
| 108 | #define BID_EXP_8PORT 0x00 /* 8, */ |
| 109 | #define BID_EXP_4PORT 0x10 /* 4, */ |
| 110 | #define BID_EXP_UNDEF 0x20 /* UNDEF, */ |
| 111 | #define BID_EXP_16PORT 0x30 /* 16, */ |
| 112 | #define BID_LCD_CTRL 0x08 /* LCD Controller */ |
| 113 | #define BID_LCD_NONE 0x00 /* - no controller present */ |
| 114 | #define BID_LCD_PRES 0x08 /* - controller present */ |
| 115 | #define BID_CON_MASK 0x07 /* - connector pinouts */ |
| 116 | #define BID_CON_DB25 0x00 /* - DB-25 F */ |
| 117 | #define BID_CON_RJ45 0x01 /* - rj45 */ |
| 118 | |
| 119 | //------------------------------------------------------------------------------ |
| 120 | // i2eBordStr |
| 121 | // |
| 122 | // This structure contains all the information the ELLIS routines require in |
| 123 | // dealing with a particular board. |
| 124 | //------------------------------------------------------------------------------ |
| 125 | // There are some queues here which are guaranteed to never contain the entry |
| 126 | // for a single channel twice. So they must be slightly larger to allow |
| 127 | // unambiguous full/empty management |
| 128 | // |
| 129 | #define CH_QUEUE_SIZE ABS_MOST_PORTS+2 |
| 130 | |
| 131 | typedef struct _i2eBordStr |
| 132 | { |
| 133 | porStr i2ePom; // Structure containing the power-on message. |
| 134 | |
| 135 | unsigned short i2ePomSize; |
| 136 | // The number of bytes actually read if |
| 137 | // different from sizeof i2ePom, indicates |
| 138 | // there is an error! |
| 139 | |
| 140 | unsigned short i2eStartMail; |
| 141 | // Contains whatever inbound mailbox data |
| 142 | // present at startup. NO_MAIL_HERE indicates |
| 143 | // nothing was present. No special |
| 144 | // significance as of this writing, but may be |
| 145 | // useful for diagnostic reasons. |
| 146 | |
| 147 | unsigned short i2eValid; |
| 148 | // Indicates validity of the structure; if |
| 149 | // i2eValid == I2E_MAGIC, then we can trust |
| 150 | // the other fields. Some (especially |
| 151 | // initialization) functions are good about |
| 152 | // checking for validity. Many functions do |
| 153 | // not, it being assumed that the larger |
| 154 | // context assures we are using a valid |
| 155 | // i2eBordStrPtr. |
| 156 | |
| 157 | unsigned short i2eError; |
| 158 | // Used for returning an error condition from |
| 159 | // several functions which use i2eBordStrPtr |
| 160 | // as an argument. |
| 161 | |
| 162 | // Accelerators to characterize separate features of a board, derived from a |
| 163 | // number of sources. |
| 164 | |
| 165 | unsigned short i2eFifoSize; |
| 166 | // Always, the size of the FIFO. For |
| 167 | // IntelliPort-II, always the same, for -IIEX |
| 168 | // taken from the Power-On reset message. |
| 169 | |
| 170 | volatile |
| 171 | unsigned short i2eFifoRemains; |
| 172 | // Used during normal operation to indicate a |
| 173 | // lower bound on the amount of data which |
| 174 | // might be in the outbound fifo. |
| 175 | |
| 176 | unsigned char i2eFifoStyle; |
| 177 | // Accelerator which tells which style (-II or |
| 178 | // -IIEX) FIFO we are using. |
| 179 | |
| 180 | unsigned char i2eDataWidth16; |
| 181 | // Accelerator which tells whether we should |
| 182 | // do 8 or 16-bit data transfers. |
| 183 | |
| 184 | unsigned char i2eMaxIrq; |
| 185 | // The highest allowable IRQ, based on the |
| 186 | // slot size. |
| 187 | |
| 188 | unsigned char i2eChangeIrq; |
| 189 | // Whether tis valid to change IRQ's |
| 190 | // ISA = ok, EISA, MicroChannel, no |
| 191 | |
| 192 | // Accelerators for various addresses on the board |
| 193 | int i2eBase; // I/O Address of the Board |
| 194 | int i2eData; // From here data transfers happen |
| 195 | int i2eStatus; // From here status reads happen |
| 196 | int i2ePointer; // (IntelliPort-II: pointer/commands) |
| 197 | int i2eXMail; // (IntelliPOrt-IIEX: mailboxes |
| 198 | int i2eXMask; // (IntelliPort-IIEX: mask write |
| 199 | |
| 200 | //------------------------------------------------------- |
| 201 | // Information presented in a common format across boards |
| 202 | // For each box, bit map of the channels present. Box closest to |
| 203 | // the host is box 0. LSB is channel 0. IntelliPort-II (non-expandable) |
| 204 | // is taken to be box 0. These are derived from product i.d. registers. |
| 205 | |
| 206 | unsigned short i2eChannelMap[ABS_MAX_BOXES]; |
| 207 | |
| 208 | // Same as above, except each is derived from firmware attempting to detect |
| 209 | // the uart presence (by reading a valid GFRCR register). If bits are set in |
| 210 | // i2eChannelMap and not in i2eGoodMap, there is a potential problem. |
| 211 | |
| 212 | unsigned short i2eGoodMap[ABS_MAX_BOXES]; |
| 213 | |
| 214 | // --------------------------- |
| 215 | // For indirect function calls |
| 216 | |
| 217 | // Routine to cause an N-millisecond delay: Patched by the ii2Initialize |
| 218 | // function. |
| 219 | |
| 220 | void (*i2eDelay)(unsigned int); |
| 221 | |
| 222 | // Routine to write N bytes to the board through the FIFO. Returns true if |
| 223 | // all copacetic, otherwise returns false and error is in i2eError field. |
| 224 | // IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER. |
| 225 | |
| 226 | int (*i2eWriteBuf)(struct _i2eBordStr *, unsigned char *, int); |
| 227 | |
| 228 | // Routine to read N bytes from the board through the FIFO. Returns true if |
| 229 | // copacetic, otherwise returns false and error in i2eError. |
| 230 | // IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER. |
| 231 | |
| 232 | int (*i2eReadBuf)(struct _i2eBordStr *, unsigned char *, int); |
| 233 | |
| 234 | // Returns a word from FIFO. Will use 2 byte operations if needed. |
| 235 | |
| 236 | unsigned short (*i2eReadWord)(struct _i2eBordStr *); |
| 237 | |
| 238 | // Writes a word to FIFO. Will use 2 byte operations if needed. |
| 239 | |
| 240 | void (*i2eWriteWord)(struct _i2eBordStr *, unsigned short); |
| 241 | |
| 242 | // Waits specified time for the Transmit FIFO to go empty. Returns true if |
| 243 | // ok, otherwise returns false and error in i2eError. |
| 244 | |
| 245 | int (*i2eWaitForTxEmpty)(struct _i2eBordStr *, int); |
| 246 | |
| 247 | // Returns true or false according to whether the outgoing mailbox is empty. |
| 248 | |
| 249 | int (*i2eTxMailEmpty)(struct _i2eBordStr *); |
| 250 | |
| 251 | // Checks whether outgoing mailbox is empty. If so, sends mail and returns |
| 252 | // true. Otherwise returns false. |
| 253 | |
| 254 | int (*i2eTrySendMail)(struct _i2eBordStr *, unsigned char); |
| 255 | |
| 256 | // If no mail available, returns NO_MAIL_HERE, else returns the value in the |
| 257 | // mailbox (guaranteed can't be NO_MAIL_HERE). |
| 258 | |
| 259 | unsigned short (*i2eGetMail)(struct _i2eBordStr *); |
| 260 | |
| 261 | // Enables the board to interrupt the host when it writes to the mailbox. |
| 262 | // Irqs will not occur, however, until the loadware separately enables |
| 263 | // interrupt generation to the host. The standard loadware does this in |
| 264 | // response to a command packet sent by the host. (Also, disables |
| 265 | // any other potential interrupt sources from the board -- other than the |
| 266 | // inbound mailbox). |
| 267 | |
| 268 | void (*i2eEnableMailIrq)(struct _i2eBordStr *); |
| 269 | |
| 270 | // Writes an arbitrary value to the mask register. |
| 271 | |
| 272 | void (*i2eWriteMask)(struct _i2eBordStr *, unsigned char); |
| 273 | |
| 274 | |
| 275 | // State information |
| 276 | |
| 277 | // During downloading, indicates the number of blocks remaining to download |
| 278 | // to the board. |
| 279 | |
| 280 | short i2eToLoad; |
| 281 | |
| 282 | // State of board (see manifests below) (e.g., whether in reset condition, |
| 283 | // whether standard loadware is installed, etc. |
| 284 | |
| 285 | unsigned char i2eState; |
| 286 | |
| 287 | // These three fields are only valid when there is loadware running on the |
| 288 | // board. (i2eState == II_STATE_LOADED or i2eState == II_STATE_STDLOADED ) |
| 289 | |
| 290 | unsigned char i2eLVersion; // Loadware version |
| 291 | unsigned char i2eLRevision; // Loadware revision |
| 292 | unsigned char i2eLSub; // Loadware subrevision |
| 293 | |
| 294 | // Flags which only have meaning in the context of the standard loadware. |
| 295 | // Somewhat violates the layering concept, but there is so little additional |
| 296 | // needed at the board level (while much additional at the channel level), |
| 297 | // that this beats maintaining two different per-board structures. |
| 298 | |
| 299 | // Indicates which IRQ the board has been initialized (from software) to use |
| 300 | // For MicroChannel boards, any value different from IRQ_UNDEFINED means |
| 301 | // that the software command has been sent to enable interrupts (or specify |
| 302 | // they are disabled). Special value: IRQ_UNDEFINED indicates that the |
| 303 | // software command to select the interrupt has not yet been sent, therefore |
| 304 | // (since the standard loadware insists that it be sent before any other |
| 305 | // packets are sent) no other packets should be sent yet. |
| 306 | |
| 307 | unsigned short i2eUsingIrq; |
| 308 | |
| 309 | // This is set when we hit the MB_OUT_STUFFED mailbox, which prevents us |
| 310 | // putting more in the mailbox until an appropriate mailbox message is |
| 311 | // received. |
| 312 | |
| 313 | unsigned char i2eWaitingForEmptyFifo; |
| 314 | |
| 315 | // Any mailbox bits waiting to be sent to the board are OR'ed in here. |
| 316 | |
| 317 | unsigned char i2eOutMailWaiting; |
| 318 | |
| 319 | // The head of any incoming packet is read into here, is then examined and |
| 320 | // we dispatch accordingly. |
| 321 | |
| 322 | unsigned short i2eLeadoffWord[1]; |
| 323 | |
| 324 | // Running counter of interrupts where the mailbox indicated incoming data. |
| 325 | |
| 326 | unsigned short i2eFifoInInts; |
| 327 | |
| 328 | // Running counter of interrupts where the mailbox indicated outgoing data |
| 329 | // had been stripped. |
| 330 | |
| 331 | unsigned short i2eFifoOutInts; |
| 332 | |
| 333 | // If not void, gives the address of a routine to call if fatal board error |
| 334 | // is found (only applies to standard l/w). |
| 335 | |
| 336 | void (*i2eFatalTrap)(struct _i2eBordStr *); |
| 337 | |
| 338 | // Will point to an array of some sort of channel structures (whose format |
| 339 | // is unknown at this level, being a function of what loadware is |
| 340 | // installed and the code configuration (max sizes of buffers, etc.)). |
| 341 | |
| 342 | void *i2eChannelPtr; |
| 343 | |
| 344 | // Set indicates that the board has gone fatal. |
| 345 | |
| 346 | unsigned short i2eFatal; |
| 347 | |
| 348 | // The number of elements pointed to by i2eChannelPtr. |
| 349 | |
| 350 | unsigned short i2eChannelCnt; |
| 351 | |
| 352 | // Ring-buffers of channel structures whose channels have particular needs. |
| 353 | |
| 354 | rwlock_t Fbuf_spinlock; |
| 355 | volatile |
| 356 | unsigned short i2Fbuf_strip; // Strip index |
| 357 | volatile |
| 358 | unsigned short i2Fbuf_stuff; // Stuff index |
| 359 | void *i2Fbuf[CH_QUEUE_SIZE]; // An array of channel pointers |
| 360 | // of channels who need to send |
| 361 | // flow control packets. |
| 362 | rwlock_t Dbuf_spinlock; |
| 363 | volatile |
| 364 | unsigned short i2Dbuf_strip; // Strip index |
| 365 | volatile |
| 366 | unsigned short i2Dbuf_stuff; // Stuff index |
| 367 | void *i2Dbuf[CH_QUEUE_SIZE]; // An array of channel pointers |
| 368 | // of channels who need to send |
| 369 | // data or in-line command packets. |
| 370 | rwlock_t Bbuf_spinlock; |
| 371 | volatile |
| 372 | unsigned short i2Bbuf_strip; // Strip index |
| 373 | volatile |
| 374 | unsigned short i2Bbuf_stuff; // Stuff index |
| 375 | void *i2Bbuf[CH_QUEUE_SIZE]; // An array of channel pointers |
| 376 | // of channels who need to send |
| 377 | // bypass command packets. |
| 378 | |
| 379 | /* |
| 380 | * A set of flags to indicate that certain events have occurred on at least |
| 381 | * one of the ports on this board. We use this to decide whether to spin |
| 382 | * through the channels looking for breaks, etc. |
| 383 | */ |
| 384 | int got_input; |
| 385 | int status_change; |
| 386 | bidStat channelBtypes; |
| 387 | |
| 388 | /* |
| 389 | * Debugging counters, etc. |
| 390 | */ |
| 391 | unsigned long debugFlowQueued; |
| 392 | unsigned long debugInlineQueued; |
| 393 | unsigned long debugDataQueued; |
| 394 | unsigned long debugBypassQueued; |
| 395 | unsigned long debugFlowCount; |
| 396 | unsigned long debugInlineCount; |
| 397 | unsigned long debugBypassCount; |
| 398 | |
| 399 | rwlock_t read_fifo_spinlock; |
| 400 | rwlock_t write_fifo_spinlock; |
| 401 | |
| 402 | // For queuing interrupt bottom half handlers. /\/\|=mhw=|\/\/ |
| 403 | struct work_struct tqueue_interrupt; |
| 404 | |
| 405 | struct timer_list SendPendingTimer; // Used by iiSendPending |
| 406 | unsigned int SendPendingRetry; |
| 407 | } i2eBordStr, *i2eBordStrPtr; |
| 408 | |
| 409 | //------------------------------------------------------------------- |
| 410 | // Macro Definitions for the indirect calls defined in the i2eBordStr |
| 411 | //------------------------------------------------------------------- |
| 412 | // |
| 413 | #define iiDelay(a,b) (*(a)->i2eDelay)(b) |
| 414 | #define iiWriteBuf(a,b,c) (*(a)->i2eWriteBuf)(a,b,c) |
| 415 | #define iiReadBuf(a,b,c) (*(a)->i2eReadBuf)(a,b,c) |
| 416 | |
| 417 | #define iiWriteWord(a,b) (*(a)->i2eWriteWord)(a,b) |
| 418 | #define iiReadWord(a) (*(a)->i2eReadWord)(a) |
| 419 | |
| 420 | #define iiWaitForTxEmpty(a,b) (*(a)->i2eWaitForTxEmpty)(a,b) |
| 421 | |
| 422 | #define iiTxMailEmpty(a) (*(a)->i2eTxMailEmpty)(a) |
| 423 | #define iiTrySendMail(a,b) (*(a)->i2eTrySendMail)(a,b) |
| 424 | |
| 425 | #define iiGetMail(a) (*(a)->i2eGetMail)(a) |
| 426 | #define iiEnableMailIrq(a) (*(a)->i2eEnableMailIrq)(a) |
| 427 | #define iiDisableMailIrq(a) (*(a)->i2eWriteMask)(a,0) |
| 428 | #define iiWriteMask(a,b) (*(a)->i2eWriteMask)(a,b) |
| 429 | |
| 430 | //------------------------------------------- |
| 431 | // Manifests for i2eBordStr: |
| 432 | //------------------------------------------- |
| 433 | |
| 434 | #define YES 1 |
| 435 | #define NO 0 |
| 436 | |
| 437 | #define NULLFUNC (void (*)(void))0 |
| 438 | #define NULLPTR (void *)0 |
| 439 | |
| 440 | typedef void (*delayFunc_t)(unsigned int); |
| 441 | |
| 442 | // i2eValid |
| 443 | // |
| 444 | #define I2E_MAGIC 0x4251 // Structure is valid. |
| 445 | #define I2E_INCOMPLETE 0x1122 // Structure failed during init. |
| 446 | |
| 447 | |
| 448 | // i2eError |
| 449 | // |
| 450 | #define I2EE_GOOD 0 // Operation successful |
| 451 | #define I2EE_BADADDR 1 // Address out of range |
| 452 | #define I2EE_BADSTATE 2 // Attempt to perform a function when the board |
| 453 | // structure was in the incorrect state |
| 454 | #define I2EE_BADMAGIC 3 // Bad magic number from Power On test (i2ePomSize |
| 455 | // reflects what was read |
| 456 | #define I2EE_PORM_SHORT 4 // Power On message too short |
| 457 | #define I2EE_PORM_LONG 5 // Power On message too long |
| 458 | #define I2EE_BAD_FAMILY 6 // Un-supported board family type |
| 459 | #define I2EE_INCONSIST 7 // Firmware reports something impossible, |
| 460 | // e.g. unexpected number of ports... Almost no |
| 461 | // excuse other than bad FIFO... |
| 462 | #define I2EE_POSTERR 8 // Power-On self test reported a bad error |
| 463 | #define I2EE_BADBUS 9 // Unknown Bus type declared in message |
| 464 | #define I2EE_TXE_TIME 10 // Timed out waiting for TX Fifo to empty |
| 465 | #define I2EE_INVALID 11 // i2eValid field does not indicate a valid and |
| 466 | // complete board structure (for functions which |
| 467 | // require this be so.) |
| 468 | #define I2EE_BAD_PORT 12 // Discrepancy between channels actually found and |
| 469 | // what the product is supposed to have. Check |
| 470 | // i2eGoodMap vs i2eChannelMap for details. |
| 471 | #define I2EE_BAD_IRQ 13 // Someone specified an unsupported IRQ |
| 472 | #define I2EE_NOCHANNELS 14 // No channel structures have been defined (for |
| 473 | // functions requiring this). |
| 474 | |
| 475 | // i2eFifoStyle |
| 476 | // |
| 477 | #define FIFO_II 0 /* IntelliPort-II style: see also i2hw.h */ |
| 478 | #define FIFO_IIEX 1 /* IntelliPort-IIEX style */ |
| 479 | |
| 480 | // i2eGetMail |
| 481 | // |
| 482 | #define NO_MAIL_HERE 0x1111 // Since mail is unsigned char, cannot possibly |
| 483 | // promote to 0x1111. |
| 484 | // i2eState |
| 485 | // |
| 486 | #define II_STATE_COLD 0 // Addresses have been defined, but board not even |
| 487 | // reset yet. |
| 488 | #define II_STATE_RESET 1 // Board,if it exists, has just been reset |
| 489 | #define II_STATE_READY 2 // Board ready for its first block |
| 490 | #define II_STATE_LOADING 3 // Board continuing load |
| 491 | #define II_STATE_LOADED 4 // Board has finished load: status ok |
| 492 | #define II_STATE_BADLOAD 5 // Board has finished load: failed! |
| 493 | #define II_STATE_STDLOADED 6 // Board has finished load: standard firmware |
| 494 | |
| 495 | // i2eUsingIrq |
| 496 | // |
| 497 | #define IRQ_UNDEFINED 0x1352 // No valid irq (or polling = 0) can ever |
| 498 | // promote to this! |
| 499 | //------------------------------------------ |
| 500 | // Handy Macros for i2ellis.c and others |
| 501 | // Note these are common to -II and -IIEX |
| 502 | //------------------------------------------ |
| 503 | |
| 504 | // Given a pointer to the board structure, does the input FIFO have any data or |
| 505 | // not? |
| 506 | // |
| 507 | #define HAS_INPUT(pB) !(INB(pB->i2eStatus) & ST_IN_EMPTY) |
| 508 | #define HAS_NO_INPUT(pB) (INB(pB->i2eStatus) & ST_IN_EMPTY) |
| 509 | |
| 510 | // Given a pointer to board structure, read a byte or word from the fifo |
| 511 | // |
| 512 | #define BYTE_FROM(pB) (unsigned char)INB(pB->i2eData) |
| 513 | #define WORD_FROM(pB) (unsigned short)INW(pB->i2eData) |
| 514 | |
| 515 | // Given a pointer to board structure, is there room for any data to be written |
| 516 | // to the data fifo? |
| 517 | // |
| 518 | #define HAS_OUTROOM(pB) !(INB(pB->i2eStatus) & ST_OUT_FULL) |
| 519 | #define HAS_NO_OUTROOM(pB) (INB(pB->i2eStatus) & ST_OUT_FULL) |
| 520 | |
| 521 | // Given a pointer to board structure, write a single byte to the fifo |
| 522 | // structure. Note that for 16-bit interfaces, the high order byte is undefined |
| 523 | // and unknown. |
| 524 | // |
| 525 | #define BYTE_TO(pB, c) OUTB(pB->i2eData,(c)) |
| 526 | |
| 527 | // Write a word to the fifo structure. For 8-bit interfaces, this may have |
| 528 | // unknown results. |
| 529 | // |
| 530 | #define WORD_TO(pB, c) OUTW(pB->i2eData,(c)) |
| 531 | |
| 532 | // Given a pointer to the board structure, is there anything in the incoming |
| 533 | // mailbox? |
| 534 | // |
| 535 | #define HAS_MAIL(pB) (INB(pB->i2eStatus) & ST_IN_MAIL) |
| 536 | |
| 537 | #define UPDATE_FIFO_ROOM(pB) (pB)->i2eFifoRemains=(pB)->i2eFifoSize |
| 538 | |
| 539 | // Handy macro to round up a number (like the buffer write and read routines do) |
| 540 | // |
| 541 | #define ROUNDUP(number) (((number)+1) & (~1)) |
| 542 | |
| 543 | //------------------------------------------ |
| 544 | // Function Declarations for i2ellis.c |
| 545 | //------------------------------------------ |
| 546 | // |
| 547 | // Functions called directly |
| 548 | // |
| 549 | // Initialization of a board & structure is in four (five!) parts: |
| 550 | // |
| 551 | // 0) iiEllisInit() - Initialize iiEllis subsystem. |
| 552 | // 1) iiSetAddress() - Define the board address & delay function for a board. |
| 553 | // 2) iiReset() - Reset the board (provided it exists) |
| 554 | // -- Note you may do this to several boards -- |
| 555 | // 3) iiResetDelay() - Delay for 2 seconds (once for all boards) |
| 556 | // 4) iiInitialize() - Attempt to read Power-up message; further initialize |
| 557 | // accelerators |
| 558 | // |
| 559 | // Then you may use iiDownloadAll() or iiDownloadFile() (in i2file.c) to write |
| 560 | // loadware. To change loadware, you must begin again with step 2, resetting |
| 561 | // the board again (step 1 not needed). |
| 562 | |
| 563 | static void iiEllisInit(void); |
| 564 | static int iiSetAddress(i2eBordStrPtr, int, delayFunc_t ); |
| 565 | static int iiReset(i2eBordStrPtr); |
| 566 | static int iiResetDelay(i2eBordStrPtr); |
| 567 | static int iiInitialize(i2eBordStrPtr); |
| 568 | |
| 569 | // Routine to validate that all channels expected are there. |
| 570 | // |
| 571 | extern int iiValidateChannels(i2eBordStrPtr); |
| 572 | |
| 573 | // Routine used to download a block of loadware. |
| 574 | // |
| 575 | static int iiDownloadBlock(i2eBordStrPtr, loadHdrStrPtr, int); |
| 576 | |
| 577 | // Return values given by iiDownloadBlock, iiDownloadAll, iiDownloadFile: |
| 578 | // |
| 579 | #define II_DOWN_BADVALID 0 // board structure is invalid |
| 580 | #define II_DOWN_CONTINUING 1 // So far, so good, firmware expects more |
| 581 | #define II_DOWN_GOOD 2 // Download complete, CRC good |
| 582 | #define II_DOWN_BAD 3 // Download complete, but CRC bad |
| 583 | #define II_DOWN_BADFILE 4 // Bad magic number in loadware file |
| 584 | #define II_DOWN_BADSTATE 5 // Board is in an inappropriate state for |
| 585 | // downloading loadware. (see i2eState) |
| 586 | #define II_DOWN_TIMEOUT 6 // Timeout waiting for firmware |
| 587 | #define II_DOWN_OVER 7 // Too much data |
| 588 | #define II_DOWN_UNDER 8 // Not enough data |
| 589 | #define II_DOWN_NOFILE 9 // Loadware file not found |
| 590 | |
| 591 | // Routine to download an entire loadware module: Return values are a subset of |
| 592 | // iiDownloadBlock's, excluding, of course, II_DOWN_CONTINUING |
| 593 | // |
| 594 | static int iiDownloadAll(i2eBordStrPtr, loadHdrStrPtr, int, int); |
| 595 | |
| 596 | // Called indirectly always. Needed externally so the routine might be |
| 597 | // SPECIFIED as an argument to iiReset() |
| 598 | // |
| 599 | //static void ii2DelayIO(unsigned int); // N-millisecond delay using |
| 600 | //hardware spin |
| 601 | //static void ii2DelayTimer(unsigned int); // N-millisecond delay using Linux |
| 602 | //timer |
| 603 | |
| 604 | // Many functions defined here return True if good, False otherwise, with an |
| 605 | // error code in i2eError field. Here is a handy macro for setting the error |
| 606 | // code and returning. |
| 607 | // |
| 608 | #define COMPLETE(pB,code) \ |
Andrew Morton | 2723f96 | 2007-01-05 16:36:35 -0800 | [diff] [blame] | 609 | do { \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | pB->i2eError = code; \ |
| 611 | return (code == I2EE_GOOD);\ |
Andrew Morton | 2723f96 | 2007-01-05 16:36:35 -0800 | [diff] [blame] | 612 | } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | |
| 614 | #endif // I2ELLIS_H |