Kim Phillips | 728de4c9 | 2007-04-13 01:26:03 -0500 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ucc_geth_mii.h |
| 3 | * |
Kim Phillips | 4e19b5c | 2007-05-11 18:25:07 -0500 | [diff] [blame] | 4 | * QE UCC Gigabit Ethernet Driver -- MII Management Bus Implementation |
| 5 | * Provides Bus interface for MII Management regs in the UCC register space |
Kim Phillips | 728de4c9 | 2007-04-13 01:26:03 -0500 | [diff] [blame] | 6 | * |
Kim Phillips | 4e19b5c | 2007-05-11 18:25:07 -0500 | [diff] [blame] | 7 | * Copyright (C) 2007 Freescale Semiconductor, Inc. |
Kim Phillips | 728de4c9 | 2007-04-13 01:26:03 -0500 | [diff] [blame] | 8 | * |
Kim Phillips | 4e19b5c | 2007-05-11 18:25:07 -0500 | [diff] [blame] | 9 | * Authors: Li Yang <leoli@freescale.com> |
| 10 | * Kim Phillips <kim.phillips@freescale.com> |
Kim Phillips | 728de4c9 | 2007-04-13 01:26:03 -0500 | [diff] [blame] | 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms of the GNU General Public License as published by the |
| 14 | * Free Software Foundation; either version 2 of the License, or (at your |
| 15 | * option) any later version. |
| 16 | * |
| 17 | */ |
| 18 | #ifndef __UEC_MII_H |
| 19 | #define __UEC_MII_H |
| 20 | |
| 21 | /* UCC GETH MIIMCFG (MII Management Configuration Register) */ |
| 22 | #define MIIMCFG_RESET_MANAGEMENT 0x80000000 /* Reset |
| 23 | management */ |
| 24 | #define MIIMCFG_NO_PREAMBLE 0x00000010 /* Preamble |
| 25 | suppress */ |
| 26 | #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) /* clock divide |
| 27 | << shift */ |
| 28 | #define MIIMCFG_CLOCK_DIVIDE_MAX 0xf /* max clock divide */ |
| 29 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_2 0x00000000 |
| 30 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 |
| 31 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 |
| 32 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 |
| 33 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 |
| 34 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 |
| 35 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_16 0x00000008 |
| 36 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 |
| 37 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 |
| 38 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_32 0x00000009 |
| 39 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_48 0x0000000a |
| 40 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_64 0x0000000b |
| 41 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_80 0x0000000c |
| 42 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112 0x0000000d |
| 43 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_160 0x0000000e |
| 44 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_224 0x0000000f |
| 45 | |
| 46 | /* UCC GETH MIIMCOM (MII Management Command Register) */ |
| 47 | #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ |
| 48 | #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ |
| 49 | |
| 50 | /* UCC GETH MIIMADD (MII Management Address Register) */ |
| 51 | #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) /* PHY Address |
| 52 | << shift */ |
| 53 | #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) /* PHY Register |
| 54 | << shift */ |
| 55 | |
| 56 | /* UCC GETH MIIMCON (MII Management Control Register) */ |
| 57 | #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) /* PHY Control |
| 58 | << shift */ |
| 59 | #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) /* PHY Status |
| 60 | << shift */ |
| 61 | |
| 62 | /* UCC GETH MIIMIND (MII Management Indicator Register) */ |
| 63 | #define MIIMIND_NOT_VALID 0x00000004 /* Not valid */ |
| 64 | #define MIIMIND_SCAN 0x00000002 /* Scan in |
| 65 | progress */ |
| 66 | #define MIIMIND_BUSY 0x00000001 |
| 67 | |
| 68 | /* Initial TBI Physical Address */ |
| 69 | #define UTBIPAR_INIT_TBIPA 0x1f |
| 70 | |
| 71 | struct ucc_mii_mng { |
| 72 | u32 miimcfg; /* MII management configuration reg */ |
| 73 | u32 miimcom; /* MII management command reg */ |
| 74 | u32 miimadd; /* MII management address reg */ |
| 75 | u32 miimcon; /* MII management control reg */ |
| 76 | u32 miimstat; /* MII management status reg */ |
| 77 | u32 miimind; /* MII management indication reg */ |
| 78 | u8 notcare[28]; /* Space holder */ |
| 79 | u32 utbipar; /* TBI phy address reg */ |
| 80 | } __attribute__ ((packed)); |
| 81 | |
| 82 | /* TBI / MII Set Register */ |
| 83 | enum enet_tbi_mii_reg { |
| 84 | ENET_TBI_MII_CR = 0x00, /* Control */ |
| 85 | ENET_TBI_MII_SR = 0x01, /* Status */ |
| 86 | ENET_TBI_MII_ANA = 0x04, /* AN advertisement */ |
| 87 | ENET_TBI_MII_ANLPBPA = 0x05, /* AN link partner base page ability */ |
| 88 | ENET_TBI_MII_ANEX = 0x06, /* AN expansion */ |
| 89 | ENET_TBI_MII_ANNPT = 0x07, /* AN next page transmit */ |
| 90 | ENET_TBI_MII_ANLPANP = 0x08, /* AN link partner ability next page */ |
| 91 | ENET_TBI_MII_EXST = 0x0F, /* Extended status */ |
| 92 | ENET_TBI_MII_JD = 0x10, /* Jitter diagnostics */ |
| 93 | ENET_TBI_MII_TBICON = 0x11 /* TBI control */ |
| 94 | }; |
| 95 | |
| 96 | int uec_mdio_read(struct mii_bus *bus, int mii_id, int regnum); |
| 97 | int uec_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value); |
| 98 | int __init uec_mdio_init(void); |
Anton Vorontsov | 87e417b | 2007-12-17 14:54:35 +0300 | [diff] [blame^] | 99 | void uec_mdio_exit(void); |
Kim Phillips | 728de4c9 | 2007-04-13 01:26:03 -0500 | [diff] [blame] | 100 | #endif /* __UEC_MII_H */ |