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gerrit-public.fairphone.software / kernel / msm-4.19 / 8b2f35504d81422beb9e3562ee3dd99e8567cc80 / . / include / asm-powerpc / cputable.h
blob: 6fe5c9d4ca3b946e2ad5f348070851b6e039d086 [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb0212006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]26#define PPC_FEATURE_PA6T 0x00000800
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]29
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__
35
36/* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
38 */
39struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]40
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]42typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]43
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]44enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]45 PPC_OPROFILE_INVALID = 0,
46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +0100[diff] [blame]50 PPC_OPROFILE_CELL = 5,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]51};
52
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]53struct cpu_spec {
54 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
55 unsigned int pvr_mask;
56 unsigned int pvr_value;
57
58 char *cpu_name;
59 unsigned long cpu_features; /* Kernel features */
60 unsigned int cpu_user_features; /* Userland features */
61
62 /* cache line sizes */
63 unsigned int icache_bsize;
64 unsigned int dcache_bsize;
65
66 /* number of performance monitor counters */
67 unsigned int num_pmcs;
68
69 /* this is called to initialize various CPU bits like L1 cache,
70 * BHT, SPD, etc... from head.S before branching to identify_machine
71 */
72 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]73 /* Used to restore cpu setup on secondary processors and at resume */
74 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]75
76 /* Used by oprofile userspace to select the right counters */
77 char *oprofile_cpu_type;
78
79 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]80 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]81
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]82 /* Bit locations inside the mmcra change */
83 unsigned long oprofile_mmcra_sihv;
84 unsigned long oprofile_mmcra_sipr;
85
86 /* Bits to clear during an oprofile exception */
87 unsigned long oprofile_mmcra_clear;
88
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]89 /* Name of processor class, for the ELF AT_PLATFORM entry */
90 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]91};
92
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]93extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]94
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]95extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
96
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]97extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]98extern void do_feature_fixups(unsigned long value, void *fixup_start,
99 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]100
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]101#endif /* __ASSEMBLY__ */
102
103/* CPU kernel features */
104
105/* Retain the 32b definitions all use bottom half of word */
106#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
107#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
108#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
109#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
110#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
111#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
112#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
113#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
114#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
115#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
116#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
117#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
118#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
119#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
120#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
121#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
122#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
123#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
124#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
125#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]126#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]127#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
128#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]129
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]130/*
131 * Add the 64-bit processor unique features in the top half of the word;
132 * on 32-bit, make the names available but defined to be 0.
133 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]134#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]135#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]136#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]137#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]138#endif
139
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]140#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
141#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
142#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
143#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
144#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
145#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
146#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
147#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
148#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
149#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
150#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
151#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
152#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]153#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]154#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]155
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]156#ifndef __ASSEMBLY__
157
Stephen Rothwell04704662006-11-30 11:46:22 +1100[diff] [blame]158#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
159 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
160 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]161
162/* We only set the altivec features if the kernel was compiled with altivec
163 * support
164 */
165#ifdef CONFIG_ALTIVEC
166#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
167#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
168#else
169#define CPU_FTR_ALTIVEC_COMP 0
170#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
171#endif
172
173/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]174 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
175 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]176 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]177#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
178 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]179#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
180#else
181#define CPU_FTR_COMMON 0
182#endif
183
184/* The powersave features NAP & DOZE seems to confuse BDI when
185 debugging. So if a BDI is used, disable theses
186 */
187#ifndef CONFIG_BDI_SWITCH
188#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
189#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
190#else
191#define CPU_FTR_MAYBE_CAN_DOZE 0
192#define CPU_FTR_MAYBE_CAN_NAP 0
193#endif
194
195#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
196 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
197 !defined(CONFIG_BOOKE))
198
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]199#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
200#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
201 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]202 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]203#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]204 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
205 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]206#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
207 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]208 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]209#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
210 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]211 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
212 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]213#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
214 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]215 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
216 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]217#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
218 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
219 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]220 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]221#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
222 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
223 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]224 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]225#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
226 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
227 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]228 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]229#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
230 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
231 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]232 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]233#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
234 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
235 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]236 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]237#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
238 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
239 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]240 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]241#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
242 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
243 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]244 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]245#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
246 CPU_FTR_USE_TB | \
247 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
248 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
249 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]250 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]251#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
252 CPU_FTR_USE_TB | \
253 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
254 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]255 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]256#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
257 CPU_FTR_USE_TB | \
258 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
259 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]260 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]261#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
262 CPU_FTR_USE_TB | \
263 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
264 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
265 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]266 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]267#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
268 CPU_FTR_USE_TB | \
269 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
270 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
271 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]272 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]273#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
274 CPU_FTR_USE_TB | \
275 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
276 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
277 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]278 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]279#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
280 CPU_FTR_USE_TB | \
281 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
282 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
283 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]284 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]285#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
286 CPU_FTR_USE_TB | \
287 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
288 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
289 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]290 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]291#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
292 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
293#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
294 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
295#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
296 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
297 CPU_FTR_COMMON)
298#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
299 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]300#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
301#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
302 CPU_FTR_NODSISRALIGN)
303#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
304 CPU_FTR_NODSISRALIGN)
305#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
306#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
307 CPU_FTR_NODSISRALIGN)
308#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
309 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
310#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100[diff] [blame]311
312/* 64-bit CPUs */
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]313#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]314 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]315#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
316 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
317 CPU_FTR_MMCRA | CPU_FTR_CTRL)
318#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]319 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
320 CPU_FTR_MMCRA)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]321#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]322 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]323 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
324#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]326 CPU_FTR_MMCRA | CPU_FTR_SMT | \
327 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]328 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]329#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]331 CPU_FTR_MMCRA | CPU_FTR_SMT | \
332 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]333 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
334#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
336 CPU_FTR_MMCRA | CPU_FTR_SMT | \
337 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
338 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
339 CPU_FTR_SPURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]340#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]341 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]342 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]343 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]344#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
346 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
347 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]348#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
349 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]350
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]351#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]352#define CPU_FTRS_POSSIBLE \
353 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]354 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]355 CPU_FTRS_CELL | CPU_FTRS_PA6T)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]356#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]357enum {
358 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]359#if CLASSIC_PPC
360 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
361 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
362 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
363 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
364 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
365 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
366 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
367 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
368#else
369 CPU_FTRS_GENERIC_32 |
370#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]371#ifdef CONFIG_8xx
372 CPU_FTRS_8XX |
373#endif
374#ifdef CONFIG_40x
375 CPU_FTRS_40X |
376#endif
377#ifdef CONFIG_44x
378 CPU_FTRS_44X |
379#endif
380#ifdef CONFIG_E200
381 CPU_FTRS_E200 |
382#endif
383#ifdef CONFIG_E500
384 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
385#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]386 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]387};
388#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]389
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]390#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]391#define CPU_FTRS_ALWAYS \
392 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]393 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]394 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]395#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]396enum {
397 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]398#if CLASSIC_PPC
399 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
400 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
401 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
402 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
403 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
404 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
405 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
406 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
407#else
408 CPU_FTRS_GENERIC_32 &
409#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]410#ifdef CONFIG_8xx
411 CPU_FTRS_8XX &
412#endif
413#ifdef CONFIG_40x
414 CPU_FTRS_40X &
415#endif
416#ifdef CONFIG_44x
417 CPU_FTRS_44X &
418#endif
419#ifdef CONFIG_E200
420 CPU_FTRS_E200 &
421#endif
422#ifdef CONFIG_E500
423 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
424#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]425 CPU_FTRS_POSSIBLE,
426};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]427#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]428
429static inline int cpu_has_feature(unsigned long feature)
430{
431 return (CPU_FTRS_ALWAYS & feature) ||
432 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]433 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]434 & feature);
435}
436
437#endif /* !__ASSEMBLY__ */
438
439#ifdef __ASSEMBLY__
440
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]441#define BEGIN_FTR_SECTION_NESTED(label) label:
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]442#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]443#define END_FTR_SECTION_NESTED(msk, val, label) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]444 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]445#define END_FTR_SECTION(msk, val) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]446 END_FTR_SECTION_NESTED(msk, val, 97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]447
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]448#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
449#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
450#endif /* __ASSEMBLY__ */
451
452#endif /* __KERNEL__ */
453#endif /* __ASM_POWERPC_CPUTABLE_H */