blob: 29ceee366e44d7b1e86eab77adbfdcabba660ae1 [file] [log] [blame]
Florian Fainelli246d7f72014-08-27 17:04:56 -07001/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <net/dsa.h>
25
26#include "bcm_sf2.h"
27#include "bcm_sf2_regs.h"
28
29/* String, offset, and register size in bytes if different from 4 bytes */
30static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
31 { "TxOctets", 0x000, 8 },
32 { "TxDropPkts", 0x020 },
33 { "TxQPKTQ0", 0x030 },
34 { "TxBroadcastPkts", 0x040 },
35 { "TxMulticastPkts", 0x050 },
36 { "TxUnicastPKts", 0x060 },
37 { "TxCollisions", 0x070 },
38 { "TxSingleCollision", 0x080 },
39 { "TxMultipleCollision", 0x090 },
40 { "TxDeferredCollision", 0x0a0 },
41 { "TxLateCollision", 0x0b0 },
42 { "TxExcessiveCollision", 0x0c0 },
43 { "TxFrameInDisc", 0x0d0 },
44 { "TxPausePkts", 0x0e0 },
45 { "TxQPKTQ1", 0x0f0 },
46 { "TxQPKTQ2", 0x100 },
47 { "TxQPKTQ3", 0x110 },
48 { "TxQPKTQ4", 0x120 },
49 { "TxQPKTQ5", 0x130 },
50 { "RxOctets", 0x140, 8 },
51 { "RxUndersizePkts", 0x160 },
52 { "RxPausePkts", 0x170 },
53 { "RxPkts64Octets", 0x180 },
54 { "RxPkts65to127Octets", 0x190 },
55 { "RxPkts128to255Octets", 0x1a0 },
56 { "RxPkts256to511Octets", 0x1b0 },
57 { "RxPkts512to1023Octets", 0x1c0 },
58 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
59 { "RxOversizePkts", 0x1e0 },
60 { "RxJabbers", 0x1f0 },
61 { "RxAlignmentErrors", 0x200 },
62 { "RxFCSErrors", 0x210 },
63 { "RxGoodOctets", 0x220, 8 },
64 { "RxDropPkts", 0x240 },
65 { "RxUnicastPkts", 0x250 },
66 { "RxMulticastPkts", 0x260 },
67 { "RxBroadcastPkts", 0x270 },
68 { "RxSAChanges", 0x280 },
69 { "RxFragments", 0x290 },
70 { "RxJumboPkt", 0x2a0 },
71 { "RxSymblErr", 0x2b0 },
72 { "InRangeErrCount", 0x2c0 },
73 { "OutRangeErrCount", 0x2d0 },
74 { "EEELpiEvent", 0x2e0 },
75 { "EEELpiDuration", 0x2f0 },
76 { "RxDiscard", 0x300, 8 },
77 { "TxQPKTQ6", 0x320 },
78 { "TxQPKTQ7", 0x330 },
79 { "TxPkts64Octets", 0x340 },
80 { "TxPkts65to127Octets", 0x350 },
81 { "TxPkts128to255Octets", 0x360 },
82 { "TxPkts256to511Ocets", 0x370 },
83 { "TxPkts512to1023Ocets", 0x380 },
84 { "TxPkts1024toMaxPktOcets", 0x390 },
85};
86
87#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
88
89static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
90 int port, uint8_t *data)
91{
92 unsigned int i;
93
94 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
95 memcpy(data + i * ETH_GSTRING_LEN,
96 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
97}
98
99static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
100 int port, uint64_t *data)
101{
102 struct bcm_sf2_priv *priv = ds_to_priv(ds);
103 const struct bcm_sf2_hw_stats *s;
104 unsigned int i;
105 u64 val = 0;
106 u32 offset;
107
108 mutex_lock(&priv->stats_mutex);
109
110 /* Now fetch the per-port counters */
111 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
112 s = &bcm_sf2_mib[i];
113
114 /* Do a latched 64-bit read if needed */
115 offset = s->reg + CORE_P_MIB_OFFSET(port);
116 if (s->sizeof_stat == 8)
117 val = core_readq(priv, offset);
118 else
119 val = core_readl(priv, offset);
120
121 data[i] = (u64)val;
122 }
123
124 mutex_unlock(&priv->stats_mutex);
125}
126
127static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
128{
129 return BCM_SF2_STATS_SIZE;
130}
131
Alexander Duyckb4d23942014-09-15 13:00:27 -0400132static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
Florian Fainelli246d7f72014-08-27 17:04:56 -0700133{
134 return "Broadcom Starfighter 2";
135}
136
137static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
138{
139 struct bcm_sf2_priv *priv = ds_to_priv(ds);
140 unsigned int i;
141 u32 reg, val;
142
143 /* Enable the port memories */
144 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
145 reg &= ~P_TXQ_PSM_VDD(port);
146 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
147
148 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
149 reg = core_readl(priv, CORE_IMP_CTL);
150 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
151 reg &= ~(RX_DIS | TX_DIS);
152 core_writel(priv, reg, CORE_IMP_CTL);
153
154 /* Enable forwarding */
155 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
156
157 /* Enable IMP port in dumb mode */
158 reg = core_readl(priv, CORE_SWITCH_CTRL);
159 reg |= MII_DUMB_FWDG_EN;
160 core_writel(priv, reg, CORE_SWITCH_CTRL);
161
162 /* Resolve which bit controls the Broadcom tag */
163 switch (port) {
164 case 8:
165 val = BRCM_HDR_EN_P8;
166 break;
167 case 7:
168 val = BRCM_HDR_EN_P7;
169 break;
170 case 5:
171 val = BRCM_HDR_EN_P5;
172 break;
173 default:
174 val = 0;
175 break;
176 }
177
178 /* Enable Broadcom tags for IMP port */
179 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
180 reg |= val;
181 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
182
183 /* Enable reception Broadcom tag for CPU TX (switch RX) to
184 * allow us to tag outgoing frames
185 */
186 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
187 reg &= ~(1 << port);
188 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
189
190 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
191 * allow delivering frames to the per-port net_devices
192 */
193 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
194 reg &= ~(1 << port);
195 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
196
197 /* Force link status for IMP port */
198 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
199 reg |= (MII_SW_OR | LINK_STS);
200 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
201
202 /* Enable the IMP Port to be in the same VLAN as the other ports
203 * on a per-port basis such that we only have Port i and IMP in
204 * the same VLAN.
205 */
206 for (i = 0; i < priv->hw_params.num_ports; i++) {
207 if (!((1 << i) & ds->phys_port_mask))
208 continue;
209
210 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
211 reg |= (1 << port);
212 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
213 }
214}
215
216static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
217{
218 struct bcm_sf2_priv *priv = ds_to_priv(ds);
219 u32 reg;
220
221 /* Clear the memory power down */
222 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
223 reg &= ~P_TXQ_PSM_VDD(port);
224 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
225
226 /* Clear the Rx and Tx disable bits and set to no spanning tree */
227 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
228
229 /* Enable port 7 interrupts to get notified */
230 if (port == 7)
231 intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
232
233 /* Set this port, and only this one to be in the default VLAN */
234 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
235 reg &= ~PORT_VLAN_CTRL_MASK;
236 reg |= (1 << port);
237 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
238}
239
240static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
241{
242 struct bcm_sf2_priv *priv = ds_to_priv(ds);
243 u32 off, reg;
244
245 if (dsa_is_cpu_port(ds, port))
246 off = CORE_IMP_CTL;
247 else
248 off = CORE_G_PCTL_PORT(port);
249
250 reg = core_readl(priv, off);
251 reg |= RX_DIS | TX_DIS;
252 core_writel(priv, reg, off);
253
254 /* Power down the port memory */
255 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
256 reg |= P_TXQ_PSM_VDD(port);
257 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
258}
259
260static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
261{
262 struct bcm_sf2_priv *priv = dev_id;
263
264 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
265 ~priv->irq0_mask;
266 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
267
268 return IRQ_HANDLED;
269}
270
271static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
272{
273 struct bcm_sf2_priv *priv = dev_id;
274
275 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
276 ~priv->irq1_mask;
277 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
278
279 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
280 priv->port_sts[7].link = 1;
281 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
282 priv->port_sts[7].link = 0;
283
284 return IRQ_HANDLED;
285}
286
287static int bcm_sf2_sw_setup(struct dsa_switch *ds)
288{
289 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
290 struct bcm_sf2_priv *priv = ds_to_priv(ds);
291 struct device_node *dn;
292 void __iomem **base;
293 unsigned int port;
294 unsigned int i;
295 u32 reg, rev;
296 int ret;
297
298 spin_lock_init(&priv->indir_lock);
299 mutex_init(&priv->stats_mutex);
300
301 /* All the interesting properties are at the parent device_node
302 * level
303 */
304 dn = ds->pd->of_node->parent;
305
306 priv->irq0 = irq_of_parse_and_map(dn, 0);
307 priv->irq1 = irq_of_parse_and_map(dn, 1);
308
309 base = &priv->core;
310 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
311 *base = of_iomap(dn, i);
312 if (*base == NULL) {
313 pr_err("unable to find register: %s\n", reg_names[i]);
314 return -ENODEV;
315 }
316 base++;
317 }
318
319 /* Disable all interrupts and request them */
320 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
321 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
322 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
323 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
324 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
325 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
326
327 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
328 "switch_0", priv);
329 if (ret < 0) {
330 pr_err("failed to request switch_0 IRQ\n");
331 goto out_unmap;
332 }
333
334 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
335 "switch_1", priv);
336 if (ret < 0) {
337 pr_err("failed to request switch_1 IRQ\n");
338 goto out_free_irq0;
339 }
340
341 /* Reset the MIB counters */
342 reg = core_readl(priv, CORE_GMNCFGCFG);
343 reg |= RST_MIB_CNT;
344 core_writel(priv, reg, CORE_GMNCFGCFG);
345 reg &= ~RST_MIB_CNT;
346 core_writel(priv, reg, CORE_GMNCFGCFG);
347
348 /* Get the maximum number of ports for this switch */
349 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
350 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
351 priv->hw_params.num_ports = DSA_MAX_PORTS;
352
353 /* Assume a single GPHY setup if we can't read that property */
354 if (of_property_read_u32(dn, "brcm,num-gphy",
355 &priv->hw_params.num_gphy))
356 priv->hw_params.num_gphy = 1;
357
358 /* Enable all valid ports and disable those unused */
359 for (port = 0; port < priv->hw_params.num_ports; port++) {
360 /* IMP port receives special treatment */
361 if ((1 << port) & ds->phys_port_mask)
362 bcm_sf2_port_setup(ds, port);
363 else if (dsa_is_cpu_port(ds, port))
364 bcm_sf2_imp_setup(ds, port);
365 else
366 bcm_sf2_port_disable(ds, port);
367 }
368
369 /* Include the pseudo-PHY address and the broadcast PHY address to
370 * divert reads towards our workaround
371 */
372 ds->phys_mii_mask |= ((1 << 30) | (1 << 0));
373
374 rev = reg_readl(priv, REG_SWITCH_REVISION);
375 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
376 SWITCH_TOP_REV_MASK;
377 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
378
Florian Fainelliaa9aef72014-09-19 13:07:55 -0700379 rev = reg_readl(priv, REG_PHY_REVISION);
380 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
381
Florian Fainelli246d7f72014-08-27 17:04:56 -0700382 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
383 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
384 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
385 priv->core, priv->irq0, priv->irq1);
386
387 return 0;
388
389out_free_irq0:
390 free_irq(priv->irq0, priv);
391out_unmap:
392 base = &priv->core;
393 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
394 iounmap(*base);
395 base++;
396 }
397 return ret;
398}
399
400static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
401{
402 return 0;
403}
404
Florian Fainelliaa9aef72014-09-19 13:07:55 -0700405static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
406{
407 struct bcm_sf2_priv *priv = ds_to_priv(ds);
408
409 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
410 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
411 * the REG_PHY_REVISION register layout is.
412 */
413
414 return priv->hw_params.gphy_rev;
415}
416
Florian Fainelli246d7f72014-08-27 17:04:56 -0700417static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
418 int regnum, u16 val)
419{
420 struct bcm_sf2_priv *priv = ds_to_priv(ds);
421 int ret = 0;
422 u32 reg;
423
424 reg = reg_readl(priv, REG_SWITCH_CNTRL);
425 reg |= MDIO_MASTER_SEL;
426 reg_writel(priv, reg, REG_SWITCH_CNTRL);
427
428 /* Page << 8 | offset */
429 reg = 0x70;
430 reg <<= 2;
431 core_writel(priv, addr, reg);
432
433 /* Page << 8 | offset */
434 reg = 0x80 << 8 | regnum << 1;
435 reg <<= 2;
436
437 if (op)
438 ret = core_readl(priv, reg);
439 else
440 core_writel(priv, val, reg);
441
442 reg = reg_readl(priv, REG_SWITCH_CNTRL);
443 reg &= ~MDIO_MASTER_SEL;
444 reg_writel(priv, reg, REG_SWITCH_CNTRL);
445
446 return ret & 0xffff;
447}
448
449static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
450{
451 /* Intercept reads from the MDIO broadcast address or Broadcom
452 * pseudo-PHY address
453 */
454 switch (addr) {
455 case 0:
456 case 30:
457 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
458 default:
459 return 0xffff;
460 }
461}
462
463static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
464 u16 val)
465{
466 /* Intercept writes to the MDIO broadcast address or Broadcom
467 * pseudo-PHY address
468 */
469 switch (addr) {
470 case 0:
471 case 30:
472 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
473 break;
474 }
475
476 return 0;
477}
478
479static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
480 struct phy_device *phydev)
481{
482 struct bcm_sf2_priv *priv = ds_to_priv(ds);
483 u32 id_mode_dis = 0, port_mode;
484 const char *str = NULL;
485 u32 reg;
486
487 switch (phydev->interface) {
488 case PHY_INTERFACE_MODE_RGMII:
489 str = "RGMII (no delay)";
490 id_mode_dis = 1;
491 case PHY_INTERFACE_MODE_RGMII_TXID:
492 if (!str)
493 str = "RGMII (TX delay)";
494 port_mode = EXT_GPHY;
495 break;
496 case PHY_INTERFACE_MODE_MII:
497 str = "MII";
498 port_mode = EXT_EPHY;
499 break;
500 case PHY_INTERFACE_MODE_REVMII:
501 str = "Reverse MII";
502 port_mode = EXT_REVMII;
503 break;
504 default:
505 goto force_link;
506 }
507
508 /* Clear id_mode_dis bit, and the existing port mode, but
509 * make sure we enable the RGMII block for data to pass
510 */
511 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
512 reg &= ~ID_MODE_DIS;
513 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
514 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
515
516 reg |= port_mode | RGMII_MODE_EN;
517 if (id_mode_dis)
518 reg |= ID_MODE_DIS;
519
520 if (phydev->pause) {
521 if (phydev->asym_pause)
522 reg |= TX_PAUSE_EN;
523 reg |= RX_PAUSE_EN;
524 }
525
526 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
527
528 pr_info("Port %d configured for %s\n", port, str);
529
530force_link:
531 /* Force link settings detected from the PHY */
532 reg = SW_OVERRIDE;
533 switch (phydev->speed) {
534 case SPEED_1000:
535 reg |= SPDSTS_1000 << SPEED_SHIFT;
536 break;
537 case SPEED_100:
538 reg |= SPDSTS_100 << SPEED_SHIFT;
539 break;
540 }
541
542 if (phydev->link)
543 reg |= LINK_STS;
544 if (phydev->duplex == DUPLEX_FULL)
545 reg |= DUPLX_MODE;
546
547 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
548}
549
550static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
551 struct fixed_phy_status *status)
552{
553 struct bcm_sf2_priv *priv = ds_to_priv(ds);
554 u32 link, duplex, pause, speed;
555 u32 reg;
556
557 link = core_readl(priv, CORE_LNKSTS);
558 duplex = core_readl(priv, CORE_DUPSTS);
559 pause = core_readl(priv, CORE_PAUSESTS);
560 speed = core_readl(priv, CORE_SPDSTS);
561
562 speed >>= (port * SPDSTS_SHIFT);
563 speed &= SPDSTS_MASK;
564
565 status->link = 0;
566
567 /* Port 7 is special as we do not get link status from CORE_LNKSTS,
568 * which means that we need to force the link at the port override
569 * level to get the data to flow. We do use what the interrupt handler
570 * did determine before.
571 */
572 if (port == 7) {
573 status->link = priv->port_sts[port].link;
574 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(7));
575 reg |= SW_OVERRIDE;
576 if (status->link)
577 reg |= LINK_STS;
578 else
579 reg &= ~LINK_STS;
580 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(7));
581 status->duplex = 1;
582 } else {
583 status->link = !!(link & (1 << port));
584 status->duplex = !!(duplex & (1 << port));
585 }
586
587 switch (speed) {
588 case SPDSTS_10:
589 status->speed = SPEED_10;
590 break;
591 case SPDSTS_100:
592 status->speed = SPEED_100;
593 break;
594 case SPDSTS_1000:
595 status->speed = SPEED_1000;
596 break;
597 }
598
599 if ((pause & (1 << port)) &&
600 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
601 status->asym_pause = 1;
602 status->pause = 1;
603 }
604
605 if (pause & (1 << port))
606 status->pause = 1;
607}
608
Florian Fainelli8cfa9492014-09-18 17:31:23 -0700609static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
610{
611 struct bcm_sf2_priv *priv = ds_to_priv(ds);
612 unsigned int port;
613
614 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
615 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
616 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
617 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
618 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
619 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
620
621 /* Disable all ports physically present including the IMP
622 * port, the other ones have already been disabled during
623 * bcm_sf2_sw_setup
624 */
625 for (port = 0; port < DSA_MAX_PORTS; port++) {
626 if ((1 << port) & ds->phys_port_mask ||
627 dsa_is_cpu_port(ds, port))
628 bcm_sf2_port_disable(ds, port);
629 }
630
631 return 0;
632}
633
634static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
635{
636 unsigned int timeout = 1000;
637 u32 reg;
638
639 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
640 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
641 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
642
643 do {
644 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
645 if (!(reg & SOFTWARE_RESET))
646 break;
647
648 usleep_range(1000, 2000);
649 } while (timeout-- > 0);
650
651 if (timeout == 0)
652 return -ETIMEDOUT;
653
654 return 0;
655}
656
657static int bcm_sf2_sw_resume(struct dsa_switch *ds)
658{
659 struct bcm_sf2_priv *priv = ds_to_priv(ds);
660 unsigned int port;
661 u32 reg;
662 int ret;
663
664 ret = bcm_sf2_sw_rst(priv);
665 if (ret) {
666 pr_err("%s: failed to software reset switch\n", __func__);
667 return ret;
668 }
669
670 /* Reinitialize the single GPHY */
671 if (priv->hw_params.num_gphy == 1) {
672 reg = reg_readl(priv, REG_SPHY_CNTRL);
673 reg |= PHY_RESET;
674 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS);
675 reg_writel(priv, reg, REG_SPHY_CNTRL);
676 udelay(21);
677 reg = reg_readl(priv, REG_SPHY_CNTRL);
678 reg &= ~PHY_RESET;
679 reg_writel(priv, reg, REG_SPHY_CNTRL);
680 }
681
682 for (port = 0; port < DSA_MAX_PORTS; port++) {
683 if ((1 << port) & ds->phys_port_mask)
684 bcm_sf2_port_setup(ds, port);
685 else if (dsa_is_cpu_port(ds, port))
686 bcm_sf2_imp_setup(ds, port);
687 }
688
689 return 0;
690}
691
Florian Fainelli246d7f72014-08-27 17:04:56 -0700692static struct dsa_switch_driver bcm_sf2_switch_driver = {
Florian Fainelliac7a04c2014-09-11 21:18:09 -0700693 .tag_protocol = DSA_TAG_PROTO_BRCM,
Florian Fainelli246d7f72014-08-27 17:04:56 -0700694 .priv_size = sizeof(struct bcm_sf2_priv),
695 .probe = bcm_sf2_sw_probe,
696 .setup = bcm_sf2_sw_setup,
697 .set_addr = bcm_sf2_sw_set_addr,
Florian Fainelliaa9aef72014-09-19 13:07:55 -0700698 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
Florian Fainelli246d7f72014-08-27 17:04:56 -0700699 .phy_read = bcm_sf2_sw_phy_read,
700 .phy_write = bcm_sf2_sw_phy_write,
701 .get_strings = bcm_sf2_sw_get_strings,
702 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
703 .get_sset_count = bcm_sf2_sw_get_sset_count,
704 .adjust_link = bcm_sf2_sw_adjust_link,
705 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
Florian Fainelli8cfa9492014-09-18 17:31:23 -0700706 .suspend = bcm_sf2_sw_suspend,
707 .resume = bcm_sf2_sw_resume,
Florian Fainelli246d7f72014-08-27 17:04:56 -0700708};
709
710static int __init bcm_sf2_init(void)
711{
712 register_switch_driver(&bcm_sf2_switch_driver);
713
714 return 0;
715}
716module_init(bcm_sf2_init);
717
718static void __exit bcm_sf2_exit(void)
719{
720 unregister_switch_driver(&bcm_sf2_switch_driver);
721}
722module_exit(bcm_sf2_exit);
723
724MODULE_AUTHOR("Broadcom Corporation");
725MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
726MODULE_LICENSE("GPL");
727MODULE_ALIAS("platform:brcm-sf2");