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gerrit-public.fairphone.software / kernel / msm-4.19 / 09ebf366599d691ef25c343cb66fe19ce2a74d52 / . / arch / arm / boot / dts / imx51.dtsi
blob: 76d84a4b8508e154fd267a2d37d7f2214e015f6b [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx51-pinfunc.h"
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]25 };
26
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 ckil {
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
41 };
42
43 ckih1 {
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
46 };
47
48 ckih2 {
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
51 };
52
53 osc {
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
56 };
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "simple-bus";
63 interrupt-parent = <&tzic>;
64 ranges;
65
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]66 ipu: ipu@40000000 {
67 #crtc-cells = <1>;
68 compatible = "fsl,imx51-ipu";
69 reg = <0x40000000 0x20000000>;
70 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]71 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
72 clock-names = "bus", "di0", "di1";
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]73 };
74
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]75 aips@70000000 { /* AIPS1 */
76 compatible = "fsl,aips-bus", "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 reg = <0x70000000 0x10000000>;
80 ranges;
81
82 spba@70000000 {
83 compatible = "fsl,spba-bus", "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 reg = <0x70000000 0x40000>;
87 ranges;
88
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]89 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]90 compatible = "fsl,imx51-esdhc";
91 reg = <0x70004000 0x4000>;
92 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]93 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
94 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]95 status = "disabled";
96 };
97
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]98 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]99 compatible = "fsl,imx51-esdhc";
100 reg = <0x70008000 0x4000>;
101 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]102 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
103 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]104 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]105 status = "disabled";
106 };
107
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]108 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]109 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
110 reg = <0x7000c000 0x4000>;
111 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]112 clocks = <&clks 32>, <&clks 33>;
113 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]114 status = "disabled";
115 };
116
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]117 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "fsl,imx51-ecspi";
121 reg = <0x70010000 0x4000>;
122 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]123 clocks = <&clks 51>, <&clks 52>;
124 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]125 status = "disabled";
126 };
127
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]128 ssi2: ssi@70014000 {
129 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
130 reg = <0x70014000 0x4000>;
131 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]132 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]133 fsl,fifo-depth = <15>;
134 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
135 status = "disabled";
136 };
137
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]138 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]139 compatible = "fsl,imx51-esdhc";
140 reg = <0x70020000 0x4000>;
141 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]142 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
143 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]144 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]145 status = "disabled";
146 };
147
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]148 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]149 compatible = "fsl,imx51-esdhc";
150 reg = <0x70024000 0x4000>;
151 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]152 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
153 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]154 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]155 status = "disabled";
156 };
157 };
158
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]159 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]160 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
161 reg = <0x73f80000 0x0200>;
162 interrupts = <18>;
163 status = "disabled";
164 };
165
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]166 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]167 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
168 reg = <0x73f80200 0x0200>;
169 interrupts = <14>;
170 status = "disabled";
171 };
172
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]173 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]174 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
175 reg = <0x73f80400 0x0200>;
176 interrupts = <16>;
177 status = "disabled";
178 };
179
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]180 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]181 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
182 reg = <0x73f80600 0x0200>;
183 interrupts = <17>;
184 status = "disabled";
185 };
186
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]187 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]188 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]189 reg = <0x73f84000 0x4000>;
190 interrupts = <50 51>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]194 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]195 };
196
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]197 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]198 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]199 reg = <0x73f88000 0x4000>;
200 interrupts = <52 53>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]204 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]205 };
206
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]207 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]208 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]209 reg = <0x73f8c000 0x4000>;
210 interrupts = <54 55>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]214 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]215 };
216
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]217 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]218 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]219 reg = <0x73f90000 0x4000>;
220 interrupts = <56 57>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]224 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]225 };
226
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]227 kpp: kpp@73f94000 {
228 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
229 reg = <0x73f94000 0x4000>;
230 interrupts = <60>;
231 clocks = <&clks 0>;
232 status = "disabled";
233 };
234
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]235 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]236 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
237 reg = <0x73f98000 0x4000>;
238 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]239 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]240 };
241
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]242 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]243 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
244 reg = <0x73f9c000 0x4000>;
245 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]246 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]247 status = "disabled";
248 };
249
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame]250 gpt: timer@73fa0000 {
251 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
252 reg = <0x73fa0000 0x4000>;
253 interrupts = <39>;
254 clocks = <&clks 36>, <&clks 41>;
255 clock-names = "ipg", "per";
256 };
257
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]258 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]259 compatible = "fsl,imx51-iomuxc";
260 reg = <0x73fa8000 0x4000>;
261
262 audmux {
263 pinctrl_audmux_1: audmuxgrp-1 {
264 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]265 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
266 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
267 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
268 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]269 >;
270 };
271 };
272
273 fec {
274 pinctrl_fec_1: fecgrp-1 {
275 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]276 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
277 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
278 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
279 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
280 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
281 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
282 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
283 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
284 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
285 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
286 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
287 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
288 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
289 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
290 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
291 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
292 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]293 >;
294 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]295
296 pinctrl_fec_2: fecgrp-2 {
297 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]298 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
299 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
300 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
301 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
302 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
303 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
304 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
305 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
306 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
307 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
308 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
309 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
310 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
311 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
312 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
313 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
314 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
315 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]316 >;
317 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]318 };
319
320 ecspi1 {
321 pinctrl_ecspi1_1: ecspi1grp-1 {
322 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]323 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
324 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
325 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]326 >;
327 };
328 };
329
Gwenhael Goavec-Meroua15ac4a2013-03-09 14:59:08 +0100[diff] [blame]330 ecspi2 {
331 pinctrl_ecspi2_1: ecspi2grp-1 {
332 fsl,pins = <
333 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
334 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
335 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
336 >;
337 };
338 };
339
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]340 esdhc1 {
341 pinctrl_esdhc1_1: esdhc1grp-1 {
342 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]343 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
344 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
345 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
346 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
347 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
348 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]349 >;
350 };
351 };
352
353 esdhc2 {
354 pinctrl_esdhc2_1: esdhc2grp-1 {
355 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]356 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
357 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
358 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
359 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
360 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
361 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]362 >;
363 };
364 };
365
366 i2c2 {
367 pinctrl_i2c2_1: i2c2grp-1 {
368 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]369 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
370 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]371 >;
372 };
Gwenhael Goavec-Merou52c9aa92013-03-09 15:04:19 +0100[diff] [blame]373
374 pinctrl_i2c2_2: i2c2grp-2 {
375 fsl,pins = <
376 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
377 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
378 >;
379 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]380 };
381
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]382 ipu_disp1 {
383 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
384 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]385 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
386 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
387 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
388 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
389 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
390 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
391 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
392 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
393 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
394 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
395 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
396 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
397 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
398 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
399 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
400 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
401 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
402 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
403 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
404 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
405 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
406 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
407 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
408 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
409 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
410 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]411 >;
412 };
413 };
414
415 ipu_disp2 {
416 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
417 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]418 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
419 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
420 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
421 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
422 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
423 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
424 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
425 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
426 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
427 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
428 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
429 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
430 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
431 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
432 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
433 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
434 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
435 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
436 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
437 MX51_PAD_DI_GP4__DI2_PIN15 0x5
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]438 >;
439 };
440 };
441
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]442 uart1 {
443 pinctrl_uart1_1: uart1grp-1 {
444 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]445 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
446 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
447 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
448 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]449 >;
450 };
451 };
452
453 uart2 {
454 pinctrl_uart2_1: uart2grp-1 {
455 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]456 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
457 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]458 >;
459 };
460 };
461
462 uart3 {
463 pinctrl_uart3_1: uart3grp-1 {
464 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]465 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
466 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
467 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
468 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]469 >;
470 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]471
472 pinctrl_uart3_2: uart3grp-2 {
473 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]474 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
475 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]476 >;
477 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]478 };
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]479
480 kpp {
481 pinctrl_kpp_1: kppgrp-1 {
482 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]483 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
484 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
485 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
486 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
487 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
488 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
489 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
490 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]491 >;
492 };
493 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]494 };
495
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]496 pwm1: pwm@73fb4000 {
497 #pwm-cells = <2>;
498 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
499 reg = <0x73fb4000 0x4000>;
500 clocks = <&clks 37>, <&clks 38>;
501 clock-names = "ipg", "per";
502 interrupts = <61>;
503 };
504
505 pwm2: pwm@73fb8000 {
506 #pwm-cells = <2>;
507 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
508 reg = <0x73fb8000 0x4000>;
509 clocks = <&clks 39>, <&clks 40>;
510 clock-names = "ipg", "per";
511 interrupts = <94>;
512 };
513
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]514 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]515 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
516 reg = <0x73fbc000 0x4000>;
517 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]518 clocks = <&clks 28>, <&clks 29>;
519 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]520 status = "disabled";
521 };
522
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]523 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]524 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
525 reg = <0x73fc0000 0x4000>;
526 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]527 clocks = <&clks 30>, <&clks 31>;
528 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]529 status = "disabled";
530 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]531
532 clks: ccm@73fd4000{
533 compatible = "fsl,imx51-ccm";
534 reg = <0x73fd4000 0x4000>;
535 interrupts = <0 71 0x04 0 72 0x04>;
536 #clock-cells = <1>;
537 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]538 };
539
540 aips@80000000 { /* AIPS2 */
541 compatible = "fsl,aips-bus", "simple-bus";
542 #address-cells = <1>;
543 #size-cells = <1>;
544 reg = <0x80000000 0x10000000>;
545 ranges;
546
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]547 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "fsl,imx51-ecspi";
551 reg = <0x83fac000 0x4000>;
552 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]553 clocks = <&clks 53>, <&clks 54>;
554 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]555 status = "disabled";
556 };
557
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]558 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]559 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
560 reg = <0x83fb0000 0x4000>;
561 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]562 clocks = <&clks 56>, <&clks 56>;
563 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]564 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]565 };
566
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]567 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]568 #address-cells = <1>;
569 #size-cells = <0>;
570 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
571 reg = <0x83fc0000 0x4000>;
572 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]573 clocks = <&clks 55>, <&clks 0>;
574 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]575 status = "disabled";
576 };
577
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]578 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]579 #address-cells = <1>;
580 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]581 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]582 reg = <0x83fc4000 0x4000>;
583 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]584 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]585 status = "disabled";
586 };
587
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]588 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]589 #address-cells = <1>;
590 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]591 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]592 reg = <0x83fc8000 0x4000>;
593 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]594 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]595 status = "disabled";
596 };
597
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]598 ssi1: ssi@83fcc000 {
599 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
600 reg = <0x83fcc000 0x4000>;
601 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]602 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]603 fsl,fifo-depth = <15>;
604 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
605 status = "disabled";
606 };
607
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]608 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]609 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
610 reg = <0x83fd0000 0x4000>;
611 status = "disabled";
612 };
613
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]614 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]615 compatible = "fsl,imx51-nand";
616 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
617 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]618 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]619 status = "disabled";
620 };
621
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]622 ssi3: ssi@83fe8000 {
623 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
624 reg = <0x83fe8000 0x4000>;
625 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]626 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]627 fsl,fifo-depth = <15>;
628 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
629 status = "disabled";
630 };
631
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]632 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]633 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
634 reg = <0x83fec000 0x4000>;
635 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]636 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
637 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]638 status = "disabled";
639 };
640 };
641 };
642};