blob: 87b73e0169c51eb2137d29679ceccbbf179b1568 [file] [log] [blame]
Jan Nikitenko63bd2352007-05-08 00:32:25 -07001/*
2 * au1550_spi.c - au1550 psc spi controller driver
3 * may work also with au1200, au1210, au1250
4 * will not work on au1000, au1100 and au1500 (no full spi controller there)
5 *
6 * Copyright (c) 2006 ATRON electronic GmbH
7 * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/errno.h>
27#include <linux/device.h>
28#include <linux/platform_device.h>
Manuel Lauss3a93a152008-07-23 21:29:56 -070029#include <linux/resource.h>
Jan Nikitenko63bd2352007-05-08 00:32:25 -070030#include <linux/spi/spi.h>
31#include <linux/spi/spi_bitbang.h>
32#include <linux/dma-mapping.h>
33#include <linux/completion.h>
34#include <asm/mach-au1x00/au1000.h>
35#include <asm/mach-au1x00/au1xxx_psc.h>
36#include <asm/mach-au1x00/au1xxx_dbdma.h>
37
38#include <asm/mach-au1x00/au1550_spi.h>
39
40static unsigned usedma = 1;
41module_param(usedma, uint, 0644);
42
43/*
44#define AU1550_SPI_DEBUG_LOOPBACK
45*/
46
47
48#define AU1550_SPI_DBDMA_DESCRIPTORS 1
49#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
50
51struct au1550_spi {
52 struct spi_bitbang bitbang;
53
54 volatile psc_spi_t __iomem *regs;
55 int irq;
56 unsigned freq_max;
57 unsigned freq_min;
58
59 unsigned len;
60 unsigned tx_count;
61 unsigned rx_count;
62 const u8 *tx;
63 u8 *rx;
64
65 void (*rx_word)(struct au1550_spi *hw);
66 void (*tx_word)(struct au1550_spi *hw);
67 int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
68 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
69
70 struct completion master_done;
71
72 unsigned usedma;
73 u32 dma_tx_id;
74 u32 dma_rx_id;
75 u32 dma_tx_ch;
76 u32 dma_rx_ch;
77
78 u8 *dma_rx_tmpbuf;
79 unsigned dma_rx_tmpbuf_size;
80 u32 dma_rx_tmpbuf_addr;
81
82 struct spi_master *master;
83 struct device *dev;
84 struct au1550_spi_info *pdata;
Manuel Lauss3a93a152008-07-23 21:29:56 -070085 struct resource *ioarea;
Jan Nikitenko63bd2352007-05-08 00:32:25 -070086};
87
88
89/* we use an 8-bit memory device for dma transfers to/from spi fifo */
90static dbdev_tab_t au1550_spi_mem_dbdev =
91{
92 .dev_id = DBDMA_MEM_CHAN,
93 .dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
94 .dev_tsize = 0,
95 .dev_devwidth = 8,
96 .dev_physaddr = 0x00000000,
97 .dev_intlevel = 0,
98 .dev_intpolarity = 0
99};
100
Manuel Lauss3a93a152008-07-23 21:29:56 -0700101static int ddma_memid; /* id to above mem dma device */
102
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700103static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
104
105
Jan Nikitenko40369e12008-03-13 12:32:38 -0700106/*
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700107 * compute BRG and DIV bits to setup spi clock based on main input clock rate
108 * that was specified in platform data structure
109 * according to au1550 datasheet:
110 * psc_tempclk = psc_mainclk / (2 << DIV)
111 * spiclk = psc_tempclk / (2 * (BRG + 1))
112 * BRG valid range is 4..63
113 * DIV valid range is 0..3
114 */
115static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
116{
117 u32 mainclk_hz = hw->pdata->mainclk_hz;
118 u32 div, brg;
119
120 for (div = 0; div < 4; div++) {
121 brg = mainclk_hz / speed_hz / (4 << div);
122 /* now we have BRG+1 in brg, so count with that */
123 if (brg < (4 + 1)) {
124 brg = (4 + 1); /* speed_hz too big */
125 break; /* set lowest brg (div is == 0) */
126 }
127 if (brg <= (63 + 1))
128 break; /* we have valid brg and div */
129 }
130 if (div == 4) {
131 div = 3; /* speed_hz too small */
132 brg = (63 + 1); /* set highest brg and div */
133 }
134 brg--;
135 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
136}
137
138static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
139{
140 hw->regs->psc_spimsk =
141 PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144 au_sync();
145
146 hw->regs->psc_spievent =
147 PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150 au_sync();
151}
152
153static void au1550_spi_reset_fifos(struct au1550_spi *hw)
154{
155 u32 pcr;
156
157 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158 au_sync();
159 do {
160 pcr = hw->regs->psc_spipcr;
161 au_sync();
162 } while (pcr != 0);
163}
164
165/*
166 * dma transfers are used for the most common spi word size of 8-bits
167 * we cannot easily change already set up dma channels' width, so if we wanted
168 * dma support for more than 8-bit words (up to 24 bits), we would need to
169 * setup dma channels from scratch on each spi transfer, based on bits_per_word
170 * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
171 * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
172 * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
173 */
174static void au1550_spi_chipsel(struct spi_device *spi, int value)
175{
176 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
177 unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
178 u32 cfg, stat;
179
180 switch (value) {
181 case BITBANG_CS_INACTIVE:
182 if (hw->pdata->deactivate_cs)
183 hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
184 cspol);
185 break;
186
187 case BITBANG_CS_ACTIVE:
188 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189
190 cfg = hw->regs->psc_spicfg;
191 au_sync();
192 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193 au_sync();
194
195 if (spi->mode & SPI_CPOL)
196 cfg |= PSC_SPICFG_BI;
197 else
198 cfg &= ~PSC_SPICFG_BI;
199 if (spi->mode & SPI_CPHA)
200 cfg &= ~PSC_SPICFG_CDE;
201 else
202 cfg |= PSC_SPICFG_CDE;
203
204 if (spi->mode & SPI_LSB_FIRST)
205 cfg |= PSC_SPICFG_MLF;
206 else
207 cfg &= ~PSC_SPICFG_MLF;
208
209 if (hw->usedma && spi->bits_per_word <= 8)
210 cfg &= ~PSC_SPICFG_DD_DISABLE;
211 else
212 cfg |= PSC_SPICFG_DD_DISABLE;
213 cfg = PSC_SPICFG_CLR_LEN(cfg);
214 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
215
216 cfg = PSC_SPICFG_CLR_BAUD(cfg);
217 cfg &= ~PSC_SPICFG_SET_DIV(3);
218 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219
220 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221 au_sync();
222 do {
223 stat = hw->regs->psc_spistat;
224 au_sync();
225 } while ((stat & PSC_SPISTAT_DR) == 0);
226
227 if (hw->pdata->activate_cs)
228 hw->pdata->activate_cs(hw->pdata, spi->chip_select,
229 cspol);
230 break;
231 }
232}
233
234static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
235{
236 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
237 unsigned bpw, hz;
238 u32 cfg, stat;
239
240 bpw = t ? t->bits_per_word : spi->bits_per_word;
241 hz = t ? t->speed_hz : spi->max_speed_hz;
242
243 if (bpw < 4 || bpw > 24) {
244 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
245 bpw);
246 return -EINVAL;
247 }
248 if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
249 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
250 hz);
251 return -EINVAL;
252 }
253
254 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
255
256 cfg = hw->regs->psc_spicfg;
257 au_sync();
258 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
259 au_sync();
260
261 if (hw->usedma && bpw <= 8)
262 cfg &= ~PSC_SPICFG_DD_DISABLE;
263 else
264 cfg |= PSC_SPICFG_DD_DISABLE;
265 cfg = PSC_SPICFG_CLR_LEN(cfg);
266 cfg |= PSC_SPICFG_SET_LEN(bpw);
267
268 cfg = PSC_SPICFG_CLR_BAUD(cfg);
269 cfg &= ~PSC_SPICFG_SET_DIV(3);
270 cfg |= au1550_spi_baudcfg(hw, hz);
271
272 hw->regs->psc_spicfg = cfg;
273 au_sync();
274
275 if (cfg & PSC_SPICFG_DE_ENABLE) {
276 do {
277 stat = hw->regs->psc_spistat;
278 au_sync();
279 } while ((stat & PSC_SPISTAT_DR) == 0);
280 }
281
282 au1550_spi_reset_fifos(hw);
283 au1550_spi_mask_ack_all(hw);
284 return 0;
285}
286
David Brownelldccd5732007-07-17 04:04:02 -0700287/* the spi->mode bits understood by this driver: */
288#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
289
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700290static int au1550_spi_setup(struct spi_device *spi)
291{
292 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
293
294 if (spi->bits_per_word == 0)
295 spi->bits_per_word = 8;
296 if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
297 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
298 spi->bits_per_word);
299 return -EINVAL;
300 }
301
David Brownelldccd5732007-07-17 04:04:02 -0700302 if (spi->mode & ~MODEBITS) {
303 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
304 spi->mode & ~MODEBITS);
305 return -EINVAL;
306 }
307
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700308 if (spi->max_speed_hz == 0)
309 spi->max_speed_hz = hw->freq_max;
310 if (spi->max_speed_hz > hw->freq_max
311 || spi->max_speed_hz < hw->freq_min)
312 return -EINVAL;
313 /*
314 * NOTE: cannot change speed and other hw settings immediately,
315 * otherwise sharing of spi bus is not possible,
316 * so do not call setupxfer(spi, NULL) here
317 */
318 return 0;
319}
320
321/*
322 * for dma spi transfers, we have to setup rx channel, otherwise there is
323 * no reliable way how to recognize that spi transfer is done
324 * dma complete callbacks are called before real spi transfer is finished
325 * and if only tx dma channel is set up (and rx fifo overflow event masked)
326 * spi master done event irq is not generated unless rx fifo is empty (emptied)
327 * so we need rx tmp buffer to use for rx dma if user does not provide one
328 */
329static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
330{
331 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
332 if (!hw->dma_rx_tmpbuf)
333 return -ENOMEM;
334 hw->dma_rx_tmpbuf_size = size;
335 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
336 size, DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700337 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700338 kfree(hw->dma_rx_tmpbuf);
339 hw->dma_rx_tmpbuf = 0;
340 hw->dma_rx_tmpbuf_size = 0;
341 return -EFAULT;
342 }
343 return 0;
344}
345
346static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
347{
348 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
349 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
350 kfree(hw->dma_rx_tmpbuf);
351 hw->dma_rx_tmpbuf = 0;
352 hw->dma_rx_tmpbuf_size = 0;
353}
354
355static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
356{
357 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
358 dma_addr_t dma_tx_addr;
359 dma_addr_t dma_rx_addr;
360 u32 res;
361
362 hw->len = t->len;
363 hw->tx_count = 0;
364 hw->rx_count = 0;
365
366 hw->tx = t->tx_buf;
367 hw->rx = t->rx_buf;
368 dma_tx_addr = t->tx_dma;
369 dma_rx_addr = t->rx_dma;
370
371 /*
372 * check if buffers are already dma mapped, map them otherwise
373 * use rx buffer in place of tx if tx buffer was not provided
374 * use temp rx buffer (preallocated or realloc to fit) for rx dma
375 */
376 if (t->rx_buf) {
377 if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
378 dma_rx_addr = dma_map_single(hw->dev,
379 (void *)t->rx_buf,
380 t->len, DMA_FROM_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700381 if (dma_mapping_error(hw->dev, dma_rx_addr))
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700382 dev_err(hw->dev, "rx dma map error\n");
383 }
384 } else {
385 if (t->len > hw->dma_rx_tmpbuf_size) {
386 int ret;
387
388 au1550_spi_dma_rxtmp_free(hw);
389 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
390 AU1550_SPI_DMA_RXTMP_MINSIZE));
391 if (ret < 0)
392 return ret;
393 }
394 hw->rx = hw->dma_rx_tmpbuf;
395 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
396 dma_sync_single_for_device(hw->dev, dma_rx_addr,
397 t->len, DMA_FROM_DEVICE);
398 }
399 if (t->tx_buf) {
400 if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
401 dma_tx_addr = dma_map_single(hw->dev,
402 (void *)t->tx_buf,
403 t->len, DMA_TO_DEVICE);
FUJITA Tomonori8d8bb392008-07-25 19:44:49 -0700404 if (dma_mapping_error(hw->dev, dma_tx_addr))
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700405 dev_err(hw->dev, "tx dma map error\n");
406 }
407 } else {
408 dma_sync_single_for_device(hw->dev, dma_rx_addr,
409 t->len, DMA_BIDIRECTIONAL);
410 hw->tx = hw->rx;
411 }
412
413 /* put buffers on the ring */
414 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
415 if (!res)
416 dev_err(hw->dev, "rx dma put dest error\n");
417
418 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
419 if (!res)
420 dev_err(hw->dev, "tx dma put source error\n");
421
422 au1xxx_dbdma_start(hw->dma_rx_ch);
423 au1xxx_dbdma_start(hw->dma_tx_ch);
424
425 /* by default enable nearly all events interrupt */
426 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
427 au_sync();
428
429 /* start the transfer */
430 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
431 au_sync();
432
433 wait_for_completion(&hw->master_done);
434
435 au1xxx_dbdma_stop(hw->dma_tx_ch);
436 au1xxx_dbdma_stop(hw->dma_rx_ch);
437
438 if (!t->rx_buf) {
439 /* using the temporal preallocated and premapped buffer */
440 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
441 DMA_FROM_DEVICE);
442 }
443 /* unmap buffers if mapped above */
444 if (t->rx_buf && t->rx_dma == 0 )
445 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
446 DMA_FROM_DEVICE);
447 if (t->tx_buf && t->tx_dma == 0 )
448 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
449 DMA_TO_DEVICE);
450
451 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
452}
453
454static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
455{
456 u32 stat, evnt;
457
458 stat = hw->regs->psc_spistat;
459 evnt = hw->regs->psc_spievent;
460 au_sync();
461 if ((stat & PSC_SPISTAT_DI) == 0) {
462 dev_err(hw->dev, "Unexpected IRQ!\n");
463 return IRQ_NONE;
464 }
465
466 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
467 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
468 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
469 != 0) {
470 /*
471 * due to an spi error we consider transfer as done,
472 * so mask all events until before next transfer start
473 * and stop the possibly running dma immediatelly
474 */
475 au1550_spi_mask_ack_all(hw);
476 au1xxx_dbdma_stop(hw->dma_rx_ch);
477 au1xxx_dbdma_stop(hw->dma_tx_ch);
478
479 /* get number of transfered bytes */
480 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
481 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
482
483 au1xxx_dbdma_reset(hw->dma_rx_ch);
484 au1xxx_dbdma_reset(hw->dma_tx_ch);
485 au1550_spi_reset_fifos(hw);
486
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700487 if (evnt == PSC_SPIEVNT_RO)
488 dev_err(hw->dev,
489 "dma transfer: receive FIFO overflow!\n");
490 else
491 dev_err(hw->dev,
492 "dma transfer: unexpected SPI error "
493 "(event=0x%x stat=0x%x)!\n", evnt, stat);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700494
495 complete(&hw->master_done);
496 return IRQ_HANDLED;
497 }
498
499 if ((evnt & PSC_SPIEVNT_MD) != 0) {
500 /* transfer completed successfully */
501 au1550_spi_mask_ack_all(hw);
502 hw->rx_count = hw->len;
503 hw->tx_count = hw->len;
504 complete(&hw->master_done);
505 }
506 return IRQ_HANDLED;
507}
508
509
510/* routines to handle different word sizes in pio mode */
511#define AU1550_SPI_RX_WORD(size, mask) \
512static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
513{ \
514 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
515 au_sync(); \
516 if (hw->rx) { \
517 *(u##size *)hw->rx = (u##size)fifoword; \
518 hw->rx += (size) / 8; \
519 } \
520 hw->rx_count += (size) / 8; \
521}
522
523#define AU1550_SPI_TX_WORD(size, mask) \
524static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
525{ \
526 u32 fifoword = 0; \
527 if (hw->tx) { \
528 fifoword = *(u##size *)hw->tx & (u32)(mask); \
529 hw->tx += (size) / 8; \
530 } \
531 hw->tx_count += (size) / 8; \
532 if (hw->tx_count >= hw->len) \
533 fifoword |= PSC_SPITXRX_LC; \
534 hw->regs->psc_spitxrx = fifoword; \
535 au_sync(); \
536}
537
538AU1550_SPI_RX_WORD(8,0xff)
539AU1550_SPI_RX_WORD(16,0xffff)
540AU1550_SPI_RX_WORD(32,0xffffff)
541AU1550_SPI_TX_WORD(8,0xff)
542AU1550_SPI_TX_WORD(16,0xffff)
543AU1550_SPI_TX_WORD(32,0xffffff)
544
545static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
546{
547 u32 stat, mask;
548 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
549
550 hw->tx = t->tx_buf;
551 hw->rx = t->rx_buf;
552 hw->len = t->len;
553 hw->tx_count = 0;
554 hw->rx_count = 0;
555
556 /* by default enable nearly all events after filling tx fifo */
557 mask = PSC_SPIMSK_SD;
558
559 /* fill the transmit FIFO */
560 while (hw->tx_count < hw->len) {
561
562 hw->tx_word(hw);
563
564 if (hw->tx_count >= hw->len) {
565 /* mask tx fifo request interrupt as we are done */
566 mask |= PSC_SPIMSK_TR;
567 }
568
569 stat = hw->regs->psc_spistat;
570 au_sync();
571 if (stat & PSC_SPISTAT_TF)
572 break;
573 }
574
575 /* enable event interrupts */
576 hw->regs->psc_spimsk = mask;
577 au_sync();
578
579 /* start the transfer */
580 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
581 au_sync();
582
583 wait_for_completion(&hw->master_done);
584
585 return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
586}
587
588static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
589{
590 int busy;
591 u32 stat, evnt;
592
593 stat = hw->regs->psc_spistat;
594 evnt = hw->regs->psc_spievent;
595 au_sync();
596 if ((stat & PSC_SPISTAT_DI) == 0) {
597 dev_err(hw->dev, "Unexpected IRQ!\n");
598 return IRQ_NONE;
599 }
600
601 if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
602 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700603 | PSC_SPIEVNT_SD))
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700604 != 0) {
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700605 /*
606 * due to an error we consider transfer as done,
607 * so mask all events until before next transfer start
608 */
609 au1550_spi_mask_ack_all(hw);
610 au1550_spi_reset_fifos(hw);
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700611 dev_err(hw->dev,
612 "pio transfer: unexpected SPI error "
613 "(event=0x%x stat=0x%x)!\n", evnt, stat);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700614 complete(&hw->master_done);
615 return IRQ_HANDLED;
616 }
617
618 /*
619 * while there is something to read from rx fifo
620 * or there is a space to write to tx fifo:
621 */
622 do {
623 busy = 0;
624 stat = hw->regs->psc_spistat;
625 au_sync();
626
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700627 /*
628 * Take care to not let the Rx FIFO overflow.
629 *
630 * We only write a byte if we have read one at least. Initially,
631 * the write fifo is full, so we should read from the read fifo
632 * first.
633 * In case we miss a word from the read fifo, we should get a
634 * RO event and should back out.
635 */
636 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700637 hw->rx_word(hw);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700638 busy = 1;
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700639
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700640 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
641 hw->tx_word(hw);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700642 }
643 } while (busy);
644
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700645 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700646 au_sync();
647
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700648 /*
649 * Restart the SPI transmission in case of a transmit underflow.
650 * This seems to work despite the notes in the Au1550 data book
651 * of Figure 8-4 with flowchart for SPI master operation:
652 *
653 * """Note 1: An XFR Error Interrupt occurs, unless masked,
654 * for any of the following events: Tx FIFO Underflow,
655 * Rx FIFO Overflow, or Multiple-master Error
656 * Note 2: In case of a Tx Underflow Error, all zeroes are
657 * transmitted."""
658 *
659 * By simply restarting the spi transfer on Tx Underflow Error,
660 * we assume that spi transfer was paused instead of zeroes
661 * transmittion mentioned in the Note 2 of Au1550 data book.
662 */
663 if (evnt & PSC_SPIEVNT_TU) {
664 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
665 au_sync();
666 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
667 au_sync();
668 }
669
670 if (hw->rx_count >= hw->len) {
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700671 /* transfer completed successfully */
672 au1550_spi_mask_ack_all(hw);
673 complete(&hw->master_done);
674 }
675 return IRQ_HANDLED;
676}
677
678static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
679{
680 struct au1550_spi *hw = spi_master_get_devdata(spi->master);
681 return hw->txrx_bufs(spi, t);
682}
683
Jan Nikitenko40369e12008-03-13 12:32:38 -0700684static irqreturn_t au1550_spi_irq(int irq, void *dev)
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700685{
686 struct au1550_spi *hw = dev;
687 return hw->irq_callback(hw);
688}
689
690static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
691{
692 if (bpw <= 8) {
693 if (hw->usedma) {
694 hw->txrx_bufs = &au1550_spi_dma_txrxb;
695 hw->irq_callback = &au1550_spi_dma_irq_callback;
696 } else {
697 hw->rx_word = &au1550_spi_rx_word_8;
698 hw->tx_word = &au1550_spi_tx_word_8;
699 hw->txrx_bufs = &au1550_spi_pio_txrxb;
700 hw->irq_callback = &au1550_spi_pio_irq_callback;
701 }
702 } else if (bpw <= 16) {
703 hw->rx_word = &au1550_spi_rx_word_16;
704 hw->tx_word = &au1550_spi_tx_word_16;
705 hw->txrx_bufs = &au1550_spi_pio_txrxb;
706 hw->irq_callback = &au1550_spi_pio_irq_callback;
707 } else {
708 hw->rx_word = &au1550_spi_rx_word_32;
709 hw->tx_word = &au1550_spi_tx_word_32;
710 hw->txrx_bufs = &au1550_spi_pio_txrxb;
711 hw->irq_callback = &au1550_spi_pio_irq_callback;
712 }
713}
714
715static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
716{
717 u32 stat, cfg;
718
719 /* set up the PSC for SPI mode */
720 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
721 au_sync();
722 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
723 au_sync();
724
725 hw->regs->psc_spicfg = 0;
726 au_sync();
727
728 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
729 au_sync();
730
731 do {
732 stat = hw->regs->psc_spistat;
733 au_sync();
734 } while ((stat & PSC_SPISTAT_SR) == 0);
735
736
737 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
738 cfg |= PSC_SPICFG_SET_LEN(8);
739 cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
740 /* use minimal allowed brg and div values as initial setting: */
741 cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
742
743#ifdef AU1550_SPI_DEBUG_LOOPBACK
744 cfg |= PSC_SPICFG_LB;
745#endif
746
747 hw->regs->psc_spicfg = cfg;
748 au_sync();
749
750 au1550_spi_mask_ack_all(hw);
751
752 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
753 au_sync();
754
755 do {
756 stat = hw->regs->psc_spistat;
757 au_sync();
758 } while ((stat & PSC_SPISTAT_DR) == 0);
Jan Nikitenkobbe48ec2008-07-23 21:29:57 -0700759
760 au1550_spi_reset_fifos(hw);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700761}
762
763
764static int __init au1550_spi_probe(struct platform_device *pdev)
765{
766 struct au1550_spi *hw;
767 struct spi_master *master;
Manuel Lauss3a93a152008-07-23 21:29:56 -0700768 struct resource *r;
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700769 int err = 0;
770
771 master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
772 if (master == NULL) {
773 dev_err(&pdev->dev, "No memory for spi_master\n");
774 err = -ENOMEM;
775 goto err_nomem;
776 }
777
778 hw = spi_master_get_devdata(master);
779
780 hw->master = spi_master_get(master);
781 hw->pdata = pdev->dev.platform_data;
782 hw->dev = &pdev->dev;
783
784 if (hw->pdata == NULL) {
785 dev_err(&pdev->dev, "No platform data supplied\n");
786 err = -ENOENT;
787 goto err_no_pdata;
788 }
789
Manuel Lauss3a93a152008-07-23 21:29:56 -0700790 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
791 if (!r) {
792 dev_err(&pdev->dev, "no IRQ\n");
793 err = -ENODEV;
794 goto err_no_iores;
795 }
796 hw->irq = r->start;
797
798 hw->usedma = 0;
799 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
800 if (r) {
801 hw->dma_tx_id = r->start;
802 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
803 if (r) {
804 hw->dma_rx_id = r->start;
805 if (usedma && ddma_memid) {
806 if (pdev->dev.dma_mask == NULL)
807 dev_warn(&pdev->dev, "no dma mask\n");
808 else
809 hw->usedma = 1;
810 }
811 }
812 }
813
814 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 if (!r) {
816 dev_err(&pdev->dev, "no mmio resource\n");
817 err = -ENODEV;
818 goto err_no_iores;
819 }
820
821 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
822 pdev->name);
823 if (!hw->ioarea) {
824 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
825 err = -ENXIO;
826 goto err_no_iores;
827 }
828
829 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
830 if (!hw->regs) {
831 dev_err(&pdev->dev, "cannot ioremap\n");
832 err = -ENXIO;
833 goto err_ioremap;
834 }
835
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700836 platform_set_drvdata(pdev, hw);
837
838 init_completion(&hw->master_done);
839
840 hw->bitbang.master = hw->master;
841 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
842 hw->bitbang.chipselect = au1550_spi_chipsel;
843 hw->bitbang.master->setup = au1550_spi_setup;
844 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
845
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700846 if (hw->usedma) {
Manuel Lauss3a93a152008-07-23 21:29:56 -0700847 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700848 hw->dma_tx_id, NULL, (void *)hw);
849 if (hw->dma_tx_ch == 0) {
850 dev_err(&pdev->dev,
851 "Cannot allocate tx dma channel\n");
852 err = -ENXIO;
853 goto err_no_txdma;
854 }
855 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
856 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
857 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
858 dev_err(&pdev->dev,
859 "Cannot allocate tx dma descriptors\n");
860 err = -ENXIO;
861 goto err_no_txdma_descr;
862 }
863
864
865 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
Manuel Lauss3a93a152008-07-23 21:29:56 -0700866 ddma_memid, NULL, (void *)hw);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700867 if (hw->dma_rx_ch == 0) {
868 dev_err(&pdev->dev,
869 "Cannot allocate rx dma channel\n");
870 err = -ENXIO;
871 goto err_no_rxdma;
872 }
873 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
874 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
875 AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
876 dev_err(&pdev->dev,
877 "Cannot allocate rx dma descriptors\n");
878 err = -ENXIO;
879 goto err_no_rxdma_descr;
880 }
881
882 err = au1550_spi_dma_rxtmp_alloc(hw,
883 AU1550_SPI_DMA_RXTMP_MINSIZE);
884 if (err < 0) {
885 dev_err(&pdev->dev,
886 "Cannot allocate initial rx dma tmp buffer\n");
887 goto err_dma_rxtmp_alloc;
888 }
889 }
890
891 au1550_spi_bits_handlers_set(hw, 8);
892
893 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
894 if (err) {
895 dev_err(&pdev->dev, "Cannot claim IRQ\n");
896 goto err_no_irq;
897 }
898
Manuel Lauss3a93a152008-07-23 21:29:56 -0700899 master->bus_num = pdev->id;
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700900 master->num_chipselect = hw->pdata->num_chipselect;
901
902 /*
903 * precompute valid range for spi freq - from au1550 datasheet:
904 * psc_tempclk = psc_mainclk / (2 << DIV)
905 * spiclk = psc_tempclk / (2 * (BRG + 1))
906 * BRG valid range is 4..63
907 * DIV valid range is 0..3
908 * round the min and max frequencies to values that would still
909 * produce valid brg and div
910 */
911 {
912 int min_div = (2 << 0) * (2 * (4 + 1));
913 int max_div = (2 << 3) * (2 * (63 + 1));
914 hw->freq_max = hw->pdata->mainclk_hz / min_div;
915 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
916 }
917
918 au1550_spi_setup_psc_as_spi(hw);
919
920 err = spi_bitbang_start(&hw->bitbang);
921 if (err) {
922 dev_err(&pdev->dev, "Failed to register SPI master\n");
923 goto err_register;
924 }
925
926 dev_info(&pdev->dev,
927 "spi master registered: bus_num=%d num_chipselect=%d\n",
928 master->bus_num, master->num_chipselect);
929
930 return 0;
931
932err_register:
933 free_irq(hw->irq, hw);
934
935err_no_irq:
936 au1550_spi_dma_rxtmp_free(hw);
937
938err_dma_rxtmp_alloc:
939err_no_rxdma_descr:
940 if (hw->usedma)
941 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
942
943err_no_rxdma:
944err_no_txdma_descr:
945 if (hw->usedma)
946 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
947
948err_no_txdma:
Manuel Lauss3a93a152008-07-23 21:29:56 -0700949 iounmap((void __iomem *)hw->regs);
950
951err_ioremap:
952 release_resource(hw->ioarea);
953 kfree(hw->ioarea);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700954
955err_no_iores:
956err_no_pdata:
957 spi_master_put(hw->master);
958
959err_nomem:
960 return err;
961}
962
963static int __exit au1550_spi_remove(struct platform_device *pdev)
964{
965 struct au1550_spi *hw = platform_get_drvdata(pdev);
966
967 dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
968 hw->master->bus_num);
969
970 spi_bitbang_stop(&hw->bitbang);
971 free_irq(hw->irq, hw);
Manuel Lauss3a93a152008-07-23 21:29:56 -0700972 iounmap((void __iomem *)hw->regs);
973 release_resource(hw->ioarea);
974 kfree(hw->ioarea);
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700975
976 if (hw->usedma) {
977 au1550_spi_dma_rxtmp_free(hw);
978 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
979 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
980 }
981
982 platform_set_drvdata(pdev, NULL);
983
984 spi_master_put(hw->master);
985 return 0;
986}
987
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700988/* work with hotplug and coldplug */
989MODULE_ALIAS("platform:au1550-spi");
990
Jan Nikitenko63bd2352007-05-08 00:32:25 -0700991static struct platform_driver au1550_spi_drv = {
992 .remove = __exit_p(au1550_spi_remove),
993 .driver = {
994 .name = "au1550-spi",
995 .owner = THIS_MODULE,
996 },
997};
998
999static int __init au1550_spi_init(void)
1000{
Manuel Lauss3a93a152008-07-23 21:29:56 -07001001 /*
1002 * create memory device with 8 bits dev_devwidth
1003 * needed for proper byte ordering to spi fifo
1004 */
1005 if (usedma) {
1006 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1007 if (!ddma_memid)
1008 printk(KERN_ERR "au1550-spi: cannot add memory"
1009 "dbdma device\n");
1010 }
Jan Nikitenko63bd2352007-05-08 00:32:25 -07001011 return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
1012}
1013module_init(au1550_spi_init);
1014
1015static void __exit au1550_spi_exit(void)
1016{
Manuel Lauss3a93a152008-07-23 21:29:56 -07001017 if (usedma && ddma_memid)
1018 au1xxx_ddma_del_device(ddma_memid);
Jan Nikitenko63bd2352007-05-08 00:32:25 -07001019 platform_driver_unregister(&au1550_spi_drv);
1020}
1021module_exit(au1550_spi_exit);
1022
1023MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1024MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1025MODULE_LICENSE("GPL");