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gerrit-public.fairphone.software / kernel / msm-4.19 / 8dbcc432c2b4adf4ff7183afc5f2b42276b2a987 / . / sound / soc / codecs / max98088.c
blob: 6447dbb2f1238f1288c6ed6a797757a08ddd69fa [file] [log] [blame]
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1/*
2 * max98088.c -- MAX98088 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include <sound/soc-dapm.h>
24#include <sound/initval.h>
25#include <sound/tlv.h>
26#include <linux/slab.h>
27#include <asm/div64.h>
28#include <sound/max98088.h>
29#include "max98088.h"
30
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]31enum max98088_type {
32 MAX98088,
33 MAX98089,
34};
35
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]36struct max98088_cdata {
37 unsigned int rate;
38 unsigned int fmt;
39 int eq_sel;
40};
41
42struct max98088_priv {
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]43 enum max98088_type devtype;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]44 void *control_data;
45 struct max98088_pdata *pdata;
46 unsigned int sysclk;
47 struct max98088_cdata dai[2];
48 int eq_textcnt;
49 const char **eq_texts;
50 struct soc_enum eq_enum;
51 u8 ina_state;
52 u8 inb_state;
53 unsigned int ex_mode;
54 unsigned int digmic;
55 unsigned int mic1pre;
56 unsigned int mic2pre;
57 unsigned int extmic_mode;
58};
59
60static const u8 max98088_reg[M98088_REG_CNT] = {
61 0x00, /* 00 IRQ status */
62 0x00, /* 01 MIC status */
63 0x00, /* 02 jack status */
64 0x00, /* 03 battery voltage */
65 0x00, /* 04 */
66 0x00, /* 05 */
67 0x00, /* 06 */
68 0x00, /* 07 */
69 0x00, /* 08 */
70 0x00, /* 09 */
71 0x00, /* 0A */
72 0x00, /* 0B */
73 0x00, /* 0C */
74 0x00, /* 0D */
75 0x00, /* 0E */
76 0x00, /* 0F interrupt enable */
77
78 0x00, /* 10 master clock */
79 0x00, /* 11 DAI1 clock mode */
80 0x00, /* 12 DAI1 clock control */
81 0x00, /* 13 DAI1 clock control */
82 0x00, /* 14 DAI1 format */
83 0x00, /* 15 DAI1 clock */
84 0x00, /* 16 DAI1 config */
85 0x00, /* 17 DAI1 TDM */
86 0x00, /* 18 DAI1 filters */
87 0x00, /* 19 DAI2 clock mode */
88 0x00, /* 1A DAI2 clock control */
89 0x00, /* 1B DAI2 clock control */
90 0x00, /* 1C DAI2 format */
91 0x00, /* 1D DAI2 clock */
92 0x00, /* 1E DAI2 config */
93 0x00, /* 1F DAI2 TDM */
94
95 0x00, /* 20 DAI2 filters */
96 0x00, /* 21 data config */
97 0x00, /* 22 DAC mixer */
98 0x00, /* 23 left ADC mixer */
99 0x00, /* 24 right ADC mixer */
100 0x00, /* 25 left HP mixer */
101 0x00, /* 26 right HP mixer */
102 0x00, /* 27 HP control */
103 0x00, /* 28 left REC mixer */
104 0x00, /* 29 right REC mixer */
105 0x00, /* 2A REC control */
106 0x00, /* 2B left SPK mixer */
107 0x00, /* 2C right SPK mixer */
108 0x00, /* 2D SPK control */
109 0x00, /* 2E sidetone */
110 0x00, /* 2F DAI1 playback level */
111
112 0x00, /* 30 DAI1 playback level */
113 0x00, /* 31 DAI2 playback level */
114 0x00, /* 32 DAI2 playbakc level */
115 0x00, /* 33 left ADC level */
116 0x00, /* 34 right ADC level */
117 0x00, /* 35 MIC1 level */
118 0x00, /* 36 MIC2 level */
119 0x00, /* 37 INA level */
120 0x00, /* 38 INB level */
121 0x00, /* 39 left HP volume */
122 0x00, /* 3A right HP volume */
123 0x00, /* 3B left REC volume */
124 0x00, /* 3C right REC volume */
125 0x00, /* 3D left SPK volume */
126 0x00, /* 3E right SPK volume */
127 0x00, /* 3F MIC config */
128
129 0x00, /* 40 MIC threshold */
130 0x00, /* 41 excursion limiter filter */
131 0x00, /* 42 excursion limiter threshold */
132 0x00, /* 43 ALC */
133 0x00, /* 44 power limiter threshold */
134 0x00, /* 45 power limiter config */
135 0x00, /* 46 distortion limiter config */
136 0x00, /* 47 audio input */
137 0x00, /* 48 microphone */
138 0x00, /* 49 level control */
139 0x00, /* 4A bypass switches */
140 0x00, /* 4B jack detect */
141 0x00, /* 4C input enable */
142 0x00, /* 4D output enable */
143 0xF0, /* 4E bias control */
144 0x00, /* 4F DAC power */
145
146 0x0F, /* 50 DAC power */
147 0x00, /* 51 system */
148 0x00, /* 52 DAI1 EQ1 */
149 0x00, /* 53 DAI1 EQ1 */
150 0x00, /* 54 DAI1 EQ1 */
151 0x00, /* 55 DAI1 EQ1 */
152 0x00, /* 56 DAI1 EQ1 */
153 0x00, /* 57 DAI1 EQ1 */
154 0x00, /* 58 DAI1 EQ1 */
155 0x00, /* 59 DAI1 EQ1 */
156 0x00, /* 5A DAI1 EQ1 */
157 0x00, /* 5B DAI1 EQ1 */
158 0x00, /* 5C DAI1 EQ2 */
159 0x00, /* 5D DAI1 EQ2 */
160 0x00, /* 5E DAI1 EQ2 */
161 0x00, /* 5F DAI1 EQ2 */
162
163 0x00, /* 60 DAI1 EQ2 */
164 0x00, /* 61 DAI1 EQ2 */
165 0x00, /* 62 DAI1 EQ2 */
166 0x00, /* 63 DAI1 EQ2 */
167 0x00, /* 64 DAI1 EQ2 */
168 0x00, /* 65 DAI1 EQ2 */
169 0x00, /* 66 DAI1 EQ3 */
170 0x00, /* 67 DAI1 EQ3 */
171 0x00, /* 68 DAI1 EQ3 */
172 0x00, /* 69 DAI1 EQ3 */
173 0x00, /* 6A DAI1 EQ3 */
174 0x00, /* 6B DAI1 EQ3 */
175 0x00, /* 6C DAI1 EQ3 */
176 0x00, /* 6D DAI1 EQ3 */
177 0x00, /* 6E DAI1 EQ3 */
178 0x00, /* 6F DAI1 EQ3 */
179
180 0x00, /* 70 DAI1 EQ4 */
181 0x00, /* 71 DAI1 EQ4 */
182 0x00, /* 72 DAI1 EQ4 */
183 0x00, /* 73 DAI1 EQ4 */
184 0x00, /* 74 DAI1 EQ4 */
185 0x00, /* 75 DAI1 EQ4 */
186 0x00, /* 76 DAI1 EQ4 */
187 0x00, /* 77 DAI1 EQ4 */
188 0x00, /* 78 DAI1 EQ4 */
189 0x00, /* 79 DAI1 EQ4 */
190 0x00, /* 7A DAI1 EQ5 */
191 0x00, /* 7B DAI1 EQ5 */
192 0x00, /* 7C DAI1 EQ5 */
193 0x00, /* 7D DAI1 EQ5 */
194 0x00, /* 7E DAI1 EQ5 */
195 0x00, /* 7F DAI1 EQ5 */
196
197 0x00, /* 80 DAI1 EQ5 */
198 0x00, /* 81 DAI1 EQ5 */
199 0x00, /* 82 DAI1 EQ5 */
200 0x00, /* 83 DAI1 EQ5 */
201 0x00, /* 84 DAI2 EQ1 */
202 0x00, /* 85 DAI2 EQ1 */
203 0x00, /* 86 DAI2 EQ1 */
204 0x00, /* 87 DAI2 EQ1 */
205 0x00, /* 88 DAI2 EQ1 */
206 0x00, /* 89 DAI2 EQ1 */
207 0x00, /* 8A DAI2 EQ1 */
208 0x00, /* 8B DAI2 EQ1 */
209 0x00, /* 8C DAI2 EQ1 */
210 0x00, /* 8D DAI2 EQ1 */
211 0x00, /* 8E DAI2 EQ2 */
212 0x00, /* 8F DAI2 EQ2 */
213
214 0x00, /* 90 DAI2 EQ2 */
215 0x00, /* 91 DAI2 EQ2 */
216 0x00, /* 92 DAI2 EQ2 */
217 0x00, /* 93 DAI2 EQ2 */
218 0x00, /* 94 DAI2 EQ2 */
219 0x00, /* 95 DAI2 EQ2 */
220 0x00, /* 96 DAI2 EQ2 */
221 0x00, /* 97 DAI2 EQ2 */
222 0x00, /* 98 DAI2 EQ3 */
223 0x00, /* 99 DAI2 EQ3 */
224 0x00, /* 9A DAI2 EQ3 */
225 0x00, /* 9B DAI2 EQ3 */
226 0x00, /* 9C DAI2 EQ3 */
227 0x00, /* 9D DAI2 EQ3 */
228 0x00, /* 9E DAI2 EQ3 */
229 0x00, /* 9F DAI2 EQ3 */
230
231 0x00, /* A0 DAI2 EQ3 */
232 0x00, /* A1 DAI2 EQ3 */
233 0x00, /* A2 DAI2 EQ4 */
234 0x00, /* A3 DAI2 EQ4 */
235 0x00, /* A4 DAI2 EQ4 */
236 0x00, /* A5 DAI2 EQ4 */
237 0x00, /* A6 DAI2 EQ4 */
238 0x00, /* A7 DAI2 EQ4 */
239 0x00, /* A8 DAI2 EQ4 */
240 0x00, /* A9 DAI2 EQ4 */
241 0x00, /* AA DAI2 EQ4 */
242 0x00, /* AB DAI2 EQ4 */
243 0x00, /* AC DAI2 EQ5 */
244 0x00, /* AD DAI2 EQ5 */
245 0x00, /* AE DAI2 EQ5 */
246 0x00, /* AF DAI2 EQ5 */
247
248 0x00, /* B0 DAI2 EQ5 */
249 0x00, /* B1 DAI2 EQ5 */
250 0x00, /* B2 DAI2 EQ5 */
251 0x00, /* B3 DAI2 EQ5 */
252 0x00, /* B4 DAI2 EQ5 */
253 0x00, /* B5 DAI2 EQ5 */
254 0x00, /* B6 DAI1 biquad */
255 0x00, /* B7 DAI1 biquad */
256 0x00, /* B8 DAI1 biquad */
257 0x00, /* B9 DAI1 biquad */
258 0x00, /* BA DAI1 biquad */
259 0x00, /* BB DAI1 biquad */
260 0x00, /* BC DAI1 biquad */
261 0x00, /* BD DAI1 biquad */
262 0x00, /* BE DAI1 biquad */
263 0x00, /* BF DAI1 biquad */
264
265 0x00, /* C0 DAI2 biquad */
266 0x00, /* C1 DAI2 biquad */
267 0x00, /* C2 DAI2 biquad */
268 0x00, /* C3 DAI2 biquad */
269 0x00, /* C4 DAI2 biquad */
270 0x00, /* C5 DAI2 biquad */
271 0x00, /* C6 DAI2 biquad */
272 0x00, /* C7 DAI2 biquad */
273 0x00, /* C8 DAI2 biquad */
274 0x00, /* C9 DAI2 biquad */
275 0x00, /* CA */
276 0x00, /* CB */
277 0x00, /* CC */
278 0x00, /* CD */
279 0x00, /* CE */
280 0x00, /* CF */
281
282 0x00, /* D0 */
283 0x00, /* D1 */
284 0x00, /* D2 */
285 0x00, /* D3 */
286 0x00, /* D4 */
287 0x00, /* D5 */
288 0x00, /* D6 */
289 0x00, /* D7 */
290 0x00, /* D8 */
291 0x00, /* D9 */
292 0x00, /* DA */
293 0x70, /* DB */
294 0x00, /* DC */
295 0x00, /* DD */
296 0x00, /* DE */
297 0x00, /* DF */
298
299 0x00, /* E0 */
300 0x00, /* E1 */
301 0x00, /* E2 */
302 0x00, /* E3 */
303 0x00, /* E4 */
304 0x00, /* E5 */
305 0x00, /* E6 */
306 0x00, /* E7 */
307 0x00, /* E8 */
308 0x00, /* E9 */
309 0x00, /* EA */
310 0x00, /* EB */
311 0x00, /* EC */
312 0x00, /* ED */
313 0x00, /* EE */
314 0x00, /* EF */
315
316 0x00, /* F0 */
317 0x00, /* F1 */
318 0x00, /* F2 */
319 0x00, /* F3 */
320 0x00, /* F4 */
321 0x00, /* F5 */
322 0x00, /* F6 */
323 0x00, /* F7 */
324 0x00, /* F8 */
325 0x00, /* F9 */
326 0x00, /* FA */
327 0x00, /* FB */
328 0x00, /* FC */
329 0x00, /* FD */
330 0x00, /* FE */
331 0x00, /* FF */
332};
333
334static struct {
335 int readable;
336 int writable;
337 int vol;
338} max98088_access[M98088_REG_CNT] = {
339 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */
340 { 0xFF, 0x00, 1 }, /* 01 MIC status */
341 { 0xFF, 0x00, 1 }, /* 02 jack status */
342 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */
343 { 0xFF, 0xFF, 0 }, /* 04 */
344 { 0xFF, 0xFF, 0 }, /* 05 */
345 { 0xFF, 0xFF, 0 }, /* 06 */
346 { 0xFF, 0xFF, 0 }, /* 07 */
347 { 0xFF, 0xFF, 0 }, /* 08 */
348 { 0xFF, 0xFF, 0 }, /* 09 */
349 { 0xFF, 0xFF, 0 }, /* 0A */
350 { 0xFF, 0xFF, 0 }, /* 0B */
351 { 0xFF, 0xFF, 0 }, /* 0C */
352 { 0xFF, 0xFF, 0 }, /* 0D */
353 { 0xFF, 0xFF, 0 }, /* 0E */
354 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */
355
356 { 0xFF, 0xFF, 0 }, /* 10 master clock */
357 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */
358 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */
359 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */
360 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */
361 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */
362 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */
363 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */
364 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */
365 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */
366 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */
367 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */
368 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */
369 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */
370 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */
371 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */
372
373 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */
374 { 0xFF, 0xFF, 0 }, /* 21 data config */
375 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */
376 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */
377 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */
378 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */
379 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */
380 { 0xFF, 0xFF, 0 }, /* 27 HP control */
381 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */
382 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */
383 { 0xFF, 0xFF, 0 }, /* 2A REC control */
384 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */
385 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */
386 { 0xFF, 0xFF, 0 }, /* 2D SPK control */
387 { 0xFF, 0xFF, 0 }, /* 2E sidetone */
388 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */
389
390 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */
391 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */
392 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */
393 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */
394 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */
395 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */
396 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */
397 { 0xFF, 0xFF, 0 }, /* 37 INA level */
398 { 0xFF, 0xFF, 0 }, /* 38 INB level */
399 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */
400 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */
401 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */
402 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */
403 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */
404 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */
405 { 0xFF, 0xFF, 0 }, /* 3F MIC config */
406
407 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */
408 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */
409 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */
410 { 0xFF, 0xFF, 0 }, /* 43 ALC */
411 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */
412 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */
413 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */
414 { 0xFF, 0xFF, 0 }, /* 47 audio input */
415 { 0xFF, 0xFF, 0 }, /* 48 microphone */
416 { 0xFF, 0xFF, 0 }, /* 49 level control */
417 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */
418 { 0xFF, 0xFF, 0 }, /* 4B jack detect */
419 { 0xFF, 0xFF, 0 }, /* 4C input enable */
420 { 0xFF, 0xFF, 0 }, /* 4D output enable */
421 { 0xFF, 0xFF, 0 }, /* 4E bias control */
422 { 0xFF, 0xFF, 0 }, /* 4F DAC power */
423
424 { 0xFF, 0xFF, 0 }, /* 50 DAC power */
425 { 0xFF, 0xFF, 0 }, /* 51 system */
426 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */
427 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */
428 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */
429 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */
430 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */
431 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */
432 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */
433 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */
434 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */
435 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */
436 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */
437 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */
438 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */
439 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */
440
441 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */
442 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */
443 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */
444 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */
445 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */
446 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */
447 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */
448 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */
449 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */
450 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */
451 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */
452 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */
453 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */
454 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */
455 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */
456 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */
457
458 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */
459 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */
460 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */
461 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */
462 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */
463 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */
464 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */
465 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */
466 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */
467 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */
468 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */
469 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */
470 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */
471 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */
472 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */
473 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */
474
475 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */
476 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */
477 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */
478 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */
479 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */
480 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */
481 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */
482 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */
483 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */
484 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */
485 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */
486 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */
487 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */
488 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */
489 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */
490 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */
491
492 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */
493 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */
494 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */
495 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */
496 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */
497 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */
498 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */
499 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */
500 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */
501 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */
502 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */
503 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */
504 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */
505 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */
506 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */
507 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */
508
509 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */
510 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */
511 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */
512 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */
513 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */
514 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */
515 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */
516 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */
517 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */
518 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */
519 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */
520 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */
521 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */
522 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */
523 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */
524 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */
525
526 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */
527 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */
528 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */
529 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */
530 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */
531 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */
532 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */
533 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */
534 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */
535 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */
536 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */
537 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */
538 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */
539 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */
540 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */
541 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */
542
543 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */
544 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */
545 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */
546 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */
547 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */
548 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */
549 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */
550 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */
551 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */
552 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */
553 { 0x00, 0x00, 0 }, /* CA */
554 { 0x00, 0x00, 0 }, /* CB */
555 { 0x00, 0x00, 0 }, /* CC */
556 { 0x00, 0x00, 0 }, /* CD */
557 { 0x00, 0x00, 0 }, /* CE */
558 { 0x00, 0x00, 0 }, /* CF */
559
560 { 0x00, 0x00, 0 }, /* D0 */
561 { 0x00, 0x00, 0 }, /* D1 */
562 { 0x00, 0x00, 0 }, /* D2 */
563 { 0x00, 0x00, 0 }, /* D3 */
564 { 0x00, 0x00, 0 }, /* D4 */
565 { 0x00, 0x00, 0 }, /* D5 */
566 { 0x00, 0x00, 0 }, /* D6 */
567 { 0x00, 0x00, 0 }, /* D7 */
568 { 0x00, 0x00, 0 }, /* D8 */
569 { 0x00, 0x00, 0 }, /* D9 */
570 { 0x00, 0x00, 0 }, /* DA */
571 { 0x00, 0x00, 0 }, /* DB */
572 { 0x00, 0x00, 0 }, /* DC */
573 { 0x00, 0x00, 0 }, /* DD */
574 { 0x00, 0x00, 0 }, /* DE */
575 { 0x00, 0x00, 0 }, /* DF */
576
577 { 0x00, 0x00, 0 }, /* E0 */
578 { 0x00, 0x00, 0 }, /* E1 */
579 { 0x00, 0x00, 0 }, /* E2 */
580 { 0x00, 0x00, 0 }, /* E3 */
581 { 0x00, 0x00, 0 }, /* E4 */
582 { 0x00, 0x00, 0 }, /* E5 */
583 { 0x00, 0x00, 0 }, /* E6 */
584 { 0x00, 0x00, 0 }, /* E7 */
585 { 0x00, 0x00, 0 }, /* E8 */
586 { 0x00, 0x00, 0 }, /* E9 */
587 { 0x00, 0x00, 0 }, /* EA */
588 { 0x00, 0x00, 0 }, /* EB */
589 { 0x00, 0x00, 0 }, /* EC */
590 { 0x00, 0x00, 0 }, /* ED */
591 { 0x00, 0x00, 0 }, /* EE */
592 { 0x00, 0x00, 0 }, /* EF */
593
594 { 0x00, 0x00, 0 }, /* F0 */
595 { 0x00, 0x00, 0 }, /* F1 */
596 { 0x00, 0x00, 0 }, /* F2 */
597 { 0x00, 0x00, 0 }, /* F3 */
598 { 0x00, 0x00, 0 }, /* F4 */
599 { 0x00, 0x00, 0 }, /* F5 */
600 { 0x00, 0x00, 0 }, /* F6 */
601 { 0x00, 0x00, 0 }, /* F7 */
602 { 0x00, 0x00, 0 }, /* F8 */
603 { 0x00, 0x00, 0 }, /* F9 */
604 { 0x00, 0x00, 0 }, /* FA */
605 { 0x00, 0x00, 0 }, /* FB */
606 { 0x00, 0x00, 0 }, /* FC */
607 { 0x00, 0x00, 0 }, /* FD */
608 { 0x00, 0x00, 0 }, /* FE */
609 { 0xFF, 0x00, 1 }, /* FF */
610};
611
612static int max98088_volatile_register(unsigned int reg)
613{
614 return max98088_access[reg].vol;
615}
616
617
618/*
619 * Load equalizer DSP coefficient configurations registers
620 */
Dimitris Papastamos4428bc02010-10-21 12:15:56 +0100[diff] [blame]621static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai,
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]622 unsigned int band, u16 *coefs)
623{
624 unsigned int eq_reg;
625 unsigned int i;
626
627 BUG_ON(band > 4);
628 BUG_ON(dai > 1);
629
630 /* Load the base register address */
631 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
632
633 /* Add the band address offset, note adjustment for word address */
634 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
635
636 /* Step through the registers and coefs */
637 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
638 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i]));
639 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i]));
640 }
641}
642
643/*
644 * Excursion limiter modes
645 */
646static const char *max98088_exmode_texts[] = {
647 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
648 "400-600Hz", "400-800Hz",
649};
650
651static const unsigned int max98088_exmode_values[] = {
652 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
653};
654
655static const struct soc_enum max98088_exmode_enum =
656 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127,
657 ARRAY_SIZE(max98088_exmode_texts),
658 max98088_exmode_texts,
659 max98088_exmode_values);
660static const struct snd_kcontrol_new max98088_exmode_controls =
661 SOC_DAPM_VALUE_ENUM("Route", max98088_exmode_enum);
662
663static const char *max98088_ex_thresh[] = { /* volts PP */
664 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
665static const struct soc_enum max98088_ex_thresh_enum[] = {
666 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8,
667 max98088_ex_thresh),
668};
669
670static const char *max98088_fltr_mode[] = {"Voice", "Music" };
671static const struct soc_enum max98088_filter_mode_enum[] = {
672 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode),
673};
674
675static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
676
677static const struct soc_enum max98088_extmic_enum =
678 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text);
679
680static const struct snd_kcontrol_new max98088_extmic_mux =
681 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
682
683static const char *max98088_dai1_fltr[] = {
684 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
685 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
686static const struct soc_enum max98088_dai1_dac_filter_enum[] = {
687 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr),
688};
689static const struct soc_enum max98088_dai1_adc_filter_enum[] = {
690 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr),
691};
692
693static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
694 struct snd_ctl_elem_value *ucontrol)
695{
696 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
697 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
698 unsigned int sel = ucontrol->value.integer.value[0];
699
700 max98088->mic1pre = sel;
701 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
702 (1+sel)<<M98088_MICPRE_SHIFT);
703
704 return 0;
705}
706
707static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
708 struct snd_ctl_elem_value *ucontrol)
709{
710 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
711 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
712
713 ucontrol->value.integer.value[0] = max98088->mic1pre;
714 return 0;
715}
716
717static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
718 struct snd_ctl_elem_value *ucontrol)
719{
720 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
721 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
722 unsigned int sel = ucontrol->value.integer.value[0];
723
724 max98088->mic2pre = sel;
725 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
726 (1+sel)<<M98088_MICPRE_SHIFT);
727
728 return 0;
729}
730
731static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
732 struct snd_ctl_elem_value *ucontrol)
733{
734 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
735 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
736
737 ucontrol->value.integer.value[0] = max98088->mic2pre;
738 return 0;
739}
740
741static const unsigned int max98088_micboost_tlv[] = {
742 TLV_DB_RANGE_HEAD(2),
743 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
744 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
745};
746
747static const struct snd_kcontrol_new max98088_snd_controls[] = {
748
749 SOC_DOUBLE_R("Headphone Volume", M98088_REG_39_LVL_HP_L,
750 M98088_REG_3A_LVL_HP_R, 0, 31, 0),
751 SOC_DOUBLE_R("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
752 M98088_REG_3E_LVL_SPK_R, 0, 31, 0),
753 SOC_DOUBLE_R("Receiver Volume", M98088_REG_3B_LVL_REC_L,
754 M98088_REG_3C_LVL_REC_R, 0, 31, 0),
755
756 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
757 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
758 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
759 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
760 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
761 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
762
763 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
764 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
765
766 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
767 M98088_REG_35_LVL_MIC1, 5, 2, 0,
768 max98088_mic1pre_get, max98088_mic1pre_set,
769 max98088_micboost_tlv),
770 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
771 M98088_REG_36_LVL_MIC2, 5, 2, 0,
772 max98088_mic2pre_get, max98088_mic2pre_set,
773 max98088_micboost_tlv),
774
775 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
776 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
777
778 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
779 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
780
781 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
782 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
783
784 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
785 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
786
787 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
788
789 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
790 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
791 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
792 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
793 0, 1, 0),
794
795 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
796 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
797 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
798 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
799
800 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
801 4, 15, 0),
802 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
803 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
804 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
805
806 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
807 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
808};
809
810/* Left speaker mixer switch */
811static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
812 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
813 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
814 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
815 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
816 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
817 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
818 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
819 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
820 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
821 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
822};
823
824/* Right speaker mixer switch */
825static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
826 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
827 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
828 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
829 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
830 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
831 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
832 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
833 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
834 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
835 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
836};
837
838/* Left headphone mixer switch */
839static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
840 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
841 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
842 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
843 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
844 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
845 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
846 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
847 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
848 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
849 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
850};
851
852/* Right headphone mixer switch */
853static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
854 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
855 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
856 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
857 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
858 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
859 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
860 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
861 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
862 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
863 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
864};
865
866/* Left earpiece/receiver mixer switch */
867static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
868 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
869 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
870 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
871 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
872 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
873 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
874 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
875 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
876 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
877 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
878};
879
880/* Right earpiece/receiver mixer switch */
881static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
882 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
883 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
884 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
885 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
886 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
887 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
888 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
889 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
890 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
891 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
892};
893
894/* Left ADC mixer switch */
895static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
896 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
897 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
898 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
899 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
900 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
901 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
902};
903
904/* Right ADC mixer switch */
905static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
906 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
907 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
908 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
909 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
910 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
911 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
912};
913
914static int max98088_mic_event(struct snd_soc_dapm_widget *w,
915 struct snd_kcontrol *kcontrol, int event)
916{
917 struct snd_soc_codec *codec = w->codec;
918 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
919
920 switch (event) {
921 case SND_SOC_DAPM_POST_PMU:
922 if (w->reg == M98088_REG_35_LVL_MIC1) {
923 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
924 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
925 } else {
926 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK,
927 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
928 }
929 break;
930 case SND_SOC_DAPM_POST_PMD:
931 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0);
932 break;
933 default:
934 return -EINVAL;
935 }
936
937 return 0;
938}
939
940/*
941 * The line inputs are 2-channel stereo inputs with the left
942 * and right channels sharing a common PGA power control signal.
943 */
944static int max98088_line_pga(struct snd_soc_dapm_widget *w,
945 int event, int line, u8 channel)
946{
947 struct snd_soc_codec *codec = w->codec;
948 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
949 u8 *state;
950
951 BUG_ON(!((channel == 1) || (channel == 2)));
952
953 switch (line) {
954 case LINE_INA:
955 state = &max98088->ina_state;
956 break;
957 case LINE_INB:
958 state = &max98088->inb_state;
959 break;
960 default:
961 return -EINVAL;
962 }
963
964 switch (event) {
965 case SND_SOC_DAPM_POST_PMU:
966 *state |= channel;
967 snd_soc_update_bits(codec, w->reg,
968 (1 << w->shift), (1 << w->shift));
969 break;
970 case SND_SOC_DAPM_POST_PMD:
971 *state &= ~channel;
972 if (*state == 0) {
973 snd_soc_update_bits(codec, w->reg,
974 (1 << w->shift), 0);
975 }
976 break;
977 default:
978 return -EINVAL;
979 }
980
981 return 0;
982}
983
984static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
985 struct snd_kcontrol *k, int event)
986{
987 return max98088_line_pga(w, event, LINE_INA, 1);
988}
989
990static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
991 struct snd_kcontrol *k, int event)
992{
993 return max98088_line_pga(w, event, LINE_INA, 2);
994}
995
996static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
997 struct snd_kcontrol *k, int event)
998{
999 return max98088_line_pga(w, event, LINE_INB, 1);
1000}
1001
1002static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
1003 struct snd_kcontrol *k, int event)
1004{
1005 return max98088_line_pga(w, event, LINE_INB, 2);
1006}
1007
1008static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
1009
1010 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
1011 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
1012
1013 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
1014 M98088_REG_4D_PWR_EN_OUT, 1, 0),
1015 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
1016 M98088_REG_4D_PWR_EN_OUT, 0, 0),
1017 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
1018 M98088_REG_4D_PWR_EN_OUT, 1, 0),
1019 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
1020 M98088_REG_4D_PWR_EN_OUT, 0, 0),
1021
1022 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
1023 7, 0, NULL, 0),
1024 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
1025 6, 0, NULL, 0),
1026
1027 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
1028 5, 0, NULL, 0),
1029 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
1030 4, 0, NULL, 0),
1031
1032 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
1033 3, 0, NULL, 0),
1034 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
1035 2, 0, NULL, 0),
1036
1037 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
1038 &max98088_extmic_mux),
1039
1040 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
1041 &max98088_left_hp_mixer_controls[0],
1042 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
1043
1044 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
1045 &max98088_right_hp_mixer_controls[0],
1046 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
1047
1048 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
1049 &max98088_left_speaker_mixer_controls[0],
1050 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
1051
1052 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
1053 &max98088_right_speaker_mixer_controls[0],
1054 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
1055
1056 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
1057 &max98088_left_rec_mixer_controls[0],
1058 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
1059
1060 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
1061 &max98088_right_rec_mixer_controls[0],
1062 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
1063
1064 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1065 &max98088_left_ADC_mixer_controls[0],
1066 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
1067
1068 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1069 &max98088_right_ADC_mixer_controls[0],
1070 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
1071
1072 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
1073 5, 0, NULL, 0, max98088_mic_event,
1074 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1075
1076 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
1077 5, 0, NULL, 0, max98088_mic_event,
1078 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1079
1080 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
1081 7, 0, NULL, 0, max98088_pga_ina1_event,
1082 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1083
1084 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
1085 7, 0, NULL, 0, max98088_pga_ina2_event,
1086 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1087
1088 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
1089 6, 0, NULL, 0, max98088_pga_inb1_event,
1090 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1091
1092 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
1093 6, 0, NULL, 0, max98088_pga_inb2_event,
1094 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1095
1096 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
1097
1098 SND_SOC_DAPM_MUX("EX Limiter Mode", SND_SOC_NOPM, 0, 0,
1099 &max98088_exmode_controls),
1100
1101 SND_SOC_DAPM_OUTPUT("HPL"),
1102 SND_SOC_DAPM_OUTPUT("HPR"),
1103 SND_SOC_DAPM_OUTPUT("SPKL"),
1104 SND_SOC_DAPM_OUTPUT("SPKR"),
1105 SND_SOC_DAPM_OUTPUT("RECL"),
1106 SND_SOC_DAPM_OUTPUT("RECR"),
1107
1108 SND_SOC_DAPM_INPUT("MIC1"),
1109 SND_SOC_DAPM_INPUT("MIC2"),
1110 SND_SOC_DAPM_INPUT("INA1"),
1111 SND_SOC_DAPM_INPUT("INA2"),
1112 SND_SOC_DAPM_INPUT("INB1"),
1113 SND_SOC_DAPM_INPUT("INB2"),
1114};
1115
1116static const struct snd_soc_dapm_route audio_map[] = {
1117 /* Left headphone output mixer */
1118 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
1119 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
1120 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
1121 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
1122 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
1123 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
1124 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
1125 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
1126 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
1127 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
1128
1129 /* Right headphone output mixer */
1130 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
1131 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
1132 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
1133 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
1134 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
1135 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
1136 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
1137 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
1138 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
1139 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
1140
1141 /* Left speaker output mixer */
1142 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
1143 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
1144 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
1145 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
1146 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1147 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1148 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
1149 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
1150 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
1151 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
1152
1153 /* Right speaker output mixer */
1154 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
1155 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
1156 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
1157 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
1158 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
1159 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
1160 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
1161 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
1162 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
1163 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
1164
1165 /* Earpiece/Receiver output mixer */
1166 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
1167 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
1168 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
1169 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
1170 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
1171 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
1172 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
1173 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
1174 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
1175 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
1176
1177 /* Earpiece/Receiver output mixer */
1178 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
1179 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
1180 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
1181 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
1182 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
1183 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
1184 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
1185 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
1186 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
1187 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
1188
1189 {"HP Left Out", NULL, "Left HP Mixer"},
1190 {"HP Right Out", NULL, "Right HP Mixer"},
1191 {"SPK Left Out", NULL, "Left SPK Mixer"},
1192 {"SPK Right Out", NULL, "Right SPK Mixer"},
1193 {"REC Left Out", NULL, "Left REC Mixer"},
1194 {"REC Right Out", NULL, "Right REC Mixer"},
1195
1196 {"HPL", NULL, "HP Left Out"},
1197 {"HPR", NULL, "HP Right Out"},
1198 {"SPKL", NULL, "SPK Left Out"},
1199 {"SPKR", NULL, "SPK Right Out"},
1200 {"RECL", NULL, "REC Left Out"},
1201 {"RECR", NULL, "REC Right Out"},
1202
1203 /* Left ADC input mixer */
1204 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1205 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1206 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
1207 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
1208 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
1209 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
1210
1211 /* Right ADC input mixer */
1212 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1213 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1214 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
1215 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
1216 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
1217 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
1218
1219 /* Inputs */
1220 {"ADCL", NULL, "Left ADC Mixer"},
1221 {"ADCR", NULL, "Right ADC Mixer"},
1222 {"INA1 Input", NULL, "INA1"},
1223 {"INA2 Input", NULL, "INA2"},
1224 {"INB1 Input", NULL, "INB1"},
1225 {"INB2 Input", NULL, "INB2"},
1226 {"MIC1 Input", NULL, "MIC1"},
1227 {"MIC2 Input", NULL, "MIC2"},
1228};
1229
1230static int max98088_add_widgets(struct snd_soc_codec *codec)
1231{
1232 snd_soc_dapm_new_controls(codec, max98088_dapm_widgets,
1233 ARRAY_SIZE(max98088_dapm_widgets));
1234
1235 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
1236
1237 snd_soc_add_controls(codec, max98088_snd_controls,
1238 ARRAY_SIZE(max98088_snd_controls));
1239
1240 snd_soc_dapm_new_widgets(codec);
1241 return 0;
1242}
1243
1244/* codec mclk clock divider coefficients */
1245static const struct {
1246 u32 rate;
1247 u8 sr;
1248} rate_table[] = {
1249 {8000, 0x10},
1250 {11025, 0x20},
1251 {16000, 0x30},
1252 {22050, 0x40},
1253 {24000, 0x50},
1254 {32000, 0x60},
1255 {44100, 0x70},
1256 {48000, 0x80},
1257 {88200, 0x90},
1258 {96000, 0xA0},
1259};
1260
1261static inline int rate_value(int rate, u8 *value)
1262{
1263 int i;
1264
1265 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
1266 if (rate_table[i].rate >= rate) {
1267 *value = rate_table[i].sr;
1268 return 0;
1269 }
1270 }
1271 *value = rate_table[0].sr;
1272 return -EINVAL;
1273}
1274
1275static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
1276 struct snd_pcm_hw_params *params,
1277 struct snd_soc_dai *dai)
1278{
1279 struct snd_soc_codec *codec = dai->codec;
1280 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1281 struct max98088_cdata *cdata;
1282 unsigned long long ni;
1283 unsigned int rate;
1284 u8 regval;
1285
1286 cdata = &max98088->dai[0];
1287
1288 rate = params_rate(params);
1289
1290 switch (params_format(params)) {
1291 case SNDRV_PCM_FORMAT_S16_LE:
1292 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1293 M98088_DAI_WS, 0);
1294 break;
1295 case SNDRV_PCM_FORMAT_S24_LE:
1296 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1297 M98088_DAI_WS, M98088_DAI_WS);
1298 break;
1299 default:
1300 return -EINVAL;
1301 }
1302
1303 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1304
1305 if (rate_value(rate, &regval))
1306 return -EINVAL;
1307
1308 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE,
1309 M98088_CLKMODE_MASK, regval);
1310 cdata->rate = rate;
1311
1312 /* Configure NI when operating as master */
1313 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT)
1314 & M98088_DAI_MAS) {
1315 if (max98088->sysclk == 0) {
1316 dev_err(codec->dev, "Invalid system clock frequency\n");
1317 return -EINVAL;
1318 }
1319 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1320 * (unsigned long long int)rate;
1321 do_div(ni, (unsigned long long int)max98088->sysclk);
1322 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1323 (ni >> 8) & 0x7F);
1324 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1325 ni & 0xFF);
1326 }
1327
1328 /* Update sample rate mode */
1329 if (rate < 50000)
1330 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1331 M98088_DAI_DHF, 0);
1332 else
1333 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS,
1334 M98088_DAI_DHF, M98088_DAI_DHF);
1335
1336 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1337 M98088_SHDNRUN);
1338
1339 return 0;
1340}
1341
1342static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1343 struct snd_pcm_hw_params *params,
1344 struct snd_soc_dai *dai)
1345{
1346 struct snd_soc_codec *codec = dai->codec;
1347 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1348 struct max98088_cdata *cdata;
1349 unsigned long long ni;
1350 unsigned int rate;
1351 u8 regval;
1352
1353 cdata = &max98088->dai[1];
1354
1355 rate = params_rate(params);
1356
1357 switch (params_format(params)) {
1358 case SNDRV_PCM_FORMAT_S16_LE:
1359 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1360 M98088_DAI_WS, 0);
1361 break;
1362 case SNDRV_PCM_FORMAT_S24_LE:
1363 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1364 M98088_DAI_WS, M98088_DAI_WS);
1365 break;
1366 default:
1367 return -EINVAL;
1368 }
1369
1370 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1371
1372 if (rate_value(rate, &regval))
1373 return -EINVAL;
1374
1375 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE,
1376 M98088_CLKMODE_MASK, regval);
1377 cdata->rate = rate;
1378
1379 /* Configure NI when operating as master */
1380 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT)
1381 & M98088_DAI_MAS) {
1382 if (max98088->sysclk == 0) {
1383 dev_err(codec->dev, "Invalid system clock frequency\n");
1384 return -EINVAL;
1385 }
1386 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1387 * (unsigned long long int)rate;
1388 do_div(ni, (unsigned long long int)max98088->sysclk);
1389 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1390 (ni >> 8) & 0x7F);
1391 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1392 ni & 0xFF);
1393 }
1394
1395 /* Update sample rate mode */
1396 if (rate < 50000)
1397 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1398 M98088_DAI_DHF, 0);
1399 else
1400 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS,
1401 M98088_DAI_DHF, M98088_DAI_DHF);
1402
1403 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1404 M98088_SHDNRUN);
1405
1406 return 0;
1407}
1408
1409static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1410 int clk_id, unsigned int freq, int dir)
1411{
1412 struct snd_soc_codec *codec = dai->codec;
1413 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1414
1415 /* Requested clock frequency is already setup */
1416 if (freq == max98088->sysclk)
1417 return 0;
1418
1419 max98088->sysclk = freq; /* remember current sysclk */
1420
1421 /* Setup clocks for slave mode, and using the PLL
1422 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1423 * 0x02 (when master clk is 20MHz to 30MHz)..
1424 */
1425 if ((freq >= 10000000) && (freq < 20000000)) {
1426 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10);
1427 } else if ((freq >= 20000000) && (freq < 30000000)) {
1428 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20);
1429 } else {
1430 dev_err(codec->dev, "Invalid master clock frequency\n");
1431 return -EINVAL;
1432 }
1433
1434 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1435 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1436 M98088_SHDNRUN, 0);
1437 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS,
1438 M98088_SHDNRUN, M98088_SHDNRUN);
1439 }
1440
1441 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1442
1443 max98088->sysclk = freq;
1444 return 0;
1445}
1446
1447static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1448 unsigned int fmt)
1449{
1450 struct snd_soc_codec *codec = codec_dai->codec;
1451 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1452 struct max98088_cdata *cdata;
1453 u8 reg15val;
1454 u8 reg14val = 0;
1455
1456 cdata = &max98088->dai[0];
1457
1458 if (fmt != cdata->fmt) {
1459 cdata->fmt = fmt;
1460
1461 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1462 case SND_SOC_DAIFMT_CBS_CFS:
1463 /* Slave mode PLL */
1464 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI,
1465 0x80);
1466 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO,
1467 0x00);
1468 break;
1469 case SND_SOC_DAIFMT_CBM_CFM:
1470 /* Set to master mode */
1471 reg14val |= M98088_DAI_MAS;
1472 break;
1473 case SND_SOC_DAIFMT_CBS_CFM:
1474 case SND_SOC_DAIFMT_CBM_CFS:
1475 default:
1476 dev_err(codec->dev, "Clock mode unsupported");
1477 return -EINVAL;
1478 }
1479
1480 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1481 case SND_SOC_DAIFMT_I2S:
1482 reg14val |= M98088_DAI_DLY;
1483 break;
1484 case SND_SOC_DAIFMT_LEFT_J:
1485 break;
1486 default:
1487 return -EINVAL;
1488 }
1489
1490 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1491 case SND_SOC_DAIFMT_NB_NF:
1492 break;
1493 case SND_SOC_DAIFMT_NB_IF:
1494 reg14val |= M98088_DAI_WCI;
1495 break;
1496 case SND_SOC_DAIFMT_IB_NF:
1497 reg14val |= M98088_DAI_BCI;
1498 break;
1499 case SND_SOC_DAIFMT_IB_IF:
1500 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1501 break;
1502 default:
1503 return -EINVAL;
1504 }
1505
1506 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT,
1507 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1508 M98088_DAI_WCI, reg14val);
1509
1510 reg15val = M98088_DAI_BSEL64;
1511 if (max98088->digmic)
1512 reg15val |= M98088_DAI_OSR64;
1513 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val);
1514 }
1515
1516 return 0;
1517}
1518
1519static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1520 unsigned int fmt)
1521{
1522 struct snd_soc_codec *codec = codec_dai->codec;
1523 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1524 struct max98088_cdata *cdata;
1525 u8 reg1Cval = 0;
1526
1527 cdata = &max98088->dai[1];
1528
1529 if (fmt != cdata->fmt) {
1530 cdata->fmt = fmt;
1531
1532 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1533 case SND_SOC_DAIFMT_CBS_CFS:
1534 /* Slave mode PLL */
1535 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI,
1536 0x80);
1537 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO,
1538 0x00);
1539 break;
1540 case SND_SOC_DAIFMT_CBM_CFM:
1541 /* Set to master mode */
1542 reg1Cval |= M98088_DAI_MAS;
1543 break;
1544 case SND_SOC_DAIFMT_CBS_CFM:
1545 case SND_SOC_DAIFMT_CBM_CFS:
1546 default:
1547 dev_err(codec->dev, "Clock mode unsupported");
1548 return -EINVAL;
1549 }
1550
1551 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1552 case SND_SOC_DAIFMT_I2S:
1553 reg1Cval |= M98088_DAI_DLY;
1554 break;
1555 case SND_SOC_DAIFMT_LEFT_J:
1556 break;
1557 default:
1558 return -EINVAL;
1559 }
1560
1561 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1562 case SND_SOC_DAIFMT_NB_NF:
1563 break;
1564 case SND_SOC_DAIFMT_NB_IF:
1565 reg1Cval |= M98088_DAI_WCI;
1566 break;
1567 case SND_SOC_DAIFMT_IB_NF:
1568 reg1Cval |= M98088_DAI_BCI;
1569 break;
1570 case SND_SOC_DAIFMT_IB_IF:
1571 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1572 break;
1573 default:
1574 return -EINVAL;
1575 }
1576
1577 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT,
1578 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1579 M98088_DAI_WCI, reg1Cval);
1580
1581 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK,
1582 M98088_DAI_BSEL64);
1583 }
1584
1585 return 0;
1586}
1587
1588static void max98088_sync_cache(struct snd_soc_codec *codec)
1589{
Lars-Peter Clausend24eb0d2010-12-28 21:37:56 +0100[diff] [blame]1590 u16 *reg_cache = codec->reg_cache;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1591 int i;
1592
1593 if (!codec->cache_sync)
1594 return;
1595
1596 codec->cache_only = 0;
1597
1598 /* write back cached values if they're writeable and
1599 * different from the hardware default.
1600 */
Lars-Peter Clausend24eb0d2010-12-28 21:37:56 +0100[diff] [blame]1601 for (i = 1; i < codec->driver->reg_cache_size; i++) {
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1602 if (!max98088_access[i].writable)
1603 continue;
1604
Lars-Peter Clausend24eb0d2010-12-28 21:37:56 +0100[diff] [blame]1605 if (reg_cache[i] == max98088_reg[i])
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1606 continue;
1607
Lars-Peter Clausend24eb0d2010-12-28 21:37:56 +0100[diff] [blame]1608 snd_soc_write(codec, i, reg_cache[i]);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1609 }
1610
1611 codec->cache_sync = 0;
1612}
1613
1614static int max98088_set_bias_level(struct snd_soc_codec *codec,
1615 enum snd_soc_bias_level level)
1616{
1617 switch (level) {
1618 case SND_SOC_BIAS_ON:
1619 break;
1620
1621 case SND_SOC_BIAS_PREPARE:
1622 break;
1623
1624 case SND_SOC_BIAS_STANDBY:
1625 if (codec->bias_level == SND_SOC_BIAS_OFF)
1626 max98088_sync_cache(codec);
1627
1628 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1629 M98088_MBEN, M98088_MBEN);
1630 break;
1631
1632 case SND_SOC_BIAS_OFF:
1633 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1634 M98088_MBEN, 0);
1635 codec->cache_sync = 1;
1636 break;
1637 }
1638 codec->bias_level = level;
1639 return 0;
1640}
1641
1642#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1643#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1644
1645static struct snd_soc_dai_ops max98088_dai1_ops = {
1646 .set_sysclk = max98088_dai_set_sysclk,
1647 .set_fmt = max98088_dai1_set_fmt,
1648 .hw_params = max98088_dai1_hw_params,
1649};
1650
1651static struct snd_soc_dai_ops max98088_dai2_ops = {
1652 .set_sysclk = max98088_dai_set_sysclk,
1653 .set_fmt = max98088_dai2_set_fmt,
1654 .hw_params = max98088_dai2_hw_params,
1655};
1656
1657static struct snd_soc_dai_driver max98088_dai[] = {
1658{
1659 .name = "HiFi",
1660 .playback = {
1661 .stream_name = "HiFi Playback",
1662 .channels_min = 1,
1663 .channels_max = 2,
1664 .rates = MAX98088_RATES,
1665 .formats = MAX98088_FORMATS,
1666 },
1667 .capture = {
1668 .stream_name = "HiFi Capture",
1669 .channels_min = 1,
1670 .channels_max = 2,
1671 .rates = MAX98088_RATES,
1672 .formats = MAX98088_FORMATS,
1673 },
1674 .ops = &max98088_dai1_ops,
1675},
1676{
1677 .name = "Aux",
1678 .playback = {
1679 .stream_name = "Aux Playback",
1680 .channels_min = 1,
1681 .channels_max = 2,
1682 .rates = MAX98088_RATES,
1683 .formats = MAX98088_FORMATS,
1684 },
1685 .ops = &max98088_dai2_ops,
1686}
1687};
1688
1689static int max98088_get_channel(const char *name)
1690{
1691 if (strcmp(name, "EQ1 Mode") == 0)
1692 return 0;
1693 if (strcmp(name, "EQ2 Mode") == 0)
1694 return 1;
1695 return -EINVAL;
1696}
1697
1698static void max98088_setup_eq1(struct snd_soc_codec *codec)
1699{
1700 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1701 struct max98088_pdata *pdata = max98088->pdata;
1702 struct max98088_eq_cfg *coef_set;
1703 int best, best_val, save, i, sel, fs;
1704 struct max98088_cdata *cdata;
1705
1706 cdata = &max98088->dai[0];
1707
1708 if (!pdata || !max98088->eq_textcnt)
1709 return;
1710
1711 /* Find the selected configuration with nearest sample rate */
1712 fs = cdata->rate;
1713 sel = cdata->eq_sel;
1714
1715 best = 0;
1716 best_val = INT_MAX;
1717 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1718 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1719 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1720 best = i;
1721 best_val = abs(pdata->eq_cfg[i].rate - fs);
1722 }
1723 }
1724
1725 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1726 pdata->eq_cfg[best].name,
1727 pdata->eq_cfg[best].rate, fs);
1728
1729 /* Disable EQ while configuring, and save current on/off state */
1730 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1731 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1732
1733 coef_set = &pdata->eq_cfg[sel];
1734
1735 m98088_eq_band(codec, 0, 0, coef_set->band1);
1736 m98088_eq_band(codec, 0, 1, coef_set->band2);
1737 m98088_eq_band(codec, 0, 2, coef_set->band3);
1738 m98088_eq_band(codec, 0, 3, coef_set->band4);
1739 m98088_eq_band(codec, 0, 4, coef_set->band5);
1740
1741 /* Restore the original on/off state */
1742 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1743}
1744
1745static void max98088_setup_eq2(struct snd_soc_codec *codec)
1746{
1747 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1748 struct max98088_pdata *pdata = max98088->pdata;
1749 struct max98088_eq_cfg *coef_set;
1750 int best, best_val, save, i, sel, fs;
1751 struct max98088_cdata *cdata;
1752
1753 cdata = &max98088->dai[1];
1754
1755 if (!pdata || !max98088->eq_textcnt)
1756 return;
1757
1758 /* Find the selected configuration with nearest sample rate */
1759 fs = cdata->rate;
1760
1761 sel = cdata->eq_sel;
1762 best = 0;
1763 best_val = INT_MAX;
1764 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1765 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1766 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1767 best = i;
1768 best_val = abs(pdata->eq_cfg[i].rate - fs);
1769 }
1770 }
1771
1772 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1773 pdata->eq_cfg[best].name,
1774 pdata->eq_cfg[best].rate, fs);
1775
1776 /* Disable EQ while configuring, and save current on/off state */
1777 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL);
1778 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1779
1780 coef_set = &pdata->eq_cfg[sel];
1781
1782 m98088_eq_band(codec, 1, 0, coef_set->band1);
1783 m98088_eq_band(codec, 1, 1, coef_set->band2);
1784 m98088_eq_band(codec, 1, 2, coef_set->band3);
1785 m98088_eq_band(codec, 1, 3, coef_set->band4);
1786 m98088_eq_band(codec, 1, 4, coef_set->band5);
1787
1788 /* Restore the original on/off state */
1789 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1790 save);
1791}
1792
1793static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1794 struct snd_ctl_elem_value *ucontrol)
1795{
1796 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1797 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1798 struct max98088_pdata *pdata = max98088->pdata;
1799 int channel = max98088_get_channel(kcontrol->id.name);
1800 struct max98088_cdata *cdata;
1801 int sel = ucontrol->value.integer.value[0];
1802
1803 cdata = &max98088->dai[channel];
1804
1805 if (sel >= pdata->eq_cfgcnt)
1806 return -EINVAL;
1807
1808 cdata->eq_sel = sel;
1809
1810 switch (channel) {
1811 case 0:
1812 max98088_setup_eq1(codec);
1813 break;
1814 case 1:
1815 max98088_setup_eq2(codec);
1816 break;
1817 }
1818
1819 return 0;
1820}
1821
1822static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1823 struct snd_ctl_elem_value *ucontrol)
1824{
1825 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1826 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1827 int channel = max98088_get_channel(kcontrol->id.name);
1828 struct max98088_cdata *cdata;
1829
1830 cdata = &max98088->dai[channel];
1831 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1832 return 0;
1833}
1834
1835static void max98088_handle_eq_pdata(struct snd_soc_codec *codec)
1836{
1837 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1838 struct max98088_pdata *pdata = max98088->pdata;
1839 struct max98088_eq_cfg *cfg;
1840 unsigned int cfgcnt;
1841 int i, j;
1842 const char **t;
1843 int ret;
1844
1845 struct snd_kcontrol_new controls[] = {
1846 SOC_ENUM_EXT("EQ1 Mode",
1847 max98088->eq_enum,
1848 max98088_get_eq_enum,
1849 max98088_put_eq_enum),
1850 SOC_ENUM_EXT("EQ2 Mode",
1851 max98088->eq_enum,
1852 max98088_get_eq_enum,
1853 max98088_put_eq_enum),
1854 };
1855
1856 cfg = pdata->eq_cfg;
1857 cfgcnt = pdata->eq_cfgcnt;
1858
1859 /* Setup an array of texts for the equalizer enum.
1860 * This is based on Mark Brown's equalizer driver code.
1861 */
1862 max98088->eq_textcnt = 0;
1863 max98088->eq_texts = NULL;
1864 for (i = 0; i < cfgcnt; i++) {
1865 for (j = 0; j < max98088->eq_textcnt; j++) {
1866 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1867 break;
1868 }
1869
1870 if (j != max98088->eq_textcnt)
1871 continue;
1872
1873 /* Expand the array */
1874 t = krealloc(max98088->eq_texts,
1875 sizeof(char *) * (max98088->eq_textcnt + 1),
1876 GFP_KERNEL);
1877 if (t == NULL)
1878 continue;
1879
1880 /* Store the new entry */
1881 t[max98088->eq_textcnt] = cfg[i].name;
1882 max98088->eq_textcnt++;
1883 max98088->eq_texts = t;
1884 }
1885
1886 /* Now point the soc_enum to .texts array items */
1887 max98088->eq_enum.texts = max98088->eq_texts;
1888 max98088->eq_enum.max = max98088->eq_textcnt;
1889
1890 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
1891 if (ret != 0)
1892 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1893}
1894
1895static void max98088_handle_pdata(struct snd_soc_codec *codec)
1896{
1897 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1898 struct max98088_pdata *pdata = max98088->pdata;
1899 u8 regval = 0;
1900
1901 if (!pdata) {
1902 dev_dbg(codec->dev, "No platform data\n");
1903 return;
1904 }
1905
1906 /* Configure mic for analog/digital mic mode */
1907 if (pdata->digmic_left_mode)
1908 regval |= M98088_DIGMIC_L;
1909
1910 if (pdata->digmic_right_mode)
1911 regval |= M98088_DIGMIC_R;
1912
1913 max98088->digmic = (regval ? 1 : 0);
1914
1915 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval);
1916
1917 /* Configure receiver output */
1918 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1919 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL,
1920 M98088_REC_LINEMODE_MASK, regval);
1921
1922 /* Configure equalizers */
1923 if (pdata->eq_cfgcnt)
1924 max98088_handle_eq_pdata(codec);
1925}
1926
1927#ifdef CONFIG_PM
1928static int max98088_suspend(struct snd_soc_codec *codec, pm_message_t state)
1929{
1930 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
1931
1932 return 0;
1933}
1934
1935static int max98088_resume(struct snd_soc_codec *codec)
1936{
1937 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1938
1939 return 0;
1940}
1941#else
1942#define max98088_suspend NULL
1943#define max98088_resume NULL
1944#endif
1945
1946static int max98088_probe(struct snd_soc_codec *codec)
1947{
1948 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1949 struct max98088_cdata *cdata;
1950 int ret = 0;
1951
1952 codec->cache_sync = 1;
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]1953
1954 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
1955 if (ret != 0) {
1956 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1957 return ret;
1958 }
1959
1960 /* initalize private data */
1961
1962 max98088->sysclk = (unsigned)-1;
1963 max98088->eq_textcnt = 0;
1964
1965 cdata = &max98088->dai[0];
1966 cdata->rate = (unsigned)-1;
1967 cdata->fmt = (unsigned)-1;
1968 cdata->eq_sel = 0;
1969
1970 cdata = &max98088->dai[1];
1971 cdata->rate = (unsigned)-1;
1972 cdata->fmt = (unsigned)-1;
1973 cdata->eq_sel = 0;
1974
1975 max98088->ina_state = 0;
1976 max98088->inb_state = 0;
1977 max98088->ex_mode = 0;
1978 max98088->digmic = 0;
1979 max98088->mic1pre = 0;
1980 max98088->mic2pre = 0;
1981
1982 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID);
1983 if (ret < 0) {
1984 dev_err(codec->dev, "Failed to read device revision: %d\n",
1985 ret);
1986 goto err_access;
1987 }
1988 dev_info(codec->dev, "revision %c\n", ret + 'A');
1989
1990 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1991
1992 /* initialize registers cache to hardware default */
1993 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1994
1995 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00);
1996
1997 snd_soc_write(codec, M98088_REG_22_MIX_DAC,
1998 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1999 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
2000
2001 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0);
2002 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F);
2003
2004 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG,
2005 M98088_S1NORMAL|M98088_SDATA);
2006
2007 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG,
2008 M98088_S2NORMAL|M98088_SDATA);
2009
2010 max98088_handle_pdata(codec);
2011
2012 max98088_add_widgets(codec);
2013
2014err_access:
2015 return ret;
2016}
2017
2018static int max98088_remove(struct snd_soc_codec *codec)
2019{
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]2020 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
2021
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2022 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF);
Axel Linbc5954f2010-11-23 15:56:21 +0800[diff] [blame]2023 kfree(max98088->eq_texts);
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2024
2025 return 0;
2026}
2027
2028static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
2029 .probe = max98088_probe,
2030 .remove = max98088_remove,
2031 .suspend = max98088_suspend,
2032 .resume = max98088_resume,
2033 .set_bias_level = max98088_set_bias_level,
2034 .reg_cache_size = ARRAY_SIZE(max98088_reg),
2035 .reg_word_size = sizeof(u8),
2036 .reg_cache_default = max98088_reg,
2037 .volatile_register = max98088_volatile_register,
2038};
2039
2040static int max98088_i2c_probe(struct i2c_client *i2c,
2041 const struct i2c_device_id *id)
2042{
2043 struct max98088_priv *max98088;
2044 int ret;
2045
2046 max98088 = kzalloc(sizeof(struct max98088_priv), GFP_KERNEL);
2047 if (max98088 == NULL)
2048 return -ENOMEM;
2049
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2050 max98088->devtype = id->driver_data;
2051
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2052 i2c_set_clientdata(i2c, max98088);
2053 max98088->control_data = i2c;
2054 max98088->pdata = i2c->dev.platform_data;
2055
2056 ret = snd_soc_register_codec(&i2c->dev,
2057 &soc_codec_dev_max98088, &max98088_dai[0], 2);
2058 if (ret < 0)
2059 kfree(max98088);
2060 return ret;
2061}
2062
Arnaud Lacombef3607ae2010-10-26 16:04:35 -0400[diff] [blame]2063static int __devexit max98088_i2c_remove(struct i2c_client *client)
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2064{
2065 snd_soc_unregister_codec(&client->dev);
2066 kfree(i2c_get_clientdata(client));
2067 return 0;
2068}
2069
2070static const struct i2c_device_id max98088_i2c_id[] = {
Jesse Marroquinfb762a52010-11-17 14:26:40 -0600[diff] [blame]2071 { "max98088", MAX98088 },
2072 { "max98089", MAX98089 },
Mark Browne86e1242010-10-18 16:45:24 -0700[diff] [blame]2073 { }
2074};
2075MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
2076
2077static struct i2c_driver max98088_i2c_driver = {
2078 .driver = {
2079 .name = "max98088",
2080 .owner = THIS_MODULE,
2081 },
2082 .probe = max98088_i2c_probe,
2083 .remove = __devexit_p(max98088_i2c_remove),
2084 .id_table = max98088_i2c_id,
2085};
2086
2087static int __init max98088_init(void)
2088{
2089 int ret;
2090
2091 ret = i2c_add_driver(&max98088_i2c_driver);
2092 if (ret)
2093 pr_err("Failed to register max98088 I2C driver: %d\n", ret);
2094
2095 return ret;
2096}
2097module_init(max98088_init);
2098
2099static void __exit max98088_exit(void)
2100{
2101 i2c_del_driver(&max98088_i2c_driver);
2102}
2103module_exit(max98088_exit);
2104
2105MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
2106MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
2107MODULE_LICENSE("GPL");