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Sascha Haueraecfbdb2012-09-21 10:07:49 +02001/*
2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
10 */
11
12#ifndef __DRM_IPU_H__
13#define __DRM_IPU_H__
14
15#include <linux/types.h>
16#include <linux/videodev2.h>
17#include <linux/bitmap.h>
18#include <linux/fb.h>
Philipp Zabel310944d2016-05-12 15:00:44 +020019#include <linux/of.h>
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -070020#include <media/v4l2-mediabus.h>
Jiada Wang6541d712014-12-18 18:00:20 -080021#include <video/videomode.h>
Sascha Haueraecfbdb2012-09-21 10:07:49 +020022
23struct ipu_soc;
24
25enum ipuv3_type {
26 IPUV3EX,
27 IPUV3M,
28 IPUV3H,
29};
30
Philipp Zabel7f4392a2014-02-25 12:43:41 +010031#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
32
Sascha Haueraecfbdb2012-09-21 10:07:49 +020033/*
34 * Bitfield of Display Interface signal polarities.
35 */
36struct ipu_di_signal_cfg {
Sascha Haueraecfbdb2012-09-21 10:07:49 +020037 unsigned data_pol:1; /* true = inverted */
38 unsigned clk_pol:1; /* true = rising edge */
39 unsigned enable_pol:1;
Sascha Haueraecfbdb2012-09-21 10:07:49 +020040
Steve Longerbeamb6835a72014-12-18 18:00:25 -080041 struct videomode mode;
42
Philipp Zabel2872c802015-02-02 17:25:59 +010043 u32 bus_format;
Sascha Haueraecfbdb2012-09-21 10:07:49 +020044 u32 v_to_h_sync;
Steve Longerbeamb6835a72014-12-18 18:00:25 -080045
Sascha Haueraecfbdb2012-09-21 10:07:49 +020046#define IPU_DI_CLKMODE_SYNC (1 << 0)
47#define IPU_DI_CLKMODE_EXT (1 << 1)
48 unsigned long clkflags;
Philipp Zabel2ea42602013-04-08 18:04:35 +020049
50 u8 hsync_pin;
51 u8 vsync_pin;
Sascha Haueraecfbdb2012-09-21 10:07:49 +020052};
53
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -070054/*
55 * Enumeration of CSI destinations
56 */
57enum ipu_csi_dest {
58 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
59 IPU_CSI_DEST_IC, /* to Image Converter */
60 IPU_CSI_DEST_VDIC, /* to VDIC */
61};
62
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +020063/*
64 * Enumeration of IPU rotation modes
65 */
66enum ipu_rotate_mode {
67 IPU_ROTATE_NONE = 0,
68 IPU_ROTATE_VERT_FLIP,
69 IPU_ROTATE_HORIZ_FLIP,
70 IPU_ROTATE_180,
71 IPU_ROTATE_90_RIGHT,
72 IPU_ROTATE_90_RIGHT_VFLIP,
73 IPU_ROTATE_90_RIGHT_HFLIP,
74 IPU_ROTATE_90_LEFT,
75};
76
Sascha Haueraecfbdb2012-09-21 10:07:49 +020077enum ipu_color_space {
78 IPUV3_COLORSPACE_RGB,
79 IPUV3_COLORSPACE_YUV,
80 IPUV3_COLORSPACE_UNKNOWN,
81};
82
83struct ipuv3_channel;
84
85enum ipu_channel_irq {
86 IPU_IRQ_EOF = 0,
87 IPU_IRQ_NFACK = 64,
88 IPU_IRQ_NFB4EOF = 128,
89 IPU_IRQ_EOS = 192,
90};
91
Steve Longerbeama4cd8f22014-06-25 18:05:39 -070092/*
93 * Enumeration of IDMAC channels
94 */
95#define IPUV3_CHANNEL_CSI0 0
96#define IPUV3_CHANNEL_CSI1 1
97#define IPUV3_CHANNEL_CSI2 2
98#define IPUV3_CHANNEL_CSI3 3
99#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
100#define IPUV3_CHANNEL_MEM_IC_PP 11
101#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
102#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
103#define IPUV3_CHANNEL_G_MEM_IC_PP 15
104#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
105#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
106#define IPUV3_CHANNEL_IC_PP_MEM 22
107#define IPUV3_CHANNEL_MEM_BG_SYNC 23
108#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
109#define IPUV3_CHANNEL_MEM_FG_SYNC 27
110#define IPUV3_CHANNEL_MEM_DC_SYNC 28
111#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
112#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
113#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
114#define IPUV3_CHANNEL_MEM_ROT_ENC 45
115#define IPUV3_CHANNEL_MEM_ROT_VF 46
116#define IPUV3_CHANNEL_MEM_ROT_PP 47
117#define IPUV3_CHANNEL_ROT_ENC_MEM 48
118#define IPUV3_CHANNEL_ROT_VF_MEM 49
119#define IPUV3_CHANNEL_ROT_PP_MEM 50
120#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
121
Philipp Zabel861a50c2014-04-14 23:53:16 +0200122int ipu_map_irq(struct ipu_soc *ipu, int irq);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200123int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
124 enum ipu_channel_irq irq);
125
126#define IPU_IRQ_DP_SF_START (448 + 2)
127#define IPU_IRQ_DP_SF_END (448 + 3)
128#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
129#define IPU_IRQ_DC_FC_0 (448 + 8)
130#define IPU_IRQ_DC_FC_1 (448 + 9)
131#define IPU_IRQ_DC_FC_2 (448 + 10)
132#define IPU_IRQ_DC_FC_3 (448 + 11)
133#define IPU_IRQ_DC_FC_4 (448 + 12)
134#define IPU_IRQ_DC_FC_6 (448 + 13)
135#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
136#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
137
138/*
Steve Longerbeamba079752014-06-25 18:05:30 -0700139 * IPU Common functions
140 */
141void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
142void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
Steve Longerbeam3feb0492014-06-25 18:05:55 -0700143void ipu_dump(struct ipu_soc *ipu);
Steve Longerbeamba079752014-06-25 18:05:30 -0700144
145/*
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200146 * IPU Image DMA Controller (idmac) functions
147 */
148struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
149void ipu_idmac_put(struct ipuv3_channel *);
150
151int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
152int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
Steve Longerbeam2bcf5772014-06-25 18:05:44 -0700153void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
Steve Longerbeam4fd1a072014-06-25 18:05:45 -0700154int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
Sascha Hauerfb822a32013-10-10 16:18:41 +0200155int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200156
157void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
158 bool doublebuffer);
Philipp Zabele9046092012-05-16 17:28:29 +0200159int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
Steve Longerbeamaa52f572014-06-25 18:05:40 -0700160bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200161void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
Steve Longerbeambce6f082014-06-25 18:05:41 -0700162void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200163
164/*
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700165 * IPU Channel Parameter Memory (cpmem) functions
166 */
167struct ipu_rgb {
168 struct fb_bitfield red;
169 struct fb_bitfield green;
170 struct fb_bitfield blue;
171 struct fb_bitfield transp;
172 int bits_per_pixel;
173};
174
175struct ipu_image {
176 struct v4l2_pix_format pix;
177 struct v4l2_rect rect;
Steve Longerbeam2094b602014-06-25 18:05:52 -0700178 dma_addr_t phys0;
179 dma_addr_t phys1;
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700180};
181
182void ipu_cpmem_zero(struct ipuv3_channel *ch);
183void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
184void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
185void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
186void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
187void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
Steve Longerbeam555f0e62014-06-25 18:05:50 -0700188void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700189void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
Steve Longerbeam9b9da0b2014-06-25 18:05:49 -0700190void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
Steve Longerbeamc42d37ca2014-06-25 18:05:51 -0700191void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
192 enum ipu_rotate_mode rot);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700193int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
194 const struct ipu_rgb *rgb);
195int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
196void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
197void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
Philipp Zabel90195c32016-02-23 10:22:50 +0100198 unsigned int uv_stride,
199 unsigned int u_offset,
200 unsigned int v_offset);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700201void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
202 u32 pixel_format, int stride, int height);
203int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
204int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
Steve Longerbeam60c04452014-06-25 18:05:54 -0700205void ipu_cpmem_dump(struct ipuv3_channel *ch);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700206
207/*
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200208 * IPU Display Controller (dc) functions
209 */
210struct ipu_dc;
211struct ipu_di;
212struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
213void ipu_dc_put(struct ipu_dc *dc);
214int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
215 u32 pixel_fmt, u32 width);
Philipp Zabel1e6d4862014-04-14 23:53:23 +0200216void ipu_dc_enable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200217void ipu_dc_enable_channel(struct ipu_dc *dc);
218void ipu_dc_disable_channel(struct ipu_dc *dc);
Philipp Zabel1e6d4862014-04-14 23:53:23 +0200219void ipu_dc_disable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200220
221/*
222 * IPU Display Interface (di) functions
223 */
224struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
225void ipu_di_put(struct ipu_di *);
226int ipu_di_disable(struct ipu_di *);
227int ipu_di_enable(struct ipu_di *);
228int ipu_di_get_num(struct ipu_di *);
Jiada Wang6541d712014-12-18 18:00:20 -0800229int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200230int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
231
232/*
233 * IPU Display Multi FIFO Controller (dmfc) functions
234 */
235struct dmfc_channel;
236int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
237void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
238int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
239 unsigned long bandwidth_mbs, int burstsize);
240void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
Liu Ying27630c22016-03-14 16:10:10 +0800241void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200242struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
243void ipu_dmfc_put(struct dmfc_channel *dmfc);
244
245/*
246 * IPU Display Processor (dp) functions
247 */
248#define IPU_DP_FLOW_SYNC_BG 0
249#define IPU_DP_FLOW_SYNC_FG 1
250#define IPU_DP_FLOW_ASYNC0_BG 2
251#define IPU_DP_FLOW_ASYNC0_FG 3
252#define IPU_DP_FLOW_ASYNC1_BG 4
253#define IPU_DP_FLOW_ASYNC1_FG 5
254
255struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
256void ipu_dp_put(struct ipu_dp *);
Philipp Zabel285bbb02014-04-14 23:53:20 +0200257int ipu_dp_enable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200258int ipu_dp_enable_channel(struct ipu_dp *dp);
259void ipu_dp_disable_channel(struct ipu_dp *dp);
Philipp Zabel285bbb02014-04-14 23:53:20 +0200260void ipu_dp_disable(struct ipu_soc *ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200261int ipu_dp_setup_channel(struct ipu_dp *dp,
262 enum ipu_color_space in, enum ipu_color_space out);
263int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
264int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
265 bool bg_chan);
266
Philipp Zabel35de9252012-05-09 16:59:01 +0200267/*
Philipp Zabel3f5a8a92012-05-22 17:08:48 +0200268 * IPU CMOS Sensor Interface (csi) functions
269 */
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700270struct ipu_csi;
271int ipu_csi_init_interface(struct ipu_csi *csi,
272 struct v4l2_mbus_config *mbus_cfg,
273 struct v4l2_mbus_framefmt *mbus_fmt);
274bool ipu_csi_is_interlaced(struct ipu_csi *csi);
275void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
276void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
277void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
278 u32 r_value, u32 g_value, u32 b_value,
279 u32 pix_clk);
280int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
281 struct v4l2_mbus_framefmt *mbus_fmt);
282int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
283 u32 max_ratio, u32 id);
284int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
285int ipu_csi_enable(struct ipu_csi *csi);
286int ipu_csi_disable(struct ipu_csi *csi);
287struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
288void ipu_csi_put(struct ipu_csi *csi);
289void ipu_csi_dump(struct ipu_csi *csi);
Philipp Zabel3f5a8a92012-05-22 17:08:48 +0200290
291/*
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200292 * IPU Image Converter (ic) functions
293 */
294enum ipu_ic_task {
295 IC_TASK_ENCODER,
296 IC_TASK_VIEWFINDER,
297 IC_TASK_POST_PROCESSOR,
298 IC_NUM_TASKS,
299};
300
301struct ipu_ic;
302int ipu_ic_task_init(struct ipu_ic *ic,
303 int in_width, int in_height,
304 int out_width, int out_height,
305 enum ipu_color_space in_cs,
306 enum ipu_color_space out_cs);
307int ipu_ic_task_graphics_init(struct ipu_ic *ic,
308 enum ipu_color_space in_g_cs,
309 bool galpha_en, u32 galpha,
310 bool colorkey_en, u32 colorkey);
311void ipu_ic_task_enable(struct ipu_ic *ic);
312void ipu_ic_task_disable(struct ipu_ic *ic);
313int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
314 u32 width, u32 height, int burst_size,
315 enum ipu_rotate_mode rot);
316int ipu_ic_enable(struct ipu_ic *ic);
317int ipu_ic_disable(struct ipu_ic *ic);
318struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
319void ipu_ic_put(struct ipu_ic *ic);
320void ipu_ic_dump(struct ipu_ic *ic);
321
322/*
Philipp Zabel35de9252012-05-09 16:59:01 +0200323 * IPU Sensor Multiple FIFO Controller (SMFC) functions
324 */
Steve Longerbeam7fafa8f2014-06-25 18:05:34 -0700325struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
326void ipu_smfc_put(struct ipu_smfc *smfc);
327int ipu_smfc_enable(struct ipu_smfc *smfc);
328int ipu_smfc_disable(struct ipu_smfc *smfc);
329int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
330int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
Steve Longerbeama2be35e2014-06-25 18:05:35 -0700331int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
Philipp Zabel35de9252012-05-09 16:59:01 +0200332
Philipp Zabel7cb17792013-10-10 16:18:38 +0200333enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200334enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
Steve Longerbeamae0e9702014-06-25 18:05:36 -0700335enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
Steve Longerbeam6930afd2014-06-25 18:05:43 -0700336int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
Steve Longerbeam4cea9402014-06-25 18:05:38 -0700337bool ipu_pixelformat_is_planar(u32 pixelformat);
Steve Longerbeamf835f382014-06-25 18:05:37 -0700338int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
339 bool hflip, bool vflip);
340int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
341 bool hflip, bool vflip);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200342
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200343struct ipu_client_platformdata {
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +0200344 int csi;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200345 int di;
346 int dc;
347 int dp;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200348 int dma[2];
Philipp Zabel310944d2016-05-12 15:00:44 +0200349 struct device_node *of_node;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200350};
351
352#endif /* __DRM_IPU_H__ */