blob: 835563c1f0edf65e5fbf5545aa039738046d48f4 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/radeon_drm.h>
Marek Olšák6759a0a2012-08-09 16:34:17 +020031#include "radeon_asic.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100033#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Dave Airlie10ebc0b2012-09-17 14:40:31 +100035#include <linux/pm_runtime.h>
Alex Deucher78488652014-03-11 15:02:30 -040036
Oded Gabbaye28740e2014-07-15 13:53:32 +030037#include "radeon_kfd.h"
38
Alex Deucher78488652014-03-11 15:02:30 -040039#if defined(CONFIG_VGA_SWITCHEROO)
Alex Deucher90c4cde2014-04-10 22:29:01 -040040bool radeon_has_atpx(void);
Alex Deucher78488652014-03-11 15:02:30 -040041#else
Alex Deucher90c4cde2014-04-10 22:29:01 -040042static inline bool radeon_has_atpx(void) { return false; }
Alex Deucher78488652014-03-11 15:02:30 -040043#endif
44
Alex Deucherf482a142012-07-17 14:02:34 -040045/**
46 * radeon_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * It calls radeon_modeset_fini() to tear down the
52 * displays, and radeon_device_fini() to tear down
53 * the rest of the device (CP, writeback, etc.).
54 * Returns 0 on success.
55 */
Jerome Glissecf0fe452009-12-09 18:21:55 +010056int radeon_driver_unload_kms(struct drm_device *dev)
57{
58 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020059
Jerome Glissecf0fe452009-12-09 18:21:55 +010060 if (rdev == NULL)
61 return 0;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100062
Alex Deucher0cd9cb72013-04-12 19:15:52 -040063 if (rdev->rmmio == NULL)
64 goto done_free;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100065
Lukas Wunner19de6592016-06-08 18:47:27 +020066 if (radeon_is_px(dev)) {
67 pm_runtime_get_sync(dev->dev);
Lukas Wunner8fecb6a2016-06-08 18:47:27 +020068 pm_runtime_forbid(dev->dev);
Lukas Wunner19de6592016-06-08 18:47:27 +020069 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +100070
Oded Gabbaye28740e2014-07-15 13:53:32 +030071 radeon_kfd_device_fini(rdev);
72
Alex Deucherc4917072012-07-31 17:14:35 -040073 radeon_acpi_fini(rdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +100074
Jerome Glissecf0fe452009-12-09 18:21:55 +010075 radeon_modeset_fini(rdev);
76 radeon_device_fini(rdev);
Alex Deucher0cd9cb72013-04-12 19:15:52 -040077
78done_free:
Jerome Glissecf0fe452009-12-09 18:21:55 +010079 kfree(rdev);
80 dev->dev_private = NULL;
81 return 0;
82}
83
Alex Deucherf482a142012-07-17 14:02:34 -040084/**
85 * radeon_driver_load_kms - Main load function for KMS.
86 *
87 * @dev: drm dev pointer
88 * @flags: device flags
89 *
90 * This is the main load function for KMS (all asics).
91 * It calls radeon_device_init() to set up the non-display
92 * parts of the chip (asic init, CP, writeback, etc.), and
93 * radeon_modeset_init() to set up the display parts
94 * (crtcs, encoders, hotplug detect, etc.).
95 * Returns 0 on success, error on failure.
96 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020097int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
98{
99 struct radeon_device *rdev;
Alberto Miloned7a29522010-07-06 11:40:24 -0400100 int r, acpi_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200101
102 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
103 if (rdev == NULL) {
104 return -ENOMEM;
105 }
106 dev->dev_private = (void *)rdev;
107
108 /* update BUS flag */
Dave Airlie8410ea32010-12-15 03:16:38 +1000109 if (drm_pci_device_is_agp(dev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200110 flags |= RADEON_IS_AGP;
Jon Mason58b65422011-06-27 16:07:50 +0000111 } else if (pci_is_pcie(dev->pdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200112 flags |= RADEON_IS_PCIE;
113 } else {
114 flags |= RADEON_IS_PCI;
115 }
116
Alex Deucher73acacc2014-04-15 12:44:35 -0400117 if ((radeon_runtime_pm != 0) &&
118 radeon_has_atpx() &&
119 ((flags & RADEON_IS_IGP) == 0))
Alex Deucher90c4cde2014-04-10 22:29:01 -0400120 flags |= RADEON_IS_PX;
121
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200122 /* radeon_device_init should report only fatal error
123 * like memory allocation failure or iomapping failure,
124 * or memory manager initialization failure, it must
125 * properly initialize the GPU MC controller and permit
126 * VRAM allocation
127 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200128 r = radeon_device_init(rdev, dev, dev->pdev, flags);
129 if (r) {
Jerome Glissecf0fe452009-12-09 18:21:55 +0100130 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
131 goto out;
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200132 }
Alberto Miloned7a29522010-07-06 11:40:24 -0400133
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200134 /* Again modeset_init should fail only on fatal error
135 * otherwise it should provide enough functionalities
136 * for shadowfb to run
137 */
138 r = radeon_modeset_init(rdev);
Jerome Glissecf0fe452009-12-09 18:21:55 +0100139 if (r)
140 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
Luca Tettamantifda4b252012-07-30 21:20:35 +0200141
142 /* Call ACPI methods: require modeset init
143 * but failure is not fatal
144 */
145 if (!r) {
146 acpi_status = radeon_acpi_init(rdev);
147 if (acpi_status)
148 dev_dbg(&dev->pdev->dev,
149 "Error during ACPI methods call\n");
150 }
151
Oded Gabbaye28740e2014-07-15 13:53:32 +0300152 radeon_kfd_device_probe(rdev);
153 radeon_kfd_device_init(rdev);
154
Alex Deucher90c4cde2014-04-10 22:29:01 -0400155 if (radeon_is_px(dev)) {
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000156 pm_runtime_use_autosuspend(dev->dev);
157 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
158 pm_runtime_set_active(dev->dev);
159 pm_runtime_allow(dev->dev);
160 pm_runtime_mark_last_busy(dev->dev);
161 pm_runtime_put_autosuspend(dev->dev);
162 }
163
Jerome Glissecf0fe452009-12-09 18:21:55 +0100164out:
165 if (r)
166 radeon_driver_unload_kms(dev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000167
168
Jerome Glissecf0fe452009-12-09 18:21:55 +0100169 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170}
171
Alex Deucherf482a142012-07-17 14:02:34 -0400172/**
173 * radeon_set_filp_rights - Set filp right.
174 *
175 * @dev: drm dev pointer
176 * @owner: drm file
177 * @applier: drm file
178 * @value: value
179 *
180 * Sets the filp rights for the device (all asics).
181 */
Marek Olšák9eba4a92011-01-05 05:46:48 +0100182static void radeon_set_filp_rights(struct drm_device *dev,
183 struct drm_file **owner,
184 struct drm_file *applier,
185 uint32_t *value)
186{
Daniel Vetter45c1da52015-10-15 09:36:34 +0200187 struct radeon_device *rdev = dev->dev_private;
188
189 mutex_lock(&rdev->gem.mutex);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100190 if (*value == 1) {
191 /* wants rights */
192 if (!*owner)
193 *owner = applier;
194 } else if (*value == 0) {
195 /* revokes rights */
196 if (*owner == applier)
197 *owner = NULL;
198 }
199 *value = *owner == applier ? 1 : 0;
Daniel Vetter45c1da52015-10-15 09:36:34 +0200200 mutex_unlock(&rdev->gem.mutex);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100201}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200202
203/*
Marek Olšák9eba4a92011-01-05 05:46:48 +0100204 * Userspace get information ioctl
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205 */
Alex Deucherf482a142012-07-17 14:02:34 -0400206/**
207 * radeon_info_ioctl - answer a device specific request.
208 *
209 * @rdev: radeon device pointer
210 * @data: request object
211 * @filp: drm filp
212 *
213 * This function is used to pass device specific parameters to the userspace
214 * drivers. Examples include: pci device id, pipeline parms, tiling params,
215 * etc. (all asics).
216 * Returns 0 on success, -EINVAL on failure.
217 */
Rashika Kheria55203452014-01-06 20:53:07 +0530218static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219{
220 struct radeon_device *rdev = dev->dev_private;
Marek Olšák6759a0a2012-08-09 16:34:17 +0200221 struct drm_radeon_info *info = data;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200222 struct radeon_mode_info *minfo = &rdev->mode_info;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400223 uint32_t *value, value_tmp, *value_ptr, value_size;
224 uint64_t value64;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200225 struct drm_crtc *crtc;
226 int i, found;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200227
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228 value_ptr = (uint32_t *)((unsigned long)info->value);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400229 value = &value_tmp;
230 value_size = sizeof(uint32_t);
Dr. David Alan Gilbertd8ab3552010-08-02 09:43:52 +1000231
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200232 switch (info->request) {
233 case RADEON_INFO_DEVICE_ID:
Ville Syrjäläffbab09b2013-10-04 14:53:40 +0300234 *value = dev->pdev->device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235 break;
236 case RADEON_INFO_NUM_GB_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400237 *value = rdev->num_gb_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200238 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400239 case RADEON_INFO_NUM_Z_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400240 *value = rdev->num_z_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400241 break;
Jerome Glisse733289c2009-09-16 15:24:21 +0200242 case RADEON_INFO_ACCEL_WORKING:
Alex Deucher148a03b2010-06-03 19:00:03 -0400243 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
244 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400245 *value = false;
Alex Deucher148a03b2010-06-03 19:00:03 -0400246 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400247 *value = rdev->accel_working;
Jerome Glisse733289c2009-09-16 15:24:21 +0200248 break;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200249 case RADEON_INFO_CRTC_FROM_ID:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100250 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400251 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
252 return -EFAULT;
253 }
Jerome Glissebc35afd2010-05-12 18:01:13 +0200254 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
255 crtc = (struct drm_crtc *)minfo->crtcs[i];
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400256 if (crtc && crtc->base.id == *value) {
Alex Deucher0baf2d82010-07-21 14:05:35 -0400257 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400258 *value = radeon_crtc->crtc_id;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200259 found = 1;
260 break;
261 }
262 }
263 if (!found) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400264 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
Jerome Glissebc35afd2010-05-12 18:01:13 +0200265 return -EINVAL;
266 }
267 break;
Alex Deucher148a03b2010-06-03 19:00:03 -0400268 case RADEON_INFO_ACCEL_WORKING2:
Alex Deucher3c64bd22014-08-01 20:05:30 +0200269 if (rdev->family == CHIP_HAWAII) {
Andreas Boll9eb401a2014-08-01 20:05:32 +0200270 if (rdev->accel_working) {
271 if (rdev->new_fw)
272 *value = 3;
273 else
274 *value = 2;
275 } else {
Alex Deucher3c64bd22014-08-01 20:05:30 +0200276 *value = 0;
Andreas Boll9eb401a2014-08-01 20:05:32 +0200277 }
Alex Deucher3c64bd22014-08-01 20:05:30 +0200278 } else {
279 *value = rdev->accel_working;
280 }
Alex Deucher148a03b2010-06-03 19:00:03 -0400281 break;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400282 case RADEON_INFO_TILING_CONFIG:
Alex Deucher64f759c2012-07-06 17:40:32 -0400283 if (rdev->family >= CHIP_BONAIRE)
284 *value = rdev->config.cik.tile_config;
285 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400286 *value = rdev->config.si.tile_config;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400287 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400288 *value = rdev->config.cayman.tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -0500289 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400290 *value = rdev->config.evergreen.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400291 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400292 *value = rdev->config.rv770.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400293 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400294 *value = rdev->config.r600.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400295 else {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000296 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400297 return -EINVAL;
298 }
Alex Deucherb824b362010-08-12 08:25:47 -0400299 break;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000300 case RADEON_INFO_WANT_HYPERZ:
Marek Olšák43861f72010-08-07 03:36:34 +0200301 /* The "value" here is both an input and output parameter.
302 * If the input value is 1, filp requests hyper-z access.
303 * If the input value is 0, filp revokes its hyper-z access.
304 *
305 * When returning, the value is 1 if filp owns hyper-z access,
306 * 0 otherwise. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100307 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400308 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
309 return -EFAULT;
310 }
311 if (*value >= 2) {
312 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
Marek Olšák43861f72010-08-07 03:36:34 +0200313 return -EINVAL;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000314 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400315 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100316 break;
317 case RADEON_INFO_WANT_CMASK:
318 /* The same logic as Hyper-Z. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100319 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400320 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
321 return -EFAULT;
322 }
323 if (*value >= 2) {
324 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100325 return -EINVAL;
Marek Olšák43861f72010-08-07 03:36:34 +0200326 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400327 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400328 break;
Alex Deucher58bbf012011-01-24 17:14:26 -0500329 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
330 /* return clock value in KHz */
Alex Deucher454d2e22013-02-14 10:04:02 -0500331 if (rdev->asic->get_xclk)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400332 *value = radeon_get_xclk(rdev) * 10;
Alex Deucher454d2e22013-02-14 10:04:02 -0500333 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400334 *value = rdev->clock.spll.reference_freq * 10;
Alex Deucher58bbf012011-01-24 17:14:26 -0500335 break;
Dave Airlie486af182011-03-01 14:32:27 +1000336 case RADEON_INFO_NUM_BACKENDS:
Alex Deucher64f759c2012-07-06 17:40:32 -0400337 if (rdev->family >= CHIP_BONAIRE)
338 *value = rdev->config.cik.max_backends_per_se *
339 rdev->config.cik.max_shader_engines;
340 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400341 *value = rdev->config.si.max_backends_per_se *
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400342 rdev->config.si.max_shader_engines;
343 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400344 *value = rdev->config.cayman.max_backends_per_se *
Alex Deucherfecf1d02011-03-02 20:07:29 -0500345 rdev->config.cayman.max_shader_engines;
346 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400347 *value = rdev->config.evergreen.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000348 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400349 *value = rdev->config.rv770.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000350 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400351 *value = rdev->config.r600.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000352 else {
353 return -EINVAL;
354 }
355 break;
Alex Deucher65659452011-04-26 13:27:43 -0400356 case RADEON_INFO_NUM_TILE_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400357 if (rdev->family >= CHIP_BONAIRE)
358 *value = rdev->config.cik.max_tile_pipes;
359 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400360 *value = rdev->config.si.max_tile_pipes;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400361 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400362 *value = rdev->config.cayman.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400363 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400364 *value = rdev->config.evergreen.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400365 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400366 *value = rdev->config.rv770.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400367 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400368 *value = rdev->config.r600.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400369 else {
370 return -EINVAL;
371 }
372 break;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400373 case RADEON_INFO_FUSION_GART_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400374 *value = 1;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400375 break;
Alex Deuchere55b9422011-07-15 19:53:52 +0000376 case RADEON_INFO_BACKEND_MAP:
Alex Deucher64f759c2012-07-06 17:40:32 -0400377 if (rdev->family >= CHIP_BONAIRE)
Michel Dänzer1ddce272013-11-18 18:25:59 +0900378 *value = rdev->config.cik.backend_map;
Alex Deucher64f759c2012-07-06 17:40:32 -0400379 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400380 *value = rdev->config.si.backend_map;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400381 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400382 *value = rdev->config.cayman.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000383 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400384 *value = rdev->config.evergreen.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000385 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400386 *value = rdev->config.rv770.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000387 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400388 *value = rdev->config.r600.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000389 else {
390 return -EINVAL;
391 }
392 break;
Jerome Glisse721604a2012-01-05 22:11:05 -0500393 case RADEON_INFO_VA_START:
394 /* this is where we report if vm is supported or not */
395 if (rdev->family < CHIP_CAYMAN)
396 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400397 *value = RADEON_VA_RESERVED_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500398 break;
399 case RADEON_INFO_IB_VM_MAX_SIZE:
400 /* this is where we report if vm is supported or not */
401 if (rdev->family < CHIP_CAYMAN)
402 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400403 *value = RADEON_IB_VM_MAX_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500404 break;
Tom Stellard609c1e12012-03-20 17:17:55 -0400405 case RADEON_INFO_MAX_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400406 if (rdev->family >= CHIP_BONAIRE)
407 *value = rdev->config.cik.max_cu_per_sh;
408 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400409 *value = rdev->config.si.max_cu_per_sh;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400410 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400411 *value = rdev->config.cayman.max_pipes_per_simd;
Tom Stellard609c1e12012-03-20 17:17:55 -0400412 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400413 *value = rdev->config.evergreen.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400414 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400415 *value = rdev->config.rv770.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400416 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400417 *value = rdev->config.r600.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400418 else {
419 return -EINVAL;
420 }
421 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400422 case RADEON_INFO_TIMESTAMP:
423 if (rdev->family < CHIP_R600) {
424 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
425 return -EINVAL;
426 }
427 value = (uint32_t*)&value64;
428 value_size = sizeof(uint64_t);
429 value64 = radeon_get_gpu_clock_counter(rdev);
430 break;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500431 case RADEON_INFO_MAX_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400432 if (rdev->family >= CHIP_BONAIRE)
433 *value = rdev->config.cik.max_shader_engines;
434 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400435 *value = rdev->config.si.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500436 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400437 *value = rdev->config.cayman.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500438 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400439 *value = rdev->config.evergreen.num_ses;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500440 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400441 *value = 1;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500442 break;
443 case RADEON_INFO_MAX_SH_PER_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400444 if (rdev->family >= CHIP_BONAIRE)
445 *value = rdev->config.cik.max_sh_per_se;
446 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400447 *value = rdev->config.si.max_sh_per_se;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500448 else
449 return -EINVAL;
450 break;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400451 case RADEON_INFO_FASTFB_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400452 *value = rdev->fastfb_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400453 break;
Christian König902aaef2013-04-09 10:35:42 -0400454 case RADEON_INFO_RING_WORKING:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100455 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400456 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
457 return -EFAULT;
458 }
459 switch (*value) {
Christian König902aaef2013-04-09 10:35:42 -0400460 case RADEON_CS_RING_GFX:
461 case RADEON_CS_RING_COMPUTE:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400462 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400463 break;
464 case RADEON_CS_RING_DMA:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400465 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
466 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400467 break;
468 case RADEON_CS_RING_UVD:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400469 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400470 break;
Christian Königf7ba8b02014-01-27 10:16:06 -0700471 case RADEON_CS_RING_VCE:
472 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
473 break;
Christian König902aaef2013-04-09 10:35:42 -0400474 default:
475 return -EINVAL;
476 }
477 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400478 case RADEON_INFO_SI_TILE_MODE_ARRAY:
Alex Deucher64f759c2012-07-06 17:40:32 -0400479 if (rdev->family >= CHIP_BONAIRE) {
Alex Deucher39aee492013-04-10 13:41:25 -0400480 value = rdev->config.cik.tile_mode_array;
481 value_size = sizeof(uint32_t)*32;
482 } else if (rdev->family >= CHIP_TAHITI) {
483 value = rdev->config.si.tile_mode_array;
484 value_size = sizeof(uint32_t)*32;
485 } else {
486 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
Alex Deucher64f759c2012-07-06 17:40:32 -0400487 return -EINVAL;
488 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400489 break;
Michel Dänzer32f79a82013-11-18 18:26:00 +0900490 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
491 if (rdev->family >= CHIP_BONAIRE) {
492 value = rdev->config.cik.macrotile_mode_array;
493 value_size = sizeof(uint32_t)*16;
494 } else {
495 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
496 return -EINVAL;
497 }
498 break;
Tom Stellarde5b9e752013-08-16 17:47:39 -0400499 case RADEON_INFO_SI_CP_DMA_COMPUTE:
500 *value = 1;
501 break;
Marek Olšák439a1cf2013-12-22 02:18:01 +0100502 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
503 if (rdev->family >= CHIP_BONAIRE) {
504 *value = rdev->config.cik.backend_enable_mask;
505 } else if (rdev->family >= CHIP_TAHITI) {
506 *value = rdev->config.si.backend_enable_mask;
507 } else {
508 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
509 }
510 break;
Alex Deucherf5f1f892014-01-20 18:20:29 -0500511 case RADEON_INFO_MAX_SCLK:
512 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
513 rdev->pm.dpm_enabled)
514 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
515 else
516 *value = rdev->pm.default_sclk * 10;
517 break;
Christian König98ccc292014-01-23 09:50:49 -0700518 case RADEON_INFO_VCE_FW_VERSION:
519 *value = rdev->vce.fw_version;
520 break;
521 case RADEON_INFO_VCE_FB_VERSION:
522 *value = rdev->vce.fb_version;
523 break;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100524 case RADEON_INFO_NUM_BYTES_MOVED:
525 value = (uint32_t*)&value64;
526 value_size = sizeof(uint64_t);
527 value64 = atomic64_read(&rdev->num_bytes_moved);
528 break;
529 case RADEON_INFO_VRAM_USAGE:
530 value = (uint32_t*)&value64;
531 value_size = sizeof(uint64_t);
532 value64 = atomic64_read(&rdev->vram_usage);
533 break;
534 case RADEON_INFO_GTT_USAGE:
535 value = (uint32_t*)&value64;
536 value_size = sizeof(uint64_t);
537 value64 = atomic64_read(&rdev->gtt_usage);
538 break;
Alex Deucher65fcf662014-06-02 16:13:21 -0400539 case RADEON_INFO_ACTIVE_CU_COUNT:
540 if (rdev->family >= CHIP_BONAIRE)
541 *value = rdev->config.cik.active_cus;
542 else if (rdev->family >= CHIP_TAHITI)
543 *value = rdev->config.si.active_cus;
544 else if (rdev->family >= CHIP_CAYMAN)
545 *value = rdev->config.cayman.active_simds;
546 else if (rdev->family >= CHIP_CEDAR)
547 *value = rdev->config.evergreen.active_simds;
548 else if (rdev->family >= CHIP_RV770)
549 *value = rdev->config.rv770.active_simds;
550 else if (rdev->family >= CHIP_R600)
551 *value = rdev->config.r600.active_simds;
552 else
553 *value = 1;
554 break;
Alex Deucherd6d2a182014-09-30 10:04:40 -0400555 case RADEON_INFO_CURRENT_GPU_TEMP:
556 /* get temperature in millidegrees C */
557 if (rdev->asic->pm.get_temperature)
558 *value = radeon_get_temperature(rdev);
559 else
560 *value = 0;
561 break;
Alex Deucher5c363a82014-09-30 11:33:30 -0400562 case RADEON_INFO_CURRENT_GPU_SCLK:
563 /* get sclk in Mhz */
564 if (rdev->pm.dpm_enabled)
565 *value = radeon_dpm_get_current_sclk(rdev) / 100;
566 else
567 *value = rdev->pm.current_sclk / 100;
568 break;
569 case RADEON_INFO_CURRENT_GPU_MCLK:
570 /* get mclk in Mhz */
571 if (rdev->pm.dpm_enabled)
572 *value = radeon_dpm_get_current_mclk(rdev) / 100;
573 else
574 *value = rdev->pm.current_mclk / 100;
575 break;
Alex Deucher4535cb92014-10-01 11:26:50 -0400576 case RADEON_INFO_READ_REG:
577 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
578 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
579 return -EFAULT;
580 }
581 if (radeon_get_allowed_info_register(rdev, *value, value))
582 return -EINVAL;
583 break;
Michel Dänzer3bc980b2015-06-16 17:28:16 +0900584 case RADEON_INFO_VA_UNMAP_WORKING:
585 *value = true;
586 break;
Marek Olšák72b90762015-04-29 19:40:33 +0200587 case RADEON_INFO_GPU_RESET_COUNTER:
588 *value = atomic_read(&rdev->gpu_reset_counter);
589 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200590 default:
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000591 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200592 return -EINVAL;
593 }
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100594 if (copy_to_user(value_ptr, (char*)value, value_size)) {
Marek Olšák6759a0a2012-08-09 16:34:17 +0200595 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200596 return -EFAULT;
597 }
598 return 0;
599}
600
601
602/*
603 * Outdated mess for old drm with Xorg being in charge (void function now).
604 */
Alex Deucherf482a142012-07-17 14:02:34 -0400605/**
Alex Deucher8c70e1c2015-10-02 16:52:58 -0400606 * radeon_driver_lastclose_kms - drm callback for last close
Alex Deucherf482a142012-07-17 14:02:34 -0400607 *
608 * @dev: drm dev pointer
609 *
Lukas Wunner8e5de1d2015-09-05 11:14:43 +0200610 * Switch vga_switcheroo state after last close (all asics).
Alex Deucherf482a142012-07-17 14:02:34 -0400611 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200612void radeon_driver_lastclose_kms(struct drm_device *dev)
613{
Alex Deucher8c70e1c2015-10-02 16:52:58 -0400614 struct radeon_device *rdev = dev->dev_private;
615
616 radeon_fbdev_restore_mode(rdev);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000617 vga_switcheroo_process_delayed_switch();
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200618}
619
Alex Deucherf482a142012-07-17 14:02:34 -0400620/**
621 * radeon_driver_open_kms - drm callback for open
622 *
623 * @dev: drm dev pointer
624 * @file_priv: drm file
625 *
626 * On device open, init vm on cayman+ (all asics).
627 * Returns 0 on success, error on failure.
628 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200629int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
630{
Jerome Glisse721604a2012-01-05 22:11:05 -0500631 struct radeon_device *rdev = dev->dev_private;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000632 int r;
Jerome Glisse721604a2012-01-05 22:11:05 -0500633
634 file_priv->driver_priv = NULL;
635
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000636 r = pm_runtime_get_sync(dev->dev);
637 if (r < 0)
638 return r;
639
Jerome Glisse721604a2012-01-05 22:11:05 -0500640 /* new gpu have virtual address space support */
641 if (rdev->family >= CHIP_CAYMAN) {
642 struct radeon_fpriv *fpriv;
Christian Königcc9e67e2014-07-18 13:48:10 +0200643 struct radeon_vm *vm;
Jerome Glisse721604a2012-01-05 22:11:05 -0500644 int r;
645
646 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
647 if (unlikely(!fpriv)) {
648 return -ENOMEM;
649 }
650
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400651 if (rdev->accel_working) {
Alex Deucher544143f2015-01-28 14:36:26 -0500652 vm = &fpriv->vm;
653 r = radeon_vm_init(rdev, vm);
654 if (r) {
655 kfree(fpriv);
656 return r;
657 }
658
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400659 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
660 if (r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200661 radeon_vm_fini(rdev, vm);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400662 kfree(fpriv);
663 return r;
664 }
665
666 /* map the ib pool buffer read only into
667 * virtual address space */
Christian Königcc9e67e2014-07-18 13:48:10 +0200668 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
669 rdev->ring_tmp_bo.bo);
670 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
671 RADEON_VA_IB_OFFSET,
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400672 RADEON_VM_PAGE_READABLE |
673 RADEON_VM_PAGE_SNOOPED);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400674 if (r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200675 radeon_vm_fini(rdev, vm);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400676 kfree(fpriv);
677 return r;
678 }
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100679 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500680 file_priv->driver_priv = fpriv;
681 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000682
683 pm_runtime_mark_last_busy(dev->dev);
684 pm_runtime_put_autosuspend(dev->dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200685 return 0;
686}
687
Alex Deucherf482a142012-07-17 14:02:34 -0400688/**
689 * radeon_driver_postclose_kms - drm callback for post close
690 *
691 * @dev: drm dev pointer
692 * @file_priv: drm file
693 *
694 * On device post close, tear down vm on cayman+ (all asics).
695 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200696void radeon_driver_postclose_kms(struct drm_device *dev,
697 struct drm_file *file_priv)
698{
Jerome Glisse721604a2012-01-05 22:11:05 -0500699 struct radeon_device *rdev = dev->dev_private;
700
701 /* new gpu have virtual address space support */
702 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
703 struct radeon_fpriv *fpriv = file_priv->driver_priv;
Christian Königcc9e67e2014-07-18 13:48:10 +0200704 struct radeon_vm *vm = &fpriv->vm;
Christian Königd72d43c2012-10-09 13:31:18 +0200705 int r;
706
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400707 if (rdev->accel_working) {
708 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
709 if (!r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200710 if (vm->ib_bo_va)
711 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400712 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
713 }
Alex Deucher544143f2015-01-28 14:36:26 -0500714 radeon_vm_fini(rdev, vm);
Christian Königd72d43c2012-10-09 13:31:18 +0200715 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500716
Jerome Glisse721604a2012-01-05 22:11:05 -0500717 kfree(fpriv);
718 file_priv->driver_priv = NULL;
719 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200720}
721
Alex Deucherf482a142012-07-17 14:02:34 -0400722/**
723 * radeon_driver_preclose_kms - drm callback for pre close
724 *
725 * @dev: drm dev pointer
726 * @file_priv: drm file
727 *
728 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
729 * (all asics).
730 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200731void radeon_driver_preclose_kms(struct drm_device *dev,
732 struct drm_file *file_priv)
733{
Dave Airlieab9e1f52010-07-13 11:11:11 +1000734 struct radeon_device *rdev = dev->dev_private;
Daniel Vetter45c1da52015-10-15 09:36:34 +0200735
736 mutex_lock(&rdev->gem.mutex);
Dave Airlieab9e1f52010-07-13 11:11:11 +1000737 if (rdev->hyperz_filp == file_priv)
738 rdev->hyperz_filp = NULL;
Marek Olšákdca0d612011-01-27 22:46:15 +0100739 if (rdev->cmask_filp == file_priv)
740 rdev->cmask_filp = NULL;
Daniel Vetter45c1da52015-10-15 09:36:34 +0200741 mutex_unlock(&rdev->gem.mutex);
742
Christian Königf2ba57b2013-04-08 12:41:29 +0200743 radeon_uvd_free_handles(rdev, file_priv);
Christian Königd93f7932013-05-23 12:10:04 +0200744 radeon_vce_free_handles(rdev, file_priv);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200745}
746
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200747/*
748 * VBlank related functions.
749 */
Alex Deucherf482a142012-07-17 14:02:34 -0400750/**
751 * radeon_get_vblank_counter_kms - get frame count
752 *
753 * @dev: drm dev pointer
Thierry Reding4e926d22015-12-16 15:31:47 +0100754 * @pipe: crtc to get the frame count from
Alex Deucherf482a142012-07-17 14:02:34 -0400755 *
756 * Gets the frame count on the requested crtc (all asics).
757 * Returns frame count on success, -EINVAL on failure.
758 */
Thierry Reding4e926d22015-12-16 15:31:47 +0100759u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200760{
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100761 int vpos, hpos, stat;
762 u32 count;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200763 struct radeon_device *rdev = dev->dev_private;
764
Thierry Reding85a21ea2016-01-04 18:19:12 +0100765 if (pipe >= rdev->num_crtc) {
Thierry Reding4e926d22015-12-16 15:31:47 +0100766 DRM_ERROR("Invalid crtc %u\n", pipe);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200767 return -EINVAL;
768 }
769
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100770 /* The hw increments its frame counter at start of vsync, not at start
771 * of vblank, as is required by DRM core vblank counter handling.
772 * Cook the hw count here to make it appear to the caller as if it
773 * incremented at start of vblank. We measure distance to start of
774 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
775 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
776 * result by 1 to give the proper appearance to caller.
777 */
Thierry Reding4e926d22015-12-16 15:31:47 +0100778 if (rdev->mode_info.crtcs[pipe]) {
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100779 /* Repeat readout if needed to provide stable result if
780 * we cross start of vsync during the queries.
781 */
782 do {
Thierry Reding4e926d22015-12-16 15:31:47 +0100783 count = radeon_get_vblank_counter(rdev, pipe);
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100784 /* Ask radeon_get_crtc_scanoutpos to return vpos as
785 * distance to start of vblank, instead of regular
786 * vertical scanout pos.
787 */
788 stat = radeon_get_crtc_scanoutpos(
Thierry Reding4e926d22015-12-16 15:31:47 +0100789 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100790 &vpos, &hpos, NULL, NULL,
Thierry Reding4e926d22015-12-16 15:31:47 +0100791 &rdev->mode_info.crtcs[pipe]->base.hwmode);
792 } while (count != radeon_get_vblank_counter(rdev, pipe));
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100793
794 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
795 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
796 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
797 }
798 else {
Thierry Reding4e926d22015-12-16 15:31:47 +0100799 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
800 pipe, vpos);
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100801
802 /* Bump counter if we are at >= leading edge of vblank,
803 * but before vsync where vpos would turn negative and
804 * the hw counter really increments.
805 */
806 if (vpos >= 0)
807 count++;
808 }
809 }
810 else {
811 /* Fallback to use value as is. */
Thierry Reding4e926d22015-12-16 15:31:47 +0100812 count = radeon_get_vblank_counter(rdev, pipe);
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100813 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
814 }
815
816 return count;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200817}
818
Alex Deucherf482a142012-07-17 14:02:34 -0400819/**
820 * radeon_enable_vblank_kms - enable vblank interrupt
821 *
822 * @dev: drm dev pointer
823 * @crtc: crtc to enable vblank interrupt for
824 *
825 * Enable the interrupt on the requested crtc (all asics).
826 * Returns 0 on success, -EINVAL on failure.
827 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200828int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
829{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200830 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200831 unsigned long irqflags;
832 int r;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200833
Dave Airlie9c950a42010-04-23 13:21:58 +1000834 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200835 DRM_ERROR("Invalid crtc %d\n", crtc);
836 return -EINVAL;
837 }
838
Christian Koenigfb982572012-05-17 01:33:30 +0200839 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200840 rdev->irq.crtc_vblank_int[crtc] = true;
Christian Koenigfb982572012-05-17 01:33:30 +0200841 r = radeon_irq_set(rdev);
842 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
843 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200844}
845
Alex Deucherf482a142012-07-17 14:02:34 -0400846/**
847 * radeon_disable_vblank_kms - disable vblank interrupt
848 *
849 * @dev: drm dev pointer
850 * @crtc: crtc to disable vblank interrupt for
851 *
852 * Disable the interrupt on the requested crtc (all asics).
853 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200854void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
855{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200856 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200857 unsigned long irqflags;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200858
Dave Airlie9c950a42010-04-23 13:21:58 +1000859 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200860 DRM_ERROR("Invalid crtc %d\n", crtc);
861 return;
862 }
863
Christian Koenigfb982572012-05-17 01:33:30 +0200864 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200865 rdev->irq.crtc_vblank_int[crtc] = false;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200866 radeon_irq_set(rdev);
Christian Koenigfb982572012-05-17 01:33:30 +0200867 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200868}
869
Alex Deucherf482a142012-07-17 14:02:34 -0400870/**
871 * radeon_get_vblank_timestamp_kms - get vblank timestamp
872 *
873 * @dev: drm dev pointer
874 * @crtc: crtc to get the timestamp for
875 * @max_error: max error
876 * @vblank_time: time value
877 * @flags: flags passed to the driver
878 *
879 * Gets the timestamp on the requested crtc based on the
880 * scanout position. (all asics).
881 * Returns postive status flags on success, negative error on failure.
882 */
Mario Kleinerf5a80202010-10-23 04:42:17 +0200883int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
884 int *max_error,
885 struct timeval *vblank_time,
886 unsigned flags)
887{
888 struct drm_crtc *drmcrtc;
889 struct radeon_device *rdev = dev->dev_private;
890
891 if (crtc < 0 || crtc >= dev->num_crtcs) {
892 DRM_ERROR("Invalid crtc %d\n", crtc);
893 return -EINVAL;
894 }
895
896 /* Get associated drm_crtc: */
897 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
Petr Mladekf5475cc2014-11-27 16:57:21 +0100898 if (!drmcrtc)
899 return -EINVAL;
Mario Kleinerf5a80202010-10-23 04:42:17 +0200900
901 /* Helper routine in DRM core does all the work: */
902 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
903 vblank_time, flags,
Ville Syrjäläeba1f352015-09-14 22:43:43 +0300904 &drmcrtc->hwmode);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200905}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200906
Rob Clarkbaa70942013-08-02 13:27:49 -0400907const struct drm_ioctl_desc radeon_ioctls_kms[] = {
Daniel Vetter4b635392015-09-08 13:56:26 +0200908 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
909 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
910 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
911 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
912 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
913 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
914 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
915 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
916 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
917 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
918 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
919 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
920 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
921 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
922 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
923 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
924 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
925 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
926 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
927 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
928 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
929 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
930 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
931 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
932 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
933 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
934 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200935 /* KMS */
Daniel Vetterf8c47142015-09-08 13:56:30 +0200936 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
937 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
938 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
939 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
940 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
941 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
942 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
943 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
944 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
945 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
946 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
947 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
948 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
949 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
950 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200951};
Damien Lespiauf95aeb12014-06-09 14:39:49 +0100952int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);