blob: 3493da5c8f0efcaef97f2b07145d91097665b703 [file] [log] [blame]
Alex Deuchera02860aa2015-04-20 16:44:53 -04001/*
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23
24/****************************************************************************/
25/*Portion I: Definitions shared between VBIOS and Driver */
26/****************************************************************************/
27
28#ifndef _ATOMBIOS_H
29#define _ATOMBIOS_H
30
31#define ATOM_VERSION_MAJOR 0x00020000
32#define ATOM_VERSION_MINOR 0x00000002
33
34#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
35
36/* Endianness should be specified before inclusion,
37 * default to little endian
38 */
39#ifndef ATOM_BIG_ENDIAN
40#error Endian not specified
41#endif
42
43#ifdef _H2INC
44 #ifndef ULONG
45 typedef unsigned long ULONG;
46 #endif
47
48 #ifndef UCHAR
49 typedef unsigned char UCHAR;
50 #endif
51
52 #ifndef USHORT
53 typedef unsigned short USHORT;
54 #endif
55#endif
56
57#define ATOM_DAC_A 0
58#define ATOM_DAC_B 1
59#define ATOM_EXT_DAC 2
60
61#define ATOM_CRTC1 0
62#define ATOM_CRTC2 1
63#define ATOM_CRTC3 2
64#define ATOM_CRTC4 3
65#define ATOM_CRTC5 4
66#define ATOM_CRTC6 5
67
68#define ATOM_UNDERLAY_PIPE0 16
69#define ATOM_UNDERLAY_PIPE1 17
70
71#define ATOM_CRTC_INVALID 0xFF
72
73#define ATOM_DIGA 0
74#define ATOM_DIGB 1
75
76#define ATOM_PPLL1 0
77#define ATOM_PPLL2 1
78#define ATOM_DCPLL 2
79#define ATOM_PPLL0 2
80#define ATOM_PPLL3 3
81
Alex Deucher6e14e92b2015-10-15 00:43:41 -040082#define ATOM_PHY_PLL0 4
83#define ATOM_PHY_PLL1 5
84
Alex Deuchera02860aa2015-04-20 16:44:53 -040085#define ATOM_EXT_PLL1 8
Alex Deucher6e14e92b2015-10-15 00:43:41 -040086#define ATOM_GCK_DFS 8
Alex Deuchera02860aa2015-04-20 16:44:53 -040087#define ATOM_EXT_PLL2 9
Alex Deucher6e14e92b2015-10-15 00:43:41 -040088#define ATOM_FCH_CLK 9
Alex Deuchera02860aa2015-04-20 16:44:53 -040089#define ATOM_EXT_CLOCK 10
Alex Deucher6e14e92b2015-10-15 00:43:41 -040090#define ATOM_DP_DTO 11
91
92#define ATOM_COMBOPHY_PLL0 20
93#define ATOM_COMBOPHY_PLL1 21
94#define ATOM_COMBOPHY_PLL2 22
95#define ATOM_COMBOPHY_PLL3 23
96#define ATOM_COMBOPHY_PLL4 24
97#define ATOM_COMBOPHY_PLL5 25
98
Alex Deuchera02860aa2015-04-20 16:44:53 -040099#define ATOM_PPLL_INVALID 0xFF
100
101#define ENCODER_REFCLK_SRC_P1PLL 0
102#define ENCODER_REFCLK_SRC_P2PLL 1
103#define ENCODER_REFCLK_SRC_DCPLL 2
104#define ENCODER_REFCLK_SRC_EXTCLK 3
105#define ENCODER_REFCLK_SRC_INVALID 0xFF
106
107#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
109#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
110#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios
111
112#define ATOM_DISABLE 0
113#define ATOM_ENABLE 1
114#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
115#define ATOM_LCD_BLON (ATOM_ENABLE+2)
116#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
117#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
118#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
119#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
120#define ATOM_INIT (ATOM_DISABLE+7)
121#define ATOM_GET_STATUS (ATOM_DISABLE+8)
122
123#define ATOM_BLANKING 1
124#define ATOM_BLANKING_OFF 0
125
126
127#define ATOM_CRT1 0
128#define ATOM_CRT2 1
129
130#define ATOM_TV_NTSC 1
131#define ATOM_TV_NTSCJ 2
132#define ATOM_TV_PAL 3
133#define ATOM_TV_PALM 4
134#define ATOM_TV_PALCN 5
135#define ATOM_TV_PALN 6
136#define ATOM_TV_PAL60 7
137#define ATOM_TV_SECAM 8
138#define ATOM_TV_CV 16
139
140#define ATOM_DAC1_PS2 1
141#define ATOM_DAC1_CV 2
142#define ATOM_DAC1_NTSC 3
143#define ATOM_DAC1_PAL 4
144
145#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
146#define ATOM_DAC2_CV ATOM_DAC1_CV
147#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
148#define ATOM_DAC2_PAL ATOM_DAC1_PAL
149
150#define ATOM_PM_ON 0
151#define ATOM_PM_STANDBY 1
152#define ATOM_PM_SUSPEND 2
153#define ATOM_PM_OFF 3
154
155// For ATOM_LVDS_INFO_V12
156// Bit0:{=0:single, =1:dual},
157// Bit1 {=0:666RGB, =1:888RGB},
158// Bit2:3:{Grey level}
159// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
160#define ATOM_PANEL_MISC_DUAL 0x00000001
161#define ATOM_PANEL_MISC_888RGB 0x00000002
162#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
163#define ATOM_PANEL_MISC_FPDI 0x00000010
164#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
165#define ATOM_PANEL_MISC_SPATIAL 0x00000020
166#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
167#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
168
169#define MEMTYPE_DDR1 "DDR1"
170#define MEMTYPE_DDR2 "DDR2"
171#define MEMTYPE_DDR3 "DDR3"
172#define MEMTYPE_DDR4 "DDR4"
173
174#define ASIC_BUS_TYPE_PCI "PCI"
175#define ASIC_BUS_TYPE_AGP "AGP"
176#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
177
178//Maximum size of that FireGL flag string
179#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
180#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
181
182#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
183#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
184
185#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
186#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
187
188#define HW_ASSISTED_I2C_STATUS_FAILURE 2
189#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
190
191#pragma pack(1) // BIOS data must use byte aligment
192
193// Define offset to location of ROM header.
194#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
195#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
196
197#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
198#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0!
199#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
200#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
201
202/****************************************************************************/
203// Common header for all tables (Data table, Command table).
204// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
205// And the pointer actually points to this header.
206/****************************************************************************/
207
208typedef struct _ATOM_COMMON_TABLE_HEADER
209{
210 USHORT usStructureSize;
211 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
212 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware
213 //Image can't be updated, while Driver needs to carry the new table!
214}ATOM_COMMON_TABLE_HEADER;
215
216/****************************************************************************/
217// Structure stores the ROM header.
218/****************************************************************************/
219typedef struct _ATOM_ROM_HEADER
220{
221 ATOM_COMMON_TABLE_HEADER sHeader;
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
223 //atombios should init it as "ATOM", don't change the position
224 USHORT usBiosRuntimeSegmentAddress;
225 USHORT usProtectedModeInfoOffset;
226 USHORT usConfigFilenameOffset;
227 USHORT usCRC_BlockOffset;
228 USHORT usBIOS_BootupMessageOffset;
229 USHORT usInt10Offset;
230 USHORT usPciBusDevInitCode;
231 USHORT usIoBaseAddress;
232 USHORT usSubsystemVendorID;
233 USHORT usSubsystemID;
234 USHORT usPCI_InfoOffset;
235 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
236 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
237 UCHAR ucExtendedFunctionCode;
238 UCHAR ucReserved;
239}ATOM_ROM_HEADER;
240
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400241
242typedef struct _ATOM_ROM_HEADER_V2_1
243{
244 ATOM_COMMON_TABLE_HEADER sHeader;
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
246 //atombios should init it as "ATOM", don't change the position
247 USHORT usBiosRuntimeSegmentAddress;
248 USHORT usProtectedModeInfoOffset;
249 USHORT usConfigFilenameOffset;
250 USHORT usCRC_BlockOffset;
251 USHORT usBIOS_BootupMessageOffset;
252 USHORT usInt10Offset;
253 USHORT usPciBusDevInitCode;
254 USHORT usIoBaseAddress;
255 USHORT usSubsystemVendorID;
256 USHORT usSubsystemID;
257 USHORT usPCI_InfoOffset;
258 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
259 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
260 UCHAR ucExtendedFunctionCode;
261 UCHAR ucReserved;
262 ULONG ulPSPDirTableOffset;
263}ATOM_ROM_HEADER_V2_1;
264
265
Alex Deuchera02860aa2015-04-20 16:44:53 -0400266//==============================Command Table Portion====================================
267
268
269/****************************************************************************/
270// Structures used in Command.mtb
271/****************************************************************************/
272typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
273 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
274 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
275 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
276 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
277 USHORT DIGxEncoderControl; //Only used by Bios
278 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
279 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
280 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
281 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
282 USHORT GPIOPinControl; //Atomic Table, only used by Bios
283 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
284 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
285 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
286 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
287 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
288 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
289 USHORT MemoryPLLInit; //Atomic Table, used only by Bios
290 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
291 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
292 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
293 USHORT SetUniphyInstance; //Atomic Table, only used by Bios
294 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
295 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
296 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
297 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
298 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
299 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
300 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
301 USHORT GetConditionalGoldenSetting; //Only used by Bios
302 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1
303 USHORT PatchMCSetting; //only used by BIOS
304 USHORT MC_SEQ_Control; //only used by BIOS
305 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
306 USHORT EnableScaler; //Atomic Table, used only by Bios
307 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
308 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
309 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
310 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
311 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
312 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
313 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400314 USHORT GetSMUClockInfo; //Atomic Table, used only by Bios
Alex Deuchera02860aa2015-04-20 16:44:53 -0400315 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
316 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
317 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
318 USHORT LUT_AutoFill; //Atomic Table, only used by Bios
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400319 USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK
Alex Deuchera02860aa2015-04-20 16:44:53 -0400320 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
321 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
322 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
323 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
324 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
325 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
326 USHORT MemoryCleanUp; //Atomic Table, only used by Bios
327 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
328 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
329 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
330 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
331 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
332 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
333 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400334 USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
Alex Deuchera02860aa2015-04-20 16:44:53 -0400335 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
336 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
337 USHORT MemoryTraining; //Atomic Table, used only by Bios
338 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
339 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
340 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
341 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
342 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1
343 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
344 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
345 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
346 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
347 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
348 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
349 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
350 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
351 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
352 USHORT DPEncoderService; //Function Table,only used by Bios
353 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
354}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
355
356// For backward compatible
357#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
358#define DPTranslatorControl DIG2EncoderControl
359#define UNIPHYTransmitterControl DIG1TransmitterControl
360#define LVTMATransmitterControl DIG2TransmitterControl
361#define SetCRTC_DPM_State GetConditionalGoldenSetting
362#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance
363#define HPDInterruptService ReadHWAssistedI2CStatus
364#define EnableVGA_Access GetSCLKOverMCLKRatio
365#define EnableYUV GetDispObjectInfo
366#define DynamicClockGating EnableDispPowerGating
367#define SetupHWAssistedI2CStatus ComputeMemoryClockParam
368#define DAC2OutputControl ReadEfuseValue
369
370#define TMDSAEncoderControl PatchMCSetting
371#define LVDSEncoderControl MC_SEQ_Control
372#define LCD1OutputControl HW_Misc_Operation
373#define TV1OutputControl Gfx_Harvesting
374#define TVEncoderControl SMC_Init
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400375#define EnableHW_IconCursor SetDCEClock
376#define SetCRTC_Replication GetSMUClockInfo
377
378#define MemoryRefreshConversion Gfx_Init
Alex Deuchera02860aa2015-04-20 16:44:53 -0400379
380typedef struct _ATOM_MASTER_COMMAND_TABLE
381{
382 ATOM_COMMON_TABLE_HEADER sHeader;
383 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
384}ATOM_MASTER_COMMAND_TABLE;
385
386/****************************************************************************/
387// Structures used in every command table
388/****************************************************************************/
389typedef struct _ATOM_TABLE_ATTRIBUTE
390{
391#if ATOM_BIG_ENDIAN
392 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
393 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
394 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
395#else
396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
397 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
398 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
399#endif
400}ATOM_TABLE_ATTRIBUTE;
401
402/****************************************************************************/
403// Common header for all command tables.
404// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
405// And the pointer actually points to this header.
406/****************************************************************************/
407typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
408{
409 ATOM_COMMON_TABLE_HEADER CommonHeader;
410 ATOM_TABLE_ATTRIBUTE TableAttribute;
411}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
412
413/****************************************************************************/
414// Structures used by ComputeMemoryEnginePLLTable
415/****************************************************************************/
416
417#define COMPUTE_MEMORY_PLL_PARAM 1
418#define COMPUTE_ENGINE_PLL_PARAM 2
419#define ADJUST_MC_SETTING_PARAM 3
420
421/****************************************************************************/
422// Structures used by AdjustMemoryControllerTable
423/****************************************************************************/
424typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
425{
426#if ATOM_BIG_ENDIAN
427 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
428 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
429 ULONG ulClockFreq:24;
430#else
431 ULONG ulClockFreq:24;
432 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
433 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
434#endif
435}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
436#define POINTER_RETURN_FLAG 0x80
437
438typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
439{
440 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
441 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
442 UCHAR ucReserved; //may expand to return larger Fbdiv later
443 UCHAR ucFbDiv; //return value
444 UCHAR ucPostDiv; //return value
445}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
446
447typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
448{
449 ULONG ulClock; //When return, [23:0] return real clock
450 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
451 USHORT usFbDiv; //return Feedback value to be written to register
452 UCHAR ucPostDiv; //return post div to be written to register
453}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
454
455#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
456
457#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
458#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
459#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
460#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
461#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
462#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
463#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
464
465#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
466#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
467#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
468#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
469#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
470#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400471#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
472#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
473#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only
Alex Deuchera02860aa2015-04-20 16:44:53 -0400474
475typedef struct _ATOM_COMPUTE_CLOCK_FREQ
476{
477#if ATOM_BIG_ENDIAN
478 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
479 ULONG ulClockFreq:24; // in unit of 10kHz
480#else
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
483#endif
484}ATOM_COMPUTE_CLOCK_FREQ;
485
486typedef struct _ATOM_S_MPLL_FB_DIVIDER
487{
488 USHORT usFbDivFrac;
489 USHORT usFbDiv;
490}ATOM_S_MPLL_FB_DIVIDER;
491
492typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
493{
494 union
495 {
496 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
497 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
498 };
499 UCHAR ucRefDiv; //Output Parameter
500 UCHAR ucPostDiv; //Output Parameter
501 UCHAR ucCntlFlag; //Output Parameter
502 UCHAR ucReserved;
503}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
504
505// ucCntlFlag
506#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
507#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
508#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
509#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
510
511
512// V4 are only used for APU which PLL outside GPU
513typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
514{
515#if ATOM_BIG_ENDIAN
516 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
517 ULONG ulClock:24; //Input= target clock, output = actual clock
518#else
519 ULONG ulClock:24; //Input= target clock, output = actual clock
520 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
521#endif
522}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
523
524typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
525{
526 union
527 {
528 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
529 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
530 };
531 UCHAR ucRefDiv; //Output Parameter
532 UCHAR ucPostDiv; //Output Parameter
533 union
534 {
535 UCHAR ucCntlFlag; //Output Flags
536 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
537 };
538 UCHAR ucReserved;
539}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
540
541
542typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
543{
544 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
545 ULONG ulReserved[2];
546}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
547
548//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
549#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
550#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
551#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
552
553
554typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
555{
556 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
557 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider
558 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
559 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
560 UCHAR ucPllCntlFlag; //Output Flags: control flag
561 UCHAR ucReserved;
562}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
563
564//ucPllCntlFlag
565#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
566
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400567typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7
568{
569 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
570 ULONG ulReserved[5];
571}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7;
572
573//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
574#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
575#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
576#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
577
578typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7
579{
580 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
581 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
582 USHORT usSclk_fcw_int; //integer divider of fcwc
583 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
584 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
585 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )
586 UCHAR ucSscEnable;
587 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable
588 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable
589 USHORT usReserved;
590 USHORT usPcc_fcw_int;
591 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable
592 USHORT usPcc_fcw_slew_frac;
593}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7;
Alex Deuchera02860aa2015-04-20 16:44:53 -0400594
595// ucInputFlag
596#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
597
598// use for ComputeMemoryClockParamTable
599typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
600{
601 union
602 {
603 ULONG ulClock;
604 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
605 };
606 UCHAR ucDllSpeed; //Output
607 UCHAR ucPostDiv; //Output
608 union{
609 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
610 UCHAR ucPllCntlFlag; //Output:
611 };
612 UCHAR ucBWCntl;
613}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
614
615// definition of ucInputFlag
616#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
617// definition of ucPllCntlFlag
618#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
619#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
620#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
621#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
622
623//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
624#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
625
Eric Huang770911a2015-11-09 17:34:31 -0500626// use for ComputeMemoryClockParamTable
627typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2
628{
629 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;
630 ULONG ulReserved;
631}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
632
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400633//Input parameter of DynamicMemorySettingsTable
634//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM
Alex Deuchera02860aa2015-04-20 16:44:53 -0400635typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
636{
637 ATOM_COMPUTE_CLOCK_FREQ ulClock;
638 ULONG ulReserved[2];
639}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
640
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400641//Input parameter of DynamicMemorySettingsTable
642//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM
Alex Deuchera02860aa2015-04-20 16:44:53 -0400643typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
644{
645 ATOM_COMPUTE_CLOCK_FREQ ulClock;
646 ULONG ulMemoryClock;
647 ULONG ulReserved;
648}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
649
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400650//Input parameter of DynamicMemorySettingsTable ver2.1 and above
651//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM
652typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER
653{
654 ATOM_COMPUTE_CLOCK_FREQ ulClock;
655 UCHAR ucMclkDPMState;
656 UCHAR ucReserved[3];
657 ULONG ulReserved;
658}DYNAMICE_MC_DPM_SETTINGS_PARAMETER;
659
660//ucMclkDPMState
661#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0
662#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1
663#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2
664
665typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1
666{
667 DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg;
668 DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg;
669 DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg;
670}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1;
671
672
Alex Deuchera02860aa2015-04-20 16:44:53 -0400673/****************************************************************************/
674// Structures used by SetEngineClockTable
675/****************************************************************************/
676typedef struct _SET_ENGINE_CLOCK_PARAMETERS
677{
678 ULONG ulTargetEngineClock; //In 10Khz unit
679}SET_ENGINE_CLOCK_PARAMETERS;
680
681typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
682{
683 ULONG ulTargetEngineClock; //In 10Khz unit
684 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
685}SET_ENGINE_CLOCK_PS_ALLOCATION;
686
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400687typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2
688{
689 ULONG ulTargetEngineClock; //In 10Khz unit
690 COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved;
691}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2;
692
693
Alex Deuchera02860aa2015-04-20 16:44:53 -0400694/****************************************************************************/
695// Structures used by SetMemoryClockTable
696/****************************************************************************/
697typedef struct _SET_MEMORY_CLOCK_PARAMETERS
698{
699 ULONG ulTargetMemoryClock; //In 10Khz unit
700}SET_MEMORY_CLOCK_PARAMETERS;
701
702typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
703{
704 ULONG ulTargetMemoryClock; //In 10Khz unit
705 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
706}SET_MEMORY_CLOCK_PS_ALLOCATION;
707
708/****************************************************************************/
709// Structures used by ASIC_Init.ctb
710/****************************************************************************/
711typedef struct _ASIC_INIT_PARAMETERS
712{
713 ULONG ulDefaultEngineClock; //In 10Khz unit
714 ULONG ulDefaultMemoryClock; //In 10Khz unit
715}ASIC_INIT_PARAMETERS;
716
717typedef struct _ASIC_INIT_PS_ALLOCATION
718{
719 ASIC_INIT_PARAMETERS sASICInitClocks;
720 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
721}ASIC_INIT_PS_ALLOCATION;
722
723typedef struct _ASIC_INIT_CLOCK_PARAMETERS
724{
725 ULONG ulClkFreqIn10Khz:24;
726 ULONG ucClkFlag:8;
727}ASIC_INIT_CLOCK_PARAMETERS;
728
729typedef struct _ASIC_INIT_PARAMETERS_V1_2
730{
731 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
732 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit
733}ASIC_INIT_PARAMETERS_V1_2;
734
735typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2
736{
737 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks;
738 ULONG ulReserved[8];
739}ASIC_INIT_PS_ALLOCATION_V1_2;
740
741/****************************************************************************/
742// Structure used by DynamicClockGatingTable.ctb
743/****************************************************************************/
744typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
745{
746 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
747 UCHAR ucPadding[3];
748}DYNAMIC_CLOCK_GATING_PARAMETERS;
749#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
750
751/****************************************************************************/
752// Structure used by EnableDispPowerGatingTable.ctb
753/****************************************************************************/
754typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
755{
756 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
757 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
758 UCHAR ucPadding[2];
759}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
760
761typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION
762{
763 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
764 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
765 UCHAR ucPadding[2];
766 ULONG ulReserved[4];
767}ENABLE_DISP_POWER_GATING_PS_ALLOCATION;
768
769/****************************************************************************/
770// Structure used by EnableASIC_StaticPwrMgtTable.ctb
771/****************************************************************************/
772typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
773{
774 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
775 UCHAR ucPadding[3];
776}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
777#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
778
779/****************************************************************************/
780// Structures used by DAC_LoadDetectionTable.ctb
781/****************************************************************************/
782typedef struct _DAC_LOAD_DETECTION_PARAMETERS
783{
784 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
785 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
786 UCHAR ucMisc; //Valid only when table revision =1.3 and above
787}DAC_LOAD_DETECTION_PARAMETERS;
788
789// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
790#define DAC_LOAD_MISC_YPrPb 0x01
791
792typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
793{
794 DAC_LOAD_DETECTION_PARAMETERS sDacload;
795 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
796}DAC_LOAD_DETECTION_PS_ALLOCATION;
797
798/****************************************************************************/
799// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
800/****************************************************************************/
801typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
802{
803 USHORT usPixelClock; // in 10KHz; for bios convenient
804 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
805 UCHAR ucAction; // 0: turn off encoder
806 // 1: setup and turn on encoder
807 // 7: ATOM_ENCODER_INIT Initialize DAC
808}DAC_ENCODER_CONTROL_PARAMETERS;
809
810#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
811
812/****************************************************************************/
813// Structures used by DIG1EncoderControlTable
814// DIG2EncoderControlTable
815// ExternalEncoderControlTable
816/****************************************************************************/
817typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
818{
819 USHORT usPixelClock; // in 10KHz; for bios convenient
820 UCHAR ucConfig;
821 // [2] Link Select:
822 // =0: PHY linkA if bfLane<3
823 // =1: PHY linkB if bfLanes<3
824 // =0: PHY linkA+B if bfLanes=3
825 // [3] Transmitter Sel
826 // =0: UNIPHY or PCIEPHY
827 // =1: LVTMA
828 UCHAR ucAction; // =0: turn off encoder
829 // =1: turn on encoder
830 UCHAR ucEncoderMode;
831 // =0: DP encoder
832 // =1: LVDS encoder
833 // =2: DVI encoder
834 // =3: HDMI encoder
835 // =4: SDVO encoder
836 UCHAR ucLaneNum; // how many lanes to enable
837 UCHAR ucReserved[2];
838}DIG_ENCODER_CONTROL_PARAMETERS;
839#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
840#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
841
842//ucConfig
843#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
844#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
845#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
846#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
847#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
848#define ATOM_ENCODER_CONFIG_LINKA 0x00
849#define ATOM_ENCODER_CONFIG_LINKB 0x04
850#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
851#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
852#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
853#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
854#define ATOM_ENCODER_CONFIG_LVTMA 0x08
855#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
856#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
857#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
858// ucAction
859// ATOM_ENABLE: Enable Encoder
860// ATOM_DISABLE: Disable Encoder
861
862//ucEncoderMode
863#define ATOM_ENCODER_MODE_DP 0
864#define ATOM_ENCODER_MODE_LVDS 1
865#define ATOM_ENCODER_MODE_DVI 2
866#define ATOM_ENCODER_MODE_HDMI 3
867#define ATOM_ENCODER_MODE_SDVO 4
868#define ATOM_ENCODER_MODE_DP_AUDIO 5
869#define ATOM_ENCODER_MODE_TV 13
870#define ATOM_ENCODER_MODE_CV 14
871#define ATOM_ENCODER_MODE_CRT 15
872#define ATOM_ENCODER_MODE_DVO 16
873#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
874#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
875
876
877typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
878{
879#if ATOM_BIG_ENDIAN
880 UCHAR ucReserved1:2;
881 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
882 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
883 UCHAR ucReserved:1;
884 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
885#else
886 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
887 UCHAR ucReserved:1;
888 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
889 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
890 UCHAR ucReserved1:2;
891#endif
892}ATOM_DIG_ENCODER_CONFIG_V2;
893
894
895typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
896{
897 USHORT usPixelClock; // in 10KHz; for bios convenient
898 ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
899 UCHAR ucAction;
900 UCHAR ucEncoderMode;
901 // =0: DP encoder
902 // =1: LVDS encoder
903 // =2: DVI encoder
904 // =3: HDMI encoder
905 // =4: SDVO encoder
906 UCHAR ucLaneNum; // how many lanes to enable
907 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
908 UCHAR ucReserved;
909}DIG_ENCODER_CONTROL_PARAMETERS_V2;
910
911//ucConfig
912#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
913#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
914#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
915#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
916#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
917#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
918#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
919#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
920#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
921#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
922
923// ucAction:
924// ATOM_DISABLE
925// ATOM_ENABLE
926#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
927#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
928#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
929#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
930#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
931#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
932#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
933#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
934#define ATOM_ENCODER_CMD_SETUP 0x0f
935#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
936
Alex Deucher6e14e92b2015-10-15 00:43:41 -0400937// New Command for DIGxEncoderControlTable v1.5
938#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14
939#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP
940#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table
941#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table
942
Alex Deuchera02860aa2015-04-20 16:44:53 -0400943// ucStatus
944#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
945#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
946
947//ucTableFormatRevision=1
948//ucTableContentRevision=3
949// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
950typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
951{
952#if ATOM_BIG_ENDIAN
953 UCHAR ucReserved1:1;
954 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
955 UCHAR ucReserved:3;
956 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
957#else
958 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
959 UCHAR ucReserved:3;
960 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
961 UCHAR ucReserved1:1;
962#endif
963}ATOM_DIG_ENCODER_CONFIG_V3;
964
965#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
966#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
967#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
968#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
969#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
970#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
971#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
972#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
973#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
974#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
975
976typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
977{
978 USHORT usPixelClock; // in 10KHz; for bios convenient
979 ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
980 UCHAR ucAction;
981 union{
982 UCHAR ucEncoderMode;
983 // =0: DP encoder
984 // =1: LVDS encoder
985 // =2: DVI encoder
986 // =3: HDMI encoder
987 // =4: SDVO encoder
988 // =5: DP audio
989 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
990 // =0: external DP
991 // =0x1: internal DP2
992 // =0x11: internal DP1 for NutMeg/Travis DP translator
993 };
994 UCHAR ucLaneNum; // how many lanes to enable
995 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
996 UCHAR ucReserved;
997}DIG_ENCODER_CONTROL_PARAMETERS_V3;
998
999//ucTableFormatRevision=1
1000//ucTableContentRevision=4
1001// start from NI
1002// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
1003typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
1004{
1005#if ATOM_BIG_ENDIAN
1006 UCHAR ucReserved1:1;
1007 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1008 UCHAR ucReserved:2;
1009 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1010#else
1011 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1012 UCHAR ucReserved:2;
1013 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1014 UCHAR ucReserved1:1;
1015#endif
1016}ATOM_DIG_ENCODER_CONFIG_V4;
1017
1018#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
1019#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
1020#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
1021#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
1022#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
1023#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
1024#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
1025#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
1026#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
1027#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
1028#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
1029#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
1030#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
1031
1032typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
1033{
1034 USHORT usPixelClock; // in 10KHz; for bios convenient
1035 union{
1036 ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
1037 UCHAR ucConfig;
1038 };
1039 UCHAR ucAction;
1040 union{
1041 UCHAR ucEncoderMode;
1042 // =0: DP encoder
1043 // =1: LVDS encoder
1044 // =2: DVI encoder
1045 // =3: HDMI encoder
1046 // =4: SDVO encoder
1047 // =5: DP audio
1048 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
1049 // =0: external DP
1050 // =0x1: internal DP2
1051 // =0x11: internal DP1 for NutMeg/Travis DP translator
1052 };
1053 UCHAR ucLaneNum; // how many lanes to enable
1054 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1055 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
1056}DIG_ENCODER_CONTROL_PARAMETERS_V4;
1057
1058// define ucBitPerColor:
1059#define PANEL_BPC_UNDEFINE 0x00
1060#define PANEL_6BIT_PER_COLOR 0x01
1061#define PANEL_8BIT_PER_COLOR 0x02
1062#define PANEL_10BIT_PER_COLOR 0x03
1063#define PANEL_12BIT_PER_COLOR 0x04
1064#define PANEL_16BIT_PER_COLOR 0x05
1065
1066//define ucPanelMode
1067#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
1068#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
1069#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
1070
Alex Deucher6e14e92b2015-10-15 00:43:41 -04001071
1072typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5
1073{
1074 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1075 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP
1076 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1077 UCHAR ucLaneNum; // Lane number
1078 ULONG ulPixelClock; // Pixel Clock in 10Khz
1079 UCHAR ucBitPerColor;
1080 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
1081 UCHAR ucReserved[2];
1082}ENCODER_STREAM_SETUP_PARAMETERS_V5;
1083
1084typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5
1085{
1086 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1087 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP
1088 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1089 UCHAR ucLaneNum; // Lane number
1090 ULONG ulSymClock; // Symbol Clock in 10Khz
1091 UCHAR ucHPDSel;
1092 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1093 UCHAR ucReserved[2];
1094}ENCODER_LINK_SETUP_PARAMETERS_V5;
1095
1096typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5
1097{
1098 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1099 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP
1100 UCHAR ucPanelMode; // =0: external DP
1101 // =0x1: internal DP2
1102 // =0x11: internal DP1 NutMeg/Travis DP Translator
1103 UCHAR ucReserved;
1104 ULONG ulReserved[2];
1105}DP_PANEL_MODE_SETUP_PARAMETERS_V5;
1106
1107typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5
1108{
1109 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1110 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters
1111 UCHAR ucReserved[2];
1112 ULONG ulReserved[2];
1113}ENCODER_GENERIC_CMD_PARAMETERS_V5;
1114
1115//ucDigId
1116#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00
1117#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01
1118#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02
1119#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03
1120#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04
1121#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05
1122#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06
1123
1124
1125typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5
1126{
1127 ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam;
1128 ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam;
1129 ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam;
1130 DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam;
1131}DIG_ENCODER_CONTROL_PARAMETERS_V5;
1132
1133
Alex Deuchera02860aa2015-04-20 16:44:53 -04001134/****************************************************************************/
1135// Structures used by UNIPHYTransmitterControlTable
1136// LVTMATransmitterControlTable
1137// DVOOutputControlTable
1138/****************************************************************************/
1139typedef struct _ATOM_DP_VS_MODE
1140{
1141 UCHAR ucLaneSel;
1142 UCHAR ucLaneSet;
1143}ATOM_DP_VS_MODE;
1144
1145typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
1146{
1147 union
1148 {
1149 USHORT usPixelClock; // in 10KHz; for bios convenient
1150 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1151 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1152 };
1153 UCHAR ucConfig;
1154 // [0]=0: 4 lane Link,
1155 // =1: 8 lane Link ( Dual Links TMDS )
1156 // [1]=0: InCoherent mode
1157 // =1: Coherent Mode
1158 // [2] Link Select:
1159 // =0: PHY linkA if bfLane<3
1160 // =1: PHY linkB if bfLanes<3
1161 // =0: PHY linkA+B if bfLanes=3
1162 // [5:4]PCIE lane Sel
1163 // =0: lane 0~3 or 0~7
1164 // =1: lane 4~7
1165 // =2: lane 8~11 or 8~15
1166 // =3: lane 12~15
1167 UCHAR ucAction; // =0: turn off encoder
1168 // =1: turn on encoder
1169 UCHAR ucReserved[4];
1170}DIG_TRANSMITTER_CONTROL_PARAMETERS;
1171
1172#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
1173
1174//ucInitInfo
1175#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
1176
1177//ucConfig
1178#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
1179#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
1180#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
1181#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
1182#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
1183#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
1184#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
1185
1186#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1187#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1188#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1189
1190#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
1191#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
1192#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
1193#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
1194#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
1195#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
1196#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
1197#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
1198#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
1199#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
1200#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
1201
1202//ucAction
1203#define ATOM_TRANSMITTER_ACTION_DISABLE 0
1204#define ATOM_TRANSMITTER_ACTION_ENABLE 1
1205#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
1206#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
1207#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
1208#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
1209#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
1210#define ATOM_TRANSMITTER_ACTION_INIT 7
1211#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
1212#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
1213#define ATOM_TRANSMITTER_ACTION_SETUP 10
1214#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
1215#define ATOM_TRANSMITTER_ACTION_POWER_ON 12
1216#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
1217
1218// Following are used for DigTransmitterControlTable ver1.2
1219typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
1220{
1221#if ATOM_BIG_ENDIAN
1222 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1223 // =1 Dig Transmitter 2 ( Uniphy CD )
1224 // =2 Dig Transmitter 3 ( Uniphy EF )
1225 UCHAR ucReserved:1;
1226 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1227 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1228 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1229 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1230
1231 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1232 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1233#else
1234 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1235 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1236 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1237 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1238 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1239 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1240 UCHAR ucReserved:1;
1241 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1242 // =1 Dig Transmitter 2 ( Uniphy CD )
1243 // =2 Dig Transmitter 3 ( Uniphy EF )
1244#endif
1245}ATOM_DIG_TRANSMITTER_CONFIG_V2;
1246
1247//ucConfig
1248//Bit0
1249#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
1250
1251//Bit1
1252#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
1253
1254//Bit2
1255#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
1256#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
1257#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
1258
1259// Bit3
1260#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1261#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1262#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1263
1264// Bit4
1265#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
1266
1267// Bit7:6
1268#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1269#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
1270#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
1271#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1272
1273typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1274{
1275 union
1276 {
1277 USHORT usPixelClock; // in 10KHz; for bios convenient
1278 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1279 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1280 };
1281 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1282 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1283 UCHAR ucReserved[4];
1284}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1285
1286typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1287{
1288#if ATOM_BIG_ENDIAN
1289 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1290 // =1 Dig Transmitter 2 ( Uniphy CD )
1291 // =2 Dig Transmitter 3 ( Uniphy EF )
1292 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1293 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1294 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1295 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1296 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1297 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1298#else
1299 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1300 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1301 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1302 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1303 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1304 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1305 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1306 // =1 Dig Transmitter 2 ( Uniphy CD )
1307 // =2 Dig Transmitter 3 ( Uniphy EF )
1308#endif
1309}ATOM_DIG_TRANSMITTER_CONFIG_V3;
1310
1311
1312typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1313{
1314 union
1315 {
1316 USHORT usPixelClock; // in 10KHz; for bios convenient
1317 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1318 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1319 };
1320 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1321 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1322 UCHAR ucLaneNum;
1323 UCHAR ucReserved[3];
1324}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1325
1326//ucConfig
1327//Bit0
1328#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
1329
1330//Bit1
1331#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
1332
1333//Bit2
1334#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
1335#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
1336#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
1337
1338// Bit3
1339#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
1340#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
1341#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
1342
1343// Bit5:4
1344#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
1345#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
1346#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
1347#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
1348
1349// Bit7:6
1350#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
1351#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
1352#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
1353#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
1354
1355
1356/****************************************************************************/
1357// Structures used by UNIPHYTransmitterControlTable V1.4
1358// ASIC Families: NI
1359// ucTableFormatRevision=1
1360// ucTableContentRevision=4
1361/****************************************************************************/
1362typedef struct _ATOM_DP_VS_MODE_V4
1363{
1364 UCHAR ucLaneSel;
1365 union
1366 {
1367 UCHAR ucLaneSet;
1368 struct {
1369#if ATOM_BIG_ENDIAN
1370 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1371 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1372 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1373#else
1374 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1375 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1376 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1377#endif
1378 };
1379 };
1380}ATOM_DP_VS_MODE_V4;
1381
1382typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1383{
1384#if ATOM_BIG_ENDIAN
1385 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1386 // =1 Dig Transmitter 2 ( Uniphy CD )
1387 // =2 Dig Transmitter 3 ( Uniphy EF )
1388 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1389 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1390 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1391 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1392 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1393 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1394#else
1395 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1396 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1397 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1398 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1399 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1400 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1401 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1402 // =1 Dig Transmitter 2 ( Uniphy CD )
1403 // =2 Dig Transmitter 3 ( Uniphy EF )
1404#endif
1405}ATOM_DIG_TRANSMITTER_CONFIG_V4;
1406
1407typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1408{
1409 union
1410 {
1411 USHORT usPixelClock; // in 10KHz; for bios convenient
1412 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1413 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1414 };
1415 union
1416 {
1417 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1418 UCHAR ucConfig;
1419 };
1420 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1421 UCHAR ucLaneNum;
1422 UCHAR ucReserved[3];
1423}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1424
1425//ucConfig
1426//Bit0
1427#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1428//Bit1
1429#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1430//Bit2
1431#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1432#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1433#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1434// Bit3
1435#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1436#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1437#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1438// Bit5:4
1439#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1440#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1441#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1442#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1443#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1444// Bit7:6
1445#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1446#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1447#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1448#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1449
1450
1451typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1452{
1453#if ATOM_BIG_ENDIAN
1454 UCHAR ucReservd1:1;
1455 UCHAR ucHPDSel:3;
1456 UCHAR ucPhyClkSrcId:2;
1457 UCHAR ucCoherentMode:1;
1458 UCHAR ucReserved:1;
1459#else
1460 UCHAR ucReserved:1;
1461 UCHAR ucCoherentMode:1;
1462 UCHAR ucPhyClkSrcId:2;
1463 UCHAR ucHPDSel:3;
1464 UCHAR ucReservd1:1;
1465#endif
1466}ATOM_DIG_TRANSMITTER_CONFIG_V5;
1467
1468typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1469{
1470 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1471 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1472 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1473 UCHAR ucLaneNum; // indicate lane number 1-8
1474 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1475 UCHAR ucDigMode; // indicate DIG mode
1476 union{
1477 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1478 UCHAR ucConfig;
1479 };
1480 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1481 UCHAR ucDPLaneSet;
1482 UCHAR ucReserved;
1483 UCHAR ucReserved1;
1484}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1485
1486//ucPhyId
1487#define ATOM_PHY_ID_UNIPHYA 0
1488#define ATOM_PHY_ID_UNIPHYB 1
1489#define ATOM_PHY_ID_UNIPHYC 2
1490#define ATOM_PHY_ID_UNIPHYD 3
1491#define ATOM_PHY_ID_UNIPHYE 4
1492#define ATOM_PHY_ID_UNIPHYF 5
1493#define ATOM_PHY_ID_UNIPHYG 6
1494
1495// ucDigEncoderSel
1496#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
1497#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
1498#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
1499#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
1500#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
1501#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
1502#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
1503
1504// ucDigMode
1505#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
1506#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1507#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1508#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
1509#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1510#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
1511
1512// ucDPLaneSet
1513#define DP_LANE_SET__0DB_0_4V 0x00
1514#define DP_LANE_SET__0DB_0_6V 0x01
1515#define DP_LANE_SET__0DB_0_8V 0x02
1516#define DP_LANE_SET__0DB_1_2V 0x03
1517#define DP_LANE_SET__3_5DB_0_4V 0x08
1518#define DP_LANE_SET__3_5DB_0_6V 0x09
1519#define DP_LANE_SET__3_5DB_0_8V 0x0a
1520#define DP_LANE_SET__6DB_0_4V 0x10
1521#define DP_LANE_SET__6DB_0_6V 0x11
1522#define DP_LANE_SET__9_5DB_0_4V 0x18
1523
1524// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1525// Bit1
1526#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
1527
1528// Bit3:2
1529#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
1530#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
1531
1532#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
1533#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
1534#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
1535#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
1536// Bit6:4
1537#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
1538#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
1539
1540#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
1541#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
1542#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
1543#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
1544#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
1545#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
1546#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
1547
1548#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1549
Alex Deucher6e14e92b2015-10-15 00:43:41 -04001550typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6
1551{
1552 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1553 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1554 union
1555 {
1556 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1557 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
1558 };
1559 UCHAR ucLaneNum; // Lane number
1560 ULONG ulSymClock; // Symbol Clock in 10Khz
1561 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
1562 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1563 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1564 UCHAR ucReserved;
1565 ULONG ulReserved;
1566}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6;
1567
1568
1569// ucDigEncoderSel
1570#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01
1571#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02
1572#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04
1573#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08
1574#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10
1575#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20
1576#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40
1577
1578// ucDigMode
1579#define ATOM_TRANSMITTER_DIGMODE_V6_DP 0
1580#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2
1581#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3
1582#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5
1583
1584//ucHPDSel
1585#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00
1586#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01
1587#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02
1588#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03
1589#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04
1590#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05
1591#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06
1592
Alex Deuchera02860aa2015-04-20 16:44:53 -04001593
1594/****************************************************************************/
1595// Structures used by ExternalEncoderControlTable V1.3
1596// ASIC Families: Evergreen, Llano, NI
1597// ucTableFormatRevision=1
1598// ucTableContentRevision=3
1599/****************************************************************************/
1600
1601typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1602{
1603 union{
1604 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1605 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1606 };
1607 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1608 UCHAR ucAction; //
1609 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1610 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1611 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1612 UCHAR ucReserved;
1613}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1614
1615// ucAction
1616#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1617#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1618#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1619#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1620#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1621#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1622#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1623#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1624
1625// ucConfig
1626#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1627#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1628#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1629#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1630#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70
1631#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1632#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1633#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1634
1635typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1636{
1637 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1638 ULONG ulReserved[2];
1639}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1640
1641
1642/****************************************************************************/
1643// Structures used by DAC1OuputControlTable
1644// DAC2OuputControlTable
1645// LVTMAOutputControlTable (Before DEC30)
1646// TMDSAOutputControlTable (Before DEC30)
1647/****************************************************************************/
1648typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1649{
1650 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1651 // When the display is LCD, in addition to above:
1652 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1653 // ATOM_LCD_SELFTEST_STOP
1654
1655 UCHAR aucPadding[3]; // padding to DWORD aligned
1656}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1657
1658#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1659
1660
1661#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1662#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1663
1664#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1665#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1666
1667#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1668#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1669
1670#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1671#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1672
1673#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1674#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1675
1676#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1677#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1678
1679#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1680#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1681
1682#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1683#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1684#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
1685
1686
1687typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2
1688{
1689 // Possible value of ucAction
1690 // ATOM_TRANSMITTER_ACTION_LCD_BLON
1691 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF
1692 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
1693 // ATOM_TRANSMITTER_ACTION_POWER_ON
1694 // ATOM_TRANSMITTER_ACTION_POWER_OFF
1695 UCHAR ucAction;
1696 UCHAR ucBriLevel;
1697 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz
1698}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;
1699
1700
1701
1702/****************************************************************************/
1703// Structures used by BlankCRTCTable
1704/****************************************************************************/
1705typedef struct _BLANK_CRTC_PARAMETERS
1706{
1707 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1708 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1709 USHORT usBlackColorRCr;
1710 USHORT usBlackColorGY;
1711 USHORT usBlackColorBCb;
1712}BLANK_CRTC_PARAMETERS;
1713#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
1714
1715/****************************************************************************/
1716// Structures used by EnableCRTCTable
1717// EnableCRTCMemReqTable
1718// UpdateCRTC_DoubleBufferRegistersTable
1719/****************************************************************************/
1720typedef struct _ENABLE_CRTC_PARAMETERS
1721{
1722 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1723 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1724 UCHAR ucPadding[2];
1725}ENABLE_CRTC_PARAMETERS;
1726#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
1727
1728/****************************************************************************/
1729// Structures used by SetCRTC_OverScanTable
1730/****************************************************************************/
1731typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1732{
1733 USHORT usOverscanRight; // right
1734 USHORT usOverscanLeft; // left
1735 USHORT usOverscanBottom; // bottom
1736 USHORT usOverscanTop; // top
1737 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1738 UCHAR ucPadding[3];
1739}SET_CRTC_OVERSCAN_PARAMETERS;
1740#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
1741
1742/****************************************************************************/
1743// Structures used by SetCRTC_ReplicationTable
1744/****************************************************************************/
1745typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1746{
1747 UCHAR ucH_Replication; // horizontal replication
1748 UCHAR ucV_Replication; // vertical replication
1749 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1750 UCHAR ucPadding;
1751}SET_CRTC_REPLICATION_PARAMETERS;
1752#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
1753
1754/****************************************************************************/
1755// Structures used by SelectCRTC_SourceTable
1756/****************************************************************************/
1757typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1758{
1759 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1760 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1761 UCHAR ucPadding[2];
1762}SELECT_CRTC_SOURCE_PARAMETERS;
1763#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
1764
1765typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1766{
1767 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1768 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1769 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1770 UCHAR ucPadding;
1771}SELECT_CRTC_SOURCE_PARAMETERS_V2;
1772
1773//ucEncoderID
1774//#define ASIC_INT_DAC1_ENCODER_ID 0x00
1775//#define ASIC_INT_TV_ENCODER_ID 0x02
1776//#define ASIC_INT_DIG1_ENCODER_ID 0x03
1777//#define ASIC_INT_DAC2_ENCODER_ID 0x04
1778//#define ASIC_EXT_TV_ENCODER_ID 0x06
1779//#define ASIC_INT_DVO_ENCODER_ID 0x07
1780//#define ASIC_INT_DIG2_ENCODER_ID 0x09
1781//#define ASIC_EXT_DIG_ENCODER_ID 0x05
1782
1783//ucEncodeMode
1784//#define ATOM_ENCODER_MODE_DP 0
1785//#define ATOM_ENCODER_MODE_LVDS 1
1786//#define ATOM_ENCODER_MODE_DVI 2
1787//#define ATOM_ENCODER_MODE_HDMI 3
1788//#define ATOM_ENCODER_MODE_SDVO 4
1789//#define ATOM_ENCODER_MODE_TV 13
1790//#define ATOM_ENCODER_MODE_CV 14
1791//#define ATOM_ENCODER_MODE_CRT 15
1792
1793
1794typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3
1795{
1796 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1797 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1798 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1799 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
1800}SELECT_CRTC_SOURCE_PARAMETERS_V3;
1801
1802
1803/****************************************************************************/
1804// Structures used by SetPixelClockTable
1805// GetPixelClockTable
1806/****************************************************************************/
1807//Major revision=1., Minor revision=1
1808typedef struct _PIXEL_CLOCK_PARAMETERS
1809{
1810 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1811 // 0 means disable PPLL
1812 USHORT usRefDiv; // Reference divider
1813 USHORT usFbDiv; // feedback divider
1814 UCHAR ucPostDiv; // post divider
1815 UCHAR ucFracFbDiv; // fractional feedback divider
1816 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1817 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1818 UCHAR ucCRTC; // Which CRTC uses this Ppll
1819 UCHAR ucPadding;
1820}PIXEL_CLOCK_PARAMETERS;
1821
1822//Major revision=1., Minor revision=2, add ucMiscIfno
1823//ucMiscInfo:
1824#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1825#define MISC_DEVICE_INDEX_MASK 0xF0
1826#define MISC_DEVICE_INDEX_SHIFT 4
1827
1828typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1829{
1830 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1831 // 0 means disable PPLL
1832 USHORT usRefDiv; // Reference divider
1833 USHORT usFbDiv; // feedback divider
1834 UCHAR ucPostDiv; // post divider
1835 UCHAR ucFracFbDiv; // fractional feedback divider
1836 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1837 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1838 UCHAR ucCRTC; // Which CRTC uses this Ppll
1839 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1840}PIXEL_CLOCK_PARAMETERS_V2;
1841
1842//Major revision=1., Minor revision=3, structure/definition change
1843//ucEncoderMode:
1844//ATOM_ENCODER_MODE_DP
1845//ATOM_ENOCDER_MODE_LVDS
1846//ATOM_ENOCDER_MODE_DVI
1847//ATOM_ENOCDER_MODE_HDMI
1848//ATOM_ENOCDER_MODE_SDVO
1849//ATOM_ENCODER_MODE_TV 13
1850//ATOM_ENCODER_MODE_CV 14
1851//ATOM_ENCODER_MODE_CRT 15
1852
1853//ucDVOConfig
1854//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
1855//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
1856//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
1857//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
1858//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
1859//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
1860//#define DVO_ENCODER_CONFIG_24BIT 0x08
1861
1862//ucMiscInfo: also changed, see below
1863#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
1864#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
1865#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
1866#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
1867#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
1868#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1869#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
1870// V1.4 for RoadRunner
1871#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1872#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1873
1874
1875typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1876{
1877 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1878 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1879 USHORT usRefDiv; // Reference divider
1880 USHORT usFbDiv; // feedback divider
1881 UCHAR ucPostDiv; // post divider
1882 UCHAR ucFracFbDiv; // fractional feedback divider
1883 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1884 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1885 union
1886 {
1887 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1888 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1889 };
1890 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1891 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1892 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1893}PIXEL_CLOCK_PARAMETERS_V3;
1894
1895#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
1896#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
1897
1898
1899typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1900{
1901 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1902 // drive the pixel clock. not used for DCPLL case.
1903 union{
1904 UCHAR ucReserved;
1905 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1906 };
1907 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1908 // 0 means disable PPLL/DCPLL.
1909 USHORT usFbDiv; // feedback divider integer part.
1910 UCHAR ucPostDiv; // post divider.
1911 UCHAR ucRefDiv; // Reference divider
1912 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1913 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1914 // indicate which graphic encoder will be used.
1915 UCHAR ucEncoderMode; // Encoder mode:
1916 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1917 // bit[1]= when VGA timing is used.
1918 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1919 // bit[4]= RefClock source for PPLL.
1920 // =0: XTLAIN( default mode )
1921 // =1: other external clock source, which is pre-defined
1922 // by VBIOS depend on the feature required.
1923 // bit[7:5]: reserved.
1924 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1925
1926}PIXEL_CLOCK_PARAMETERS_V5;
1927
1928#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
1929#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
1930#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
1931#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
1932#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
1933#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1934#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1935
1936typedef struct _CRTC_PIXEL_CLOCK_FREQ
1937{
1938#if ATOM_BIG_ENDIAN
1939 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1940 // drive the pixel clock. not used for DCPLL case.
1941 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1942 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1943#else
1944 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1945 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1946 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1947 // drive the pixel clock. not used for DCPLL case.
1948#endif
1949}CRTC_PIXEL_CLOCK_FREQ;
1950
1951typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1952{
1953 union{
1954 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1955 ULONG ulDispEngClkFreq; // dispclk frequency
1956 };
1957 USHORT usFbDiv; // feedback divider integer part.
1958 UCHAR ucPostDiv; // post divider.
1959 UCHAR ucRefDiv; // Reference divider
1960 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1961 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1962 // indicate which graphic encoder will be used.
1963 UCHAR ucEncoderMode; // Encoder mode:
1964 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1965 // bit[1]= when VGA timing is used.
1966 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1967 // bit[4]= RefClock source for PPLL.
1968 // =0: XTLAIN( default mode )
1969 // =1: other external clock source, which is pre-defined
1970 // by VBIOS depend on the feature required.
1971 // bit[7:5]: reserved.
1972 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1973
1974}PIXEL_CLOCK_PARAMETERS_V6;
1975
1976#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1977#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1978#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1979#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1980#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1981#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1982#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1983#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1984#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1985#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1986#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
1987#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40
1988
1989typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1990{
1991 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1992}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1993
1994typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1995{
1996 UCHAR ucStatus;
1997 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1998 UCHAR ucReserved[2];
1999}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
2000
2001typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
2002{
2003 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
2004}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
2005
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002006typedef struct _PIXEL_CLOCK_PARAMETERS_V7
2007{
2008 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2009
2010 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2011 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
2012 // indicate which graphic encoder will be used.
2013 UCHAR ucEncoderMode; // Encoder mode:
2014 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk
2015 // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk )
2016 // bit[5:4]= RefClock source for PPLL.
2017 // =0: XTLAIN( default mode )
2018 // =1: pcie
2019 // =2: GENLK
2020 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
2021 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2022 UCHAR ucReserved[2];
2023 ULONG ulReserved;
2024}PIXEL_CLOCK_PARAMETERS_V7;
2025
2026//ucMiscInfo
2027#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01
2028#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02
2029#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04
2030#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08
2031#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30
2032#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00
2033#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10
2034#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20
2035
2036//ucDeepColorRatio
2037#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2038#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2039#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2040#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2041
2042// SetDCEClockTable input parameter for DCE11.1
2043typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1
2044{
2045 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
2046 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2047 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2048 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2049 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2050}SET_DCE_CLOCK_PARAMETERS_V1_1;
2051
2052
2053typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1
2054{
2055 SET_DCE_CLOCK_PARAMETERS_V1_1 asParam;
2056 ULONG ulReserved[2];
2057}SET_DCE_CLOCK_PS_ALLOCATION_V1_1;
2058
2059//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag
2060#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01
2061#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01
2062#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02
2063
Flora Cui2cc0c0b2016-03-14 18:33:29 -04002064// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002065typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1
2066{
2067 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2068 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2069 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2070 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2071 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2072}SET_DCE_CLOCK_PARAMETERS_V2_1;
2073
2074//ucDCEClkType
2075#define DCE_CLOCK_TYPE_DISPCLK 0
2076#define DCE_CLOCK_TYPE_DPREFCLK 1
2077#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable
2078
2079//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2080#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03
2081#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00
2082#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01
2083#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02
2084#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03
2085
2086//ucDCEClkFlag when ucDCEClkType == PIXCLK
2087#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03
2088#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2089#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2090#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2091#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2092#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04
2093
2094typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1
2095{
2096 SET_DCE_CLOCK_PARAMETERS_V2_1 asParam;
2097 ULONG ulReserved[2];
2098}SET_DCE_CLOCK_PS_ALLOCATION_V2_1;
2099
2100
Alex Deuchera02860aa2015-04-20 16:44:53 -04002101
2102/****************************************************************************/
2103// Structures used by AdjustDisplayPllTable
2104/****************************************************************************/
2105typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
2106{
2107 USHORT usPixelClock;
2108 UCHAR ucTransmitterID;
2109 UCHAR ucEncodeMode;
2110 union
2111 {
2112 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
2113 UCHAR ucConfig; //if none DVO, not defined yet
2114 };
2115 UCHAR ucReserved[3];
2116}ADJUST_DISPLAY_PLL_PARAMETERS;
2117
2118#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
2119#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
2120
2121typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
2122{
2123 USHORT usPixelClock; // target pixel clock
2124 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
2125 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
2126 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
2127 UCHAR ucExtTransmitterID; // external encoder id.
2128 UCHAR ucReserved[2];
2129}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
2130
2131// usDispPllConfig v1.2 for RoadRunner
2132#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
2133#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
2134#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
2135#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
2136#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
2137#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
2138#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
2139#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
2140#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
2141#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
2142
2143
2144typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
2145{
2146 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
2147 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
2148 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
2149 UCHAR ucReserved[2];
2150}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
2151
2152typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
2153{
2154 union
2155 {
2156 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
2157 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
2158 };
2159} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
2160
2161/****************************************************************************/
2162// Structures used by EnableYUVTable
2163/****************************************************************************/
2164typedef struct _ENABLE_YUV_PARAMETERS
2165{
2166 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
2167 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
2168 UCHAR ucPadding[2];
2169}ENABLE_YUV_PARAMETERS;
2170#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
2171
2172/****************************************************************************/
2173// Structures used by GetMemoryClockTable
2174/****************************************************************************/
2175typedef struct _GET_MEMORY_CLOCK_PARAMETERS
2176{
2177 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2178} GET_MEMORY_CLOCK_PARAMETERS;
2179#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
2180
2181/****************************************************************************/
2182// Structures used by GetEngineClockTable
2183/****************************************************************************/
2184typedef struct _GET_ENGINE_CLOCK_PARAMETERS
2185{
2186 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2187} GET_ENGINE_CLOCK_PARAMETERS;
2188#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
2189
2190/****************************************************************************/
2191// Following Structures and constant may be obsolete
2192/****************************************************************************/
2193//Maxium 8 bytes,the data read in will be placed in the parameter space.
2194//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2195typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
2196{
2197 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2198 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
2199 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
2200 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
2201 UCHAR ucSlaveAddr; //Read from which slave
2202 UCHAR ucLineNumber; //Read from which HW assisted line
2203}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
2204#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
2205
2206
2207#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
2208#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
2209#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
2210#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
2211#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
2212
2213typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
2214{
2215 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2216 USHORT usByteOffset; //Write to which byte
2217 //Upper portion of usByteOffset is Format of data
2218 //1bytePS+offsetPS
2219 //2bytesPS+offsetPS
2220 //blockID+offsetPS
2221 //blockID+offsetID
2222 //blockID+counterID+offsetID
2223 UCHAR ucData; //PS data1
2224 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
2225 UCHAR ucSlaveAddr; //Write to which slave
2226 UCHAR ucLineNumber; //Write from which HW assisted line
2227}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
2228
2229#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
2230
2231typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
2232{
2233 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2234 UCHAR ucSlaveAddr; //Write to which slave
2235 UCHAR ucLineNumber; //Write from which HW assisted line
2236}SET_UP_HW_I2C_DATA_PARAMETERS;
2237
2238/**************************************************************************/
2239#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
2240
2241
2242/****************************************************************************/
2243// Structures used by PowerConnectorDetectionTable
2244/****************************************************************************/
2245typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
2246{
2247 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2248 UCHAR ucPwrBehaviorId;
2249 USHORT usPwrBudget; //how much power currently boot to in unit of watt
2250}POWER_CONNECTOR_DETECTION_PARAMETERS;
2251
2252typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
2253{
2254 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2255 UCHAR ucReserved;
2256 USHORT usPwrBudget; //how much power currently boot to in unit of watt
2257 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2258}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
2259
2260
2261/****************************LVDS SS Command Table Definitions**********************/
2262
2263/****************************************************************************/
2264// Structures used by EnableSpreadSpectrumOnPPLLTable
2265/****************************************************************************/
2266typedef struct _ENABLE_LVDS_SS_PARAMETERS
2267{
2268 USHORT usSpreadSpectrumPercentage;
2269 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2270 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2271 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2272 UCHAR ucPadding[3];
2273}ENABLE_LVDS_SS_PARAMETERS;
2274
2275//ucTableFormatRevision=1,ucTableContentRevision=2
2276typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
2277{
2278 USHORT usSpreadSpectrumPercentage;
2279 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2280 UCHAR ucSpreadSpectrumStep; //
2281 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2282 UCHAR ucSpreadSpectrumDelay;
2283 UCHAR ucSpreadSpectrumRange;
2284 UCHAR ucPadding;
2285}ENABLE_LVDS_SS_PARAMETERS_V2;
2286
2287//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
2288typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
2289{
2290 USHORT usSpreadSpectrumPercentage;
2291 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2292 UCHAR ucSpreadSpectrumStep; //
2293 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2294 UCHAR ucSpreadSpectrumDelay;
2295 UCHAR ucSpreadSpectrumRange;
2296 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
2297}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
2298
2299 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
2300{
2301 USHORT usSpreadSpectrumPercentage;
2302 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2303 // Bit[1]: 1-Ext. 0-Int.
2304 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2305 // Bits[7:4] reserved
2306 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2307 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2308 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
2309}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
2310
2311#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
2312#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
2313#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
2314#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
2315#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
2316#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
2317#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
2318#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
2319#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
2320#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
2321#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
2322
2323// Used by DCE5.0
2324 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
2325{
2326 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
2327 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2328 // Bit[1]: 1-Ext. 0-Int.
2329 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2330 // Bits[7:4] reserved
2331 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2332 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2333 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
2334}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
2335
2336
2337#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
2338#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
2339#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
2340#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
2341#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
2342#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
2343#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
2344#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
2345#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
2346#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
2347#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
2348#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
2349
2350#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
2351
2352typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
2353{
2354 PIXEL_CLOCK_PARAMETERS sPCLKInput;
2355 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
2356}SET_PIXEL_CLOCK_PS_ALLOCATION;
2357
2358
2359
2360#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
2361
2362/****************************************************************************/
2363// Structures used by ###
2364/****************************************************************************/
2365typedef struct _MEMORY_TRAINING_PARAMETERS
2366{
2367 ULONG ulTargetMemoryClock; //In 10Khz unit
2368}MEMORY_TRAINING_PARAMETERS;
2369#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
2370
2371
2372typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2
2373{
2374 USHORT usMemTrainingMode;
2375 USHORT usReserved;
2376}MEMORY_TRAINING_PARAMETERS_V1_2;
2377
2378//usMemTrainingMode
2379#define NORMAL_MEMORY_TRAINING_MODE 0
2380#define ENTER_DRAM_SELFREFRESH_MODE 1
2381#define EXIT_DRAM_SELFRESH_MODE 2
2382
2383/****************************LVDS and other encoder command table definitions **********************/
2384
2385
2386/****************************************************************************/
2387// Structures used by LVDSEncoderControlTable (Before DEC30)
2388// LVTMAEncoderControlTable (Before DEC30)
2389// TMDSAEncoderControlTable (Before DEC30)
2390/****************************************************************************/
2391typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
2392{
2393 USHORT usPixelClock; // in 10KHz; for bios convenient
2394 UCHAR ucMisc; // bit0=0: Enable single link
2395 // =1: Enable dual link
2396 // Bit1=0: 666RGB
2397 // =1: 888RGB
2398 UCHAR ucAction; // 0: turn off encoder
2399 // 1: setup and turn on encoder
2400}LVDS_ENCODER_CONTROL_PARAMETERS;
2401
2402#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
2403
2404#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
2405#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
2406
2407#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
2408#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2409
2410//ucTableFormatRevision=1,ucTableContentRevision=2
2411typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2412{
2413 USHORT usPixelClock; // in 10KHz; for bios convenient
2414 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2415 UCHAR ucAction; // 0: turn off encoder
2416 // 1: setup and turn on encoder
2417 UCHAR ucTruncate; // bit0=0: Disable truncate
2418 // =1: Enable truncate
2419 // bit4=0: 666RGB
2420 // =1: 888RGB
2421 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2422 // =1: Enable spatial dithering
2423 // bit4=0: 666RGB
2424 // =1: 888RGB
2425 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2426 // =1: Enable temporal dithering
2427 // bit4=0: 666RGB
2428 // =1: 888RGB
2429 // bit5=0: Gray level 2
2430 // =1: Gray level 4
2431 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2432 // =1: 25FRC_SEL pattern F
2433 // bit6:5=0: 50FRC_SEL pattern A
2434 // =1: 50FRC_SEL pattern B
2435 // =2: 50FRC_SEL pattern C
2436 // =3: 50FRC_SEL pattern D
2437 // bit7=0: 75FRC_SEL pattern E
2438 // =1: 75FRC_SEL pattern F
2439}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2440
2441#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2442
2443#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2444#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2445
2446#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2447#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2448
2449
2450#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2451#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2452
2453#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2454#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2455
2456#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2457#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2458
2459/****************************************************************************/
2460// Structures used by ###
2461/****************************************************************************/
2462typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2463{
2464 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2465 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2466 UCHAR ucPadding[2];
2467}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2468
2469typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2470{
2471 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
2472 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2473}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2474
2475#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2476typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2477{
2478 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
2479 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2480}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2481
2482typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2483{
2484 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
2485 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2486}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2487
2488/****************************************************************************/
2489// Structures used by DVOEncoderControlTable
2490/****************************************************************************/
2491//ucTableFormatRevision=1,ucTableContentRevision=3
2492//ucDVOConfig:
2493#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
2494#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
2495#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
2496#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
2497#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
2498#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
2499#define DVO_ENCODER_CONFIG_24BIT 0x08
2500
2501typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2502{
2503 USHORT usPixelClock;
2504 UCHAR ucDVOConfig;
2505 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2506 UCHAR ucReseved[4];
2507}DVO_ENCODER_CONTROL_PARAMETERS_V3;
2508#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
2509
2510typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2511{
2512 USHORT usPixelClock;
2513 UCHAR ucDVOConfig;
2514 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2515 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2516 UCHAR ucReseved[3];
2517}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
2518#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2519
2520
2521//ucTableFormatRevision=1
2522//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2523// bit1=0: non-coherent mode
2524// =1: coherent mode
2525
2526//==========================================================================================
2527//Only change is here next time when changing encoder parameter definitions again!
2528#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2529#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2530
2531#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2532#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2533
2534#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2535#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2536
2537#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
2538#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
2539
2540//==========================================================================================
2541#define PANEL_ENCODER_MISC_DUAL 0x01
2542#define PANEL_ENCODER_MISC_COHERENT 0x02
2543#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
2544#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
2545
2546#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
2547#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
2548#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2549
2550#define PANEL_ENCODER_TRUNCATE_EN 0x01
2551#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
2552#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
2553#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
2554#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
2555#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
2556#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
2557#define PANEL_ENCODER_25FRC_MASK 0x10
2558#define PANEL_ENCODER_25FRC_E 0x00
2559#define PANEL_ENCODER_25FRC_F 0x10
2560#define PANEL_ENCODER_50FRC_MASK 0x60
2561#define PANEL_ENCODER_50FRC_A 0x00
2562#define PANEL_ENCODER_50FRC_B 0x20
2563#define PANEL_ENCODER_50FRC_C 0x40
2564#define PANEL_ENCODER_50FRC_D 0x60
2565#define PANEL_ENCODER_75FRC_MASK 0x80
2566#define PANEL_ENCODER_75FRC_E 0x00
2567#define PANEL_ENCODER_75FRC_F 0x80
2568
2569/****************************************************************************/
2570// Structures used by SetVoltageTable
2571/****************************************************************************/
2572#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2573#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2574#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
2575#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2576#define SET_VOLTAGE_INIT_MODE 5
2577#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2578
2579#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
2580#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
2581#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
2582
2583#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
2584#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
2585#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
2586
2587typedef struct _SET_VOLTAGE_PARAMETERS
2588{
2589 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2590 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2591 UCHAR ucVoltageIndex; // An index to tell which voltage level
2592 UCHAR ucReserved;
2593}SET_VOLTAGE_PARAMETERS;
2594
2595typedef struct _SET_VOLTAGE_PARAMETERS_V2
2596{
2597 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2598 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2599 USHORT usVoltageLevel; // real voltage level
2600}SET_VOLTAGE_PARAMETERS_V2;
2601
2602// used by both SetVoltageTable v1.3 and v1.4
2603typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
2604{
2605 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2606 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2607 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2608}SET_VOLTAGE_PARAMETERS_V1_3;
2609
2610//ucVoltageType
2611#define VOLTAGE_TYPE_VDDC 1
2612#define VOLTAGE_TYPE_MVDDC 2
2613#define VOLTAGE_TYPE_MVDDQ 3
2614#define VOLTAGE_TYPE_VDDCI 4
2615#define VOLTAGE_TYPE_VDDGFX 5
2616#define VOLTAGE_TYPE_PCC 6
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002617#define VOLTAGE_TYPE_MVPP 7
2618#define VOLTAGE_TYPE_LEDDPM 8
2619#define VOLTAGE_TYPE_PCC_MVDD 9
2620#define VOLTAGE_TYPE_PCIE_VDDC 10
2621#define VOLTAGE_TYPE_PCIE_VDDR 11
Alex Deuchera02860aa2015-04-20 16:44:53 -04002622
2623#define VOLTAGE_TYPE_GENERIC_I2C_1 0x11
2624#define VOLTAGE_TYPE_GENERIC_I2C_2 0x12
2625#define VOLTAGE_TYPE_GENERIC_I2C_3 0x13
2626#define VOLTAGE_TYPE_GENERIC_I2C_4 0x14
2627#define VOLTAGE_TYPE_GENERIC_I2C_5 0x15
2628#define VOLTAGE_TYPE_GENERIC_I2C_6 0x16
2629#define VOLTAGE_TYPE_GENERIC_I2C_7 0x17
2630#define VOLTAGE_TYPE_GENERIC_I2C_8 0x18
2631#define VOLTAGE_TYPE_GENERIC_I2C_9 0x19
2632#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A
2633
2634//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2635#define ATOM_SET_VOLTAGE 0 //Set voltage Level
2636#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
2637#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator
2638#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3
2639#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
2640#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
2641
2642// define vitual voltage id in usVoltageLevel
2643#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
2644#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
2645#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
2646#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
2647#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05
2648#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06
2649#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07
2650#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08
2651
2652typedef struct _SET_VOLTAGE_PS_ALLOCATION
2653{
2654 SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2655 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2656}SET_VOLTAGE_PS_ALLOCATION;
2657
2658// New Added from SI for GetVoltageInfoTable, input parameter structure
2659typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2660{
2661 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2662 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2663 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2664 ULONG ulReserved;
2665}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2666
2667// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2668typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2669{
2670 ULONG ulVotlageGpioState;
2671 ULONG ulVoltageGPioMask;
2672}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2673
2674// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2675typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2676{
2677 USHORT usVoltageLevel;
2678 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2679 ULONG ulReseved;
2680}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2681
2682// GetVoltageInfo v1.1 ucVoltageMode
2683#define ATOM_GET_VOLTAGE_VID 0x00
2684#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2685#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2686#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info
2687
2688// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2689#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2690// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2691#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2692
2693#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2694#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2695
2696
2697// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2698typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
2699{
2700 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2701 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2702 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2703 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2704}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
2705
2706// New in GetVoltageInfo v1.2 ucVoltageMode
2707#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
2708
2709// New Added from CI Hawaii for EVV feature
2710typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
2711{
2712 USHORT usVoltageLevel; // real voltage level in unit of mv
2713 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2714 USHORT usTDP_Current; // TDP_Current in unit of 0.01A
2715 USHORT usTDP_Power; // TDP_Current in unit of 0.1W
2716}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
2717
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002718
2719// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2720typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
2721{
2722 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2723 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2724 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2725 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2726 ULONG ulReserved[3];
2727}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3;
2728
2729// New Added from CI Hawaii for EVV feature
2730typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3
2731{
2732 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
2733 ULONG ulReserved[4];
2734}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3;
2735
2736
2737/****************************************************************************/
2738// Structures used by GetSMUClockInfo
2739/****************************************************************************/
2740typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1
2741{
2742 ULONG ulDfsPllOutputFreq:24;
2743 ULONG ucDfsDivider:8;
2744}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1;
2745
2746typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1
2747{
2748 ULONG ulDfsOutputFreq;
2749}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1;
2750
Alex Deuchera02860aa2015-04-20 16:44:53 -04002751/****************************************************************************/
2752// Structures used by TVEncoderControlTable
2753/****************************************************************************/
2754typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2755{
2756 USHORT usPixelClock; // in 10KHz; for bios convenient
2757 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2758 UCHAR ucAction; // 0: turn off encoder
2759 // 1: setup and turn on encoder
2760}TV_ENCODER_CONTROL_PARAMETERS;
2761
2762typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2763{
2764 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2765 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
2766}TV_ENCODER_CONTROL_PS_ALLOCATION;
2767
2768//==============================Data Table Portion====================================
2769
2770
2771/****************************************************************************/
2772// Structure used in Data.mtb
2773/****************************************************************************/
2774typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2775{
2776 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2777 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2778 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2779 USHORT StandardVESA_Timing; // Only used by Bios
2780 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2781 USHORT PaletteData; // Only used by BIOS
2782 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2783 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002784 USHORT SMU_Info; // Shared by various SW components,latest version 1.1
Alex Deuchera02860aa2015-04-20 16:44:53 -04002785 USHORT SupportedDevicesInfo; // Will be obsolete from R600
2786 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2787 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2788 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2789 USHORT VESA_ToInternalModeLUT; // Only used by Bios
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002790 USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600
Alex Deuchera02860aa2015-04-20 16:44:53 -04002791 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2792 USHORT GPUVirtualizationInfo; // Will be obsolete from R600
2793 USHORT SaveRestoreInfo; // Only used by Bios
2794 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2795 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2796 USHORT XTMDS_Info; // Will be obsolete from R600
2797 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2798 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2799 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2800 USHORT MC_InitParameter; // Only used by command table
2801 USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2802 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2803 USHORT TV_VideoMode; // Only used by command table
2804 USHORT VRAM_Info; // Only used by command table, latest version 1.3
2805 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2806 USHORT IntegratedSystemInfo; // Shared by various SW components
2807 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2808 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2809 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002810 USHORT ServiceInfo;
Alex Deuchera02860aa2015-04-20 16:44:53 -04002811}ATOM_MASTER_LIST_OF_DATA_TABLES;
2812
2813typedef struct _ATOM_MASTER_DATA_TABLE
2814{
2815 ATOM_COMMON_TABLE_HEADER sHeader;
2816 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
2817}ATOM_MASTER_DATA_TABLE;
2818
2819// For backward compatible
2820#define LVDS_Info LCD_Info
2821#define DAC_Info PaletteData
2822#define TMDS_Info DIGTransmitterInfo
2823#define CompassionateData GPUVirtualizationInfo
Alex Deucher6e14e92b2015-10-15 00:43:41 -04002824#define AnalogTV_Info SMU_Info
2825#define ComponentVideoInfo GFX_Info
Alex Deuchera02860aa2015-04-20 16:44:53 -04002826
2827/****************************************************************************/
2828// Structure used in MultimediaCapabilityInfoTable
2829/****************************************************************************/
2830typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2831{
2832 ATOM_COMMON_TABLE_HEADER sHeader;
2833 ULONG ulSignature; // HW info table signature string "$ATI"
2834 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2835 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2836 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2837 UCHAR ucHostPortInfo; // Provides host port configuration information
2838}ATOM_MULTIMEDIA_CAPABILITY_INFO;
2839
2840
2841/****************************************************************************/
2842// Structure used in MultimediaConfigInfoTable
2843/****************************************************************************/
2844typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2845{
2846 ATOM_COMMON_TABLE_HEADER sHeader;
2847 ULONG ulSignature; // MM info table signature sting "$MMT"
2848 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2849 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2850 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2851 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2852 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2853 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2854 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2855 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2856 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2857 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2858 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2859 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2860}ATOM_MULTIMEDIA_CONFIG_INFO;
2861
2862
2863/****************************************************************************/
2864// Structures used in FirmwareInfoTable
2865/****************************************************************************/
2866
2867// usBIOSCapability Defintion:
2868// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2869// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2870// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2871// Others: Reserved
2872#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
2873#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
2874#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
2875#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2876#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2877#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
2878#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
2879#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
2880#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
2881#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
2882#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2883#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
2884#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2885#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2886
2887
2888#ifndef _H2INC
2889
2890//Please don't add or expand this bitfield structure below, this one will retire soon.!
2891typedef struct _ATOM_FIRMWARE_CAPABILITY
2892{
2893#if ATOM_BIG_ENDIAN
2894 USHORT Reserved:1;
2895 USHORT SCL2Redefined:1;
2896 USHORT PostWithoutModeSet:1;
2897 USHORT HyperMemory_Size:4;
2898 USHORT HyperMemory_Support:1;
2899 USHORT PPMode_Assigned:1;
2900 USHORT WMI_SUPPORT:1;
2901 USHORT GPUControlsBL:1;
2902 USHORT EngineClockSS_Support:1;
2903 USHORT MemoryClockSS_Support:1;
2904 USHORT ExtendedDesktopSupport:1;
2905 USHORT DualCRTC_Support:1;
2906 USHORT FirmwarePosted:1;
2907#else
2908 USHORT FirmwarePosted:1;
2909 USHORT DualCRTC_Support:1;
2910 USHORT ExtendedDesktopSupport:1;
2911 USHORT MemoryClockSS_Support:1;
2912 USHORT EngineClockSS_Support:1;
2913 USHORT GPUControlsBL:1;
2914 USHORT WMI_SUPPORT:1;
2915 USHORT PPMode_Assigned:1;
2916 USHORT HyperMemory_Support:1;
2917 USHORT HyperMemory_Size:4;
2918 USHORT PostWithoutModeSet:1;
2919 USHORT SCL2Redefined:1;
2920 USHORT Reserved:1;
2921#endif
2922}ATOM_FIRMWARE_CAPABILITY;
2923
2924typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2925{
2926 ATOM_FIRMWARE_CAPABILITY sbfAccess;
2927 USHORT susAccess;
2928}ATOM_FIRMWARE_CAPABILITY_ACCESS;
2929
2930#else
2931
2932typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2933{
2934 USHORT susAccess;
2935}ATOM_FIRMWARE_CAPABILITY_ACCESS;
2936
2937#endif
2938
2939typedef struct _ATOM_FIRMWARE_INFO
2940{
2941 ATOM_COMMON_TABLE_HEADER sHeader;
2942 ULONG ulFirmwareRevision;
2943 ULONG ulDefaultEngineClock; //In 10Khz unit
2944 ULONG ulDefaultMemoryClock; //In 10Khz unit
2945 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2946 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2947 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2948 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2949 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2950 ULONG ulASICMaxEngineClock; //In 10Khz unit
2951 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2952 UCHAR ucASICMaxTemperature;
2953 UCHAR ucPadding[3]; //Don't use them
2954 ULONG aulReservedForBIOS[3]; //Don't use them
2955 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2956 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2957 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2958 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2959 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2960 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2961 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2962 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2963 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2964 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2965 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2966 USHORT usReferenceClock; //In 10Khz unit
2967 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2968 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2969 UCHAR ucDesign_ID; //Indicate what is the board design
2970 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2971}ATOM_FIRMWARE_INFO;
2972
2973typedef struct _ATOM_FIRMWARE_INFO_V1_2
2974{
2975 ATOM_COMMON_TABLE_HEADER sHeader;
2976 ULONG ulFirmwareRevision;
2977 ULONG ulDefaultEngineClock; //In 10Khz unit
2978 ULONG ulDefaultMemoryClock; //In 10Khz unit
2979 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2980 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2981 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2982 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2983 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2984 ULONG ulASICMaxEngineClock; //In 10Khz unit
2985 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2986 UCHAR ucASICMaxTemperature;
2987 UCHAR ucMinAllowedBL_Level;
2988 UCHAR ucPadding[2]; //Don't use them
2989 ULONG aulReservedForBIOS[2]; //Don't use them
2990 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2991 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2992 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2993 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2994 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2995 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2996 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2997 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2998 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2999 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3000 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3001 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3002 USHORT usReferenceClock; //In 10Khz unit
3003 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3004 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3005 UCHAR ucDesign_ID; //Indicate what is the board design
3006 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3007}ATOM_FIRMWARE_INFO_V1_2;
3008
3009typedef struct _ATOM_FIRMWARE_INFO_V1_3
3010{
3011 ATOM_COMMON_TABLE_HEADER sHeader;
3012 ULONG ulFirmwareRevision;
3013 ULONG ulDefaultEngineClock; //In 10Khz unit
3014 ULONG ulDefaultMemoryClock; //In 10Khz unit
3015 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3016 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3017 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3018 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3019 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3020 ULONG ulASICMaxEngineClock; //In 10Khz unit
3021 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3022 UCHAR ucASICMaxTemperature;
3023 UCHAR ucMinAllowedBL_Level;
3024 UCHAR ucPadding[2]; //Don't use them
3025 ULONG aulReservedForBIOS; //Don't use them
3026 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3027 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3028 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3029 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3030 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3031 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3032 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3033 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3034 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3035 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3036 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3037 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3038 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3039 USHORT usReferenceClock; //In 10Khz unit
3040 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3041 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3042 UCHAR ucDesign_ID; //Indicate what is the board design
3043 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3044}ATOM_FIRMWARE_INFO_V1_3;
3045
3046typedef struct _ATOM_FIRMWARE_INFO_V1_4
3047{
3048 ATOM_COMMON_TABLE_HEADER sHeader;
3049 ULONG ulFirmwareRevision;
3050 ULONG ulDefaultEngineClock; //In 10Khz unit
3051 ULONG ulDefaultMemoryClock; //In 10Khz unit
3052 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3053 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3054 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3055 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3056 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3057 ULONG ulASICMaxEngineClock; //In 10Khz unit
3058 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3059 UCHAR ucASICMaxTemperature;
3060 UCHAR ucMinAllowedBL_Level;
3061 USHORT usBootUpVDDCVoltage; //In MV unit
3062 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3063 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3064 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3065 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3066 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3067 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3068 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3069 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3070 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3071 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3072 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3073 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3074 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3075 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3076 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3077 USHORT usReferenceClock; //In 10Khz unit
3078 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3079 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3080 UCHAR ucDesign_ID; //Indicate what is the board design
3081 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3082}ATOM_FIRMWARE_INFO_V1_4;
3083
3084//the structure below to be used from Cypress
3085typedef struct _ATOM_FIRMWARE_INFO_V2_1
3086{
3087 ATOM_COMMON_TABLE_HEADER sHeader;
3088 ULONG ulFirmwareRevision;
3089 ULONG ulDefaultEngineClock; //In 10Khz unit
3090 ULONG ulDefaultMemoryClock; //In 10Khz unit
3091 ULONG ulReserved1;
3092 ULONG ulReserved2;
3093 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3094 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3095 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3096 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
3097 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3098 UCHAR ucReserved1; //Was ucASICMaxTemperature;
3099 UCHAR ucMinAllowedBL_Level;
3100 USHORT usBootUpVDDCVoltage; //In MV unit
3101 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3102 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3103 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3104 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3105 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3106 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3107 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3108 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3109 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3110 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3111 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3112 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3113 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3114 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3115 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3116 USHORT usCoreReferenceClock; //In 10Khz unit
3117 USHORT usMemoryReferenceClock; //In 10Khz unit
3118 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3119 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3120 UCHAR ucReserved4[3];
3121
3122}ATOM_FIRMWARE_INFO_V2_1;
3123
3124//the structure below to be used from NI
3125//ucTableFormatRevision=2
3126//ucTableContentRevision=2
3127
3128typedef struct _PRODUCT_BRANDING
3129{
3130 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3131 UCHAR ucReserved:2; // Bit[3:2] Reserved
3132 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3133}PRODUCT_BRANDING;
3134
3135typedef struct _ATOM_FIRMWARE_INFO_V2_2
3136{
3137 ATOM_COMMON_TABLE_HEADER sHeader;
3138 ULONG ulFirmwareRevision;
3139 ULONG ulDefaultEngineClock; //In 10Khz unit
3140 ULONG ulDefaultMemoryClock; //In 10Khz unit
3141 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3142 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3143 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3144 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3145 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3146 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
3147 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
3148 UCHAR ucReserved3; //Was ucASICMaxTemperature;
3149 UCHAR ucMinAllowedBL_Level;
3150 USHORT usBootUpVDDCVoltage; //In MV unit
3151 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3152 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3153 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3154 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3155 UCHAR ucRemoteDisplayConfig;
3156 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
3157 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
3158 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
3159 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
3160 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3161 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3162 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
3163 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3164 USHORT usCoreReferenceClock; //In 10Khz unit
3165 USHORT usMemoryReferenceClock; //In 10Khz unit
3166 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3167 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3168 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
3169 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level.
3170 UCHAR ucReserved9;
3171 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
3172 USHORT usBootUpVDDGFXVoltage; //In unit of mv;
3173 ULONG ulReserved10[3]; // New added comparing to previous version
3174}ATOM_FIRMWARE_INFO_V2_2;
3175
3176#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
3177
3178
3179// definition of ucRemoteDisplayConfig
3180#define REMOTE_DISPLAY_DISABLE 0x00
3181#define REMOTE_DISPLAY_ENABLE 0x01
3182
3183/****************************************************************************/
3184// Structures used in IntegratedSystemInfoTable
3185/****************************************************************************/
3186#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
3187#define IGP_CAP_FLAG_AC_CARD 0x4
3188#define IGP_CAP_FLAG_SDVO_CARD 0x8
3189#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
3190
3191typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
3192{
3193 ATOM_COMMON_TABLE_HEADER sHeader;
3194 ULONG ulBootUpEngineClock; //in 10kHz unit
3195 ULONG ulBootUpMemoryClock; //in 10kHz unit
3196 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3197 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3198 UCHAR ucNumberOfCyclesInPeriodHi;
3199 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
3200 USHORT usReserved1;
3201 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
3202 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
3203 ULONG ulReserved[2];
3204
3205 USHORT usFSBClock; //In MHz unit
3206 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
3207 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
3208 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3209 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
3210 USHORT usK8MemoryClock; //in MHz unit
3211 USHORT usK8SyncStartDelay; //in 0.01 us unit
3212 USHORT usK8DataReturnTime; //in 0.01 us unit
3213 UCHAR ucMaxNBVoltage;
3214 UCHAR ucMinNBVoltage;
3215 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
3216 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
3217 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
3218 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
3219 UCHAR ucMaxNBVoltageHigh;
3220 UCHAR ucMinNBVoltageHigh;
3221}ATOM_INTEGRATED_SYSTEM_INFO;
3222
3223/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
3224ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
3225 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3226ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
3227 For AMD IGP,for now this can be 0
3228ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
3229 For AMD IGP,for now this can be 0
3230
3231usFSBClock: For Intel IGP,it's FSB Freq
3232 For AMD IGP,it's HT Link Speed
3233
3234usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
3235usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
3236usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
3237
3238VC:Voltage Control
3239ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
3240ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
3241
3242ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
3243ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
3244
3245ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
3246ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
3247
3248
3249usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
3250usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
3251*/
3252
3253
3254/*
3255The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
3256Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
3257The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
3258
3259SW components can access the IGP system infor structure in the same way as before
3260*/
3261
3262
3263typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
3264{
3265 ATOM_COMMON_TABLE_HEADER sHeader;
3266 ULONG ulBootUpEngineClock; //in 10kHz unit
3267 ULONG ulReserved1[2]; //must be 0x0 for the reserved
3268 ULONG ulBootUpUMAClock; //in 10kHz unit
3269 ULONG ulBootUpSidePortClock; //in 10kHz unit
3270 ULONG ulMinSidePortClock; //in 10kHz unit
3271 ULONG ulReserved2[6]; //must be 0x0 for the reserved
3272 ULONG ulSystemConfig; //see explanation below
3273 ULONG ulBootUpReqDisplayVector;
3274 ULONG ulOtherDisplayMisc;
3275 ULONG ulDDISlot1Config;
3276 ULONG ulDDISlot2Config;
3277 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3278 UCHAR ucUMAChannelNumber;
3279 UCHAR ucDockingPinBit;
3280 UCHAR ucDockingPinPolarity;
3281 ULONG ulDockingPinCFGInfo;
3282 ULONG ulCPUCapInfo;
3283 USHORT usNumberOfCyclesInPeriod;
3284 USHORT usMaxNBVoltage;
3285 USHORT usMinNBVoltage;
3286 USHORT usBootUpNBVoltage;
3287 ULONG ulHTLinkFreq; //in 10Khz
3288 USHORT usMinHTLinkWidth;
3289 USHORT usMaxHTLinkWidth;
3290 USHORT usUMASyncStartDelay;
3291 USHORT usUMADataReturnTime;
3292 USHORT usLinkStatusZeroTime;
3293 USHORT usDACEfuse; //for storing badgap value (for RS880 only)
3294 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3295 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3296 USHORT usMaxUpStreamHTLinkWidth;
3297 USHORT usMaxDownStreamHTLinkWidth;
3298 USHORT usMinUpStreamHTLinkWidth;
3299 USHORT usMinDownStreamHTLinkWidth;
3300 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
3301 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3302 ULONG ulReserved3[96]; //must be 0x0
3303}ATOM_INTEGRATED_SYSTEM_INFO_V2;
3304
3305/*
3306ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3307ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3308ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
3309
3310ulSystemConfig:
3311Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3312Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
3313 =0: system boots up at driver control state. Power state depends on PowerPlay table.
3314Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
3315Bit[3]=1: Only one power state(Performance) will be supported.
3316 =0: Multiple power states supported from PowerPlay table.
3317Bit[4]=1: CLMC is supported and enabled on current system.
3318 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
3319Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
3320 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
3321Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
3322 =0: Voltage settings is determined by powerplay table.
3323Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
3324 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
3325Bit[8]=1: CDLF is supported and enabled on current system.
3326 =0: CDLF is not supported or enabled on current system.
3327Bit[9]=1: DLL Shut Down feature is enabled on current system.
3328 =0: DLL Shut Down feature is not enabled or supported on current system.
3329
3330ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
3331
3332ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3333 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
3334
3335ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
3336 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
3337 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
3338 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
3339 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
3340 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
3341
3342 [15:8] - Lane configuration attribute;
3343 [23:16]- Connector type, possible value:
3344 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
3345 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
3346 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
3347 CONNECTOR_OBJECT_ID_DISPLAYPORT
3348 CONNECTOR_OBJECT_ID_eDP
3349 [31:24]- Reserved
3350
3351ulDDISlot2Config: Same as Slot1.
3352ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
3353For IGP, Hypermemory is the only memory type showed in CCC.
3354
3355ucUMAChannelNumber: how many channels for the UMA;
3356
3357ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
3358ucDockingPinBit: which bit in this register to read the pin status;
3359ucDockingPinPolarity:Polarity of the pin when docked;
3360
3361ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
3362
3363usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
3364
3365usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
3366usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
3367 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
3368 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
3369 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
3370
3371usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3372
3373
3374ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
3375usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
3376 If CDLW enabled, both upstream and downstream width should be the same during bootup.
3377usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
3378 If CDLW enabled, both upstream and downstream width should be the same during bootup.
3379
3380usUMASyncStartDelay: Memory access latency, required for watermark calculation
3381usUMADataReturnTime: Memory access latency, required for watermark calculation
3382usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
3383for Griffin or Greyhound. SBIOS needs to convert to actual time by:
3384 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
3385 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
3386 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
3387 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
3388
3389ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
3390 This must be less than or equal to ulHTLinkFreq(bootup frequency).
3391ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
3392 This must be less than or equal to ulHighVoltageHTLinkFreq.
3393
3394usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
3395usMaxDownStreamHTLinkWidth: same as above.
3396usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
3397usMinDownStreamHTLinkWidth: same as above.
3398*/
3399
3400// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3401#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
3402#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
3403#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
3404#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
3405#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
3406#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
3407
3408#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
3409
3410#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
3411#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
3412#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
3413#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
3414#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
3415#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
3416#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
3417#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
3418#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
3419#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
3420
3421#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
3422
3423#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
3424#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
3425#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
3426#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
3427#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
3428#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
3429
3430#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
3431#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
3432#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
3433
3434#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
3435
3436// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
3437typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
3438{
3439 ATOM_COMMON_TABLE_HEADER sHeader;
3440 ULONG ulBootUpEngineClock; //in 10kHz unit
3441 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
3442 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
3443 ULONG ulBootUpUMAClock; //in 10kHz unit
3444 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3445 ULONG ulBootUpReqDisplayVector;
3446 ULONG ulOtherDisplayMisc;
3447 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3448 ULONG ulSystemConfig; //TBD
3449 ULONG ulCPUCapInfo; //TBD
3450 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3451 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3452 USHORT usBootUpNBVoltage; //boot up NB voltage
3453 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
3454 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
3455 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3456 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3457 ULONG ulDDISlot2Config;
3458 ULONG ulDDISlot3Config;
3459 ULONG ulDDISlot4Config;
3460 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3461 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3462 UCHAR ucUMAChannelNumber;
3463 USHORT usReserved;
3464 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3465 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3466 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3467 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3468 ULONG ulReserved6[61]; //must be 0x0
3469}ATOM_INTEGRATED_SYSTEM_INFO_V5;
3470
3471
3472
3473/****************************************************************************/
3474// Structure used in GPUVirtualizationInfoTable
3475/****************************************************************************/
3476typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1
3477{
3478 ATOM_COMMON_TABLE_HEADER sHeader;
3479 ULONG ulMCUcodeRomStartAddr;
3480 ULONG ulMCUcodeLength;
3481 ULONG ulSMCUcodeRomStartAddr;
3482 ULONG ulSMCUcodeLength;
3483 ULONG ulRLCVUcodeRomStartAddr;
3484 ULONG ulRLCVUcodeLength;
3485 ULONG ulTOCUcodeStartAddr;
3486 ULONG ulTOCUcodeLength;
3487 ULONG ulSMCPatchTableStartAddr;
3488 ULONG ulSmcPatchTableLength;
3489 ULONG ulSystemFlag;
3490}ATOM_GPU_VIRTUALIZATION_INFO_V2_1;
3491
3492
3493#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
3494#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
3495#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
3496#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
3497#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
3498#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
3499#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
3500#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
3501#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
3502#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
3503#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
3504#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
3505#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
3506#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
3507
3508// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3509#define ASIC_INT_DAC1_ENCODER_ID 0x00
3510#define ASIC_INT_TV_ENCODER_ID 0x02
3511#define ASIC_INT_DIG1_ENCODER_ID 0x03
3512#define ASIC_INT_DAC2_ENCODER_ID 0x04
3513#define ASIC_EXT_TV_ENCODER_ID 0x06
3514#define ASIC_INT_DVO_ENCODER_ID 0x07
3515#define ASIC_INT_DIG2_ENCODER_ID 0x09
3516#define ASIC_EXT_DIG_ENCODER_ID 0x05
3517#define ASIC_EXT_DIG2_ENCODER_ID 0x08
3518#define ASIC_INT_DIG3_ENCODER_ID 0x0a
3519#define ASIC_INT_DIG4_ENCODER_ID 0x0b
3520#define ASIC_INT_DIG5_ENCODER_ID 0x0c
3521#define ASIC_INT_DIG6_ENCODER_ID 0x0d
3522#define ASIC_INT_DIG7_ENCODER_ID 0x0e
3523
3524//define Encoder attribute
3525#define ATOM_ANALOG_ENCODER 0
3526#define ATOM_DIGITAL_ENCODER 1
3527#define ATOM_DP_ENCODER 2
3528
3529#define ATOM_ENCODER_ENUM_MASK 0x70
3530#define ATOM_ENCODER_ENUM_ID1 0x00
3531#define ATOM_ENCODER_ENUM_ID2 0x10
3532#define ATOM_ENCODER_ENUM_ID3 0x20
3533#define ATOM_ENCODER_ENUM_ID4 0x30
3534#define ATOM_ENCODER_ENUM_ID5 0x40
3535#define ATOM_ENCODER_ENUM_ID6 0x50
3536
3537#define ATOM_DEVICE_CRT1_INDEX 0x00000000
3538#define ATOM_DEVICE_LCD1_INDEX 0x00000001
3539#define ATOM_DEVICE_TV1_INDEX 0x00000002
3540#define ATOM_DEVICE_DFP1_INDEX 0x00000003
3541#define ATOM_DEVICE_CRT2_INDEX 0x00000004
3542#define ATOM_DEVICE_LCD2_INDEX 0x00000005
3543#define ATOM_DEVICE_DFP6_INDEX 0x00000006
3544#define ATOM_DEVICE_DFP2_INDEX 0x00000007
3545#define ATOM_DEVICE_CV_INDEX 0x00000008
3546#define ATOM_DEVICE_DFP3_INDEX 0x00000009
3547#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
3548#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
3549
3550#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
3551#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
3552#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
3553#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
3554#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3555#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
3556#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3557
3558#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3559
3560#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
3561#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
3562#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
3563#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
3564#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
3565#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
3566#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
3567#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
3568#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
3569#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
3570#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
3571#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
3572
3573
3574#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3575#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3576#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT
3577#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3578
3579#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
3580#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
3581#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
3582#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
3583#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
3584#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
3585#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
3586#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
3587#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
3588#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
3589#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
3590#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
3591#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
3592#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
3593#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
3594
3595
3596#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
3597#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
3598#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
3599#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
3600#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
3601#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
3602
3603#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
3604
3605#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
3606#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
3607
3608#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
3609#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
3610#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
3611#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
3612#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
3613#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
3614
3615#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
3616#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
3617#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
3618#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
3619
3620// usDeviceSupport:
3621// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3622// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3623// Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3624// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3625// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3626// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3627// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3628// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3629// Bit 8 = 0 - no CV support= 1- CV is supported
3630// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3631// Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3632// Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3633//
3634//
3635
3636/****************************************************************************/
3637// Structure used in MclkSS_InfoTable
3638/****************************************************************************/
3639// ucI2C_ConfigID
3640// [7:0] - I2C LINE Associate ID
3641// = 0 - no I2C
3642// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3643// = 0, [6:0]=SW assisted I2C ID
3644// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3645// = 2, HW engine for Multimedia use
3646// = 3-7 Reserved for future I2C engines
3647// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3648
3649typedef struct _ATOM_I2C_ID_CONFIG
3650{
3651#if ATOM_BIG_ENDIAN
3652 UCHAR bfHW_Capable:1;
3653 UCHAR bfHW_EngineID:3;
3654 UCHAR bfI2C_LineMux:4;
3655#else
3656 UCHAR bfI2C_LineMux:4;
3657 UCHAR bfHW_EngineID:3;
3658 UCHAR bfHW_Capable:1;
3659#endif
3660}ATOM_I2C_ID_CONFIG;
3661
3662typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3663{
3664 ATOM_I2C_ID_CONFIG sbfAccess;
3665 UCHAR ucAccess;
3666}ATOM_I2C_ID_CONFIG_ACCESS;
3667
3668
3669/****************************************************************************/
3670// Structure used in GPIO_I2C_InfoTable
3671/****************************************************************************/
3672typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3673{
3674 USHORT usClkMaskRegisterIndex;
3675 USHORT usClkEnRegisterIndex;
3676 USHORT usClkY_RegisterIndex;
3677 USHORT usClkA_RegisterIndex;
3678 USHORT usDataMaskRegisterIndex;
3679 USHORT usDataEnRegisterIndex;
3680 USHORT usDataY_RegisterIndex;
3681 USHORT usDataA_RegisterIndex;
3682 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3683 UCHAR ucClkMaskShift;
3684 UCHAR ucClkEnShift;
3685 UCHAR ucClkY_Shift;
3686 UCHAR ucClkA_Shift;
3687 UCHAR ucDataMaskShift;
3688 UCHAR ucDataEnShift;
3689 UCHAR ucDataY_Shift;
3690 UCHAR ucDataA_Shift;
3691 UCHAR ucReserved1;
3692 UCHAR ucReserved2;
3693}ATOM_GPIO_I2C_ASSIGMENT;
3694
3695typedef struct _ATOM_GPIO_I2C_INFO
3696{
3697 ATOM_COMMON_TABLE_HEADER sHeader;
3698 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3699}ATOM_GPIO_I2C_INFO;
3700
3701/****************************************************************************/
3702// Common Structure used in other structures
3703/****************************************************************************/
3704
3705#ifndef _H2INC
3706
3707//Please don't add or expand this bitfield structure below, this one will retire soon.!
3708typedef struct _ATOM_MODE_MISC_INFO
3709{
3710#if ATOM_BIG_ENDIAN
3711 USHORT Reserved:6;
3712 USHORT RGB888:1;
3713 USHORT DoubleClock:1;
3714 USHORT Interlace:1;
3715 USHORT CompositeSync:1;
3716 USHORT V_ReplicationBy2:1;
3717 USHORT H_ReplicationBy2:1;
3718 USHORT VerticalCutOff:1;
3719 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3720 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3721 USHORT HorizontalCutOff:1;
3722#else
3723 USHORT HorizontalCutOff:1;
3724 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3725 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3726 USHORT VerticalCutOff:1;
3727 USHORT H_ReplicationBy2:1;
3728 USHORT V_ReplicationBy2:1;
3729 USHORT CompositeSync:1;
3730 USHORT Interlace:1;
3731 USHORT DoubleClock:1;
3732 USHORT RGB888:1;
3733 USHORT Reserved:6;
3734#endif
3735}ATOM_MODE_MISC_INFO;
3736
3737typedef union _ATOM_MODE_MISC_INFO_ACCESS
3738{
3739 ATOM_MODE_MISC_INFO sbfAccess;
3740 USHORT usAccess;
3741}ATOM_MODE_MISC_INFO_ACCESS;
3742
3743#else
3744
3745typedef union _ATOM_MODE_MISC_INFO_ACCESS
3746{
3747 USHORT usAccess;
3748}ATOM_MODE_MISC_INFO_ACCESS;
3749
3750#endif
3751
3752// usModeMiscInfo-
3753#define ATOM_H_CUTOFF 0x01
3754#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3755#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3756#define ATOM_V_CUTOFF 0x08
3757#define ATOM_H_REPLICATIONBY2 0x10
3758#define ATOM_V_REPLICATIONBY2 0x20
3759#define ATOM_COMPOSITESYNC 0x40
3760#define ATOM_INTERLACE 0x80
3761#define ATOM_DOUBLE_CLOCK_MODE 0x100
3762#define ATOM_RGB888_MODE 0x200
3763
3764//usRefreshRate-
3765#define ATOM_REFRESH_43 43
3766#define ATOM_REFRESH_47 47
3767#define ATOM_REFRESH_56 56
3768#define ATOM_REFRESH_60 60
3769#define ATOM_REFRESH_65 65
3770#define ATOM_REFRESH_70 70
3771#define ATOM_REFRESH_72 72
3772#define ATOM_REFRESH_75 75
3773#define ATOM_REFRESH_85 85
3774
3775// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3776// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3777//
3778// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3779// = EDID_HA + EDID_HBL
3780// VESA_HDISP = VESA_ACTIVE = EDID_HA
3781// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3782// = EDID_HA + EDID_HSO
3783// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
3784// VESA_BORDER = EDID_BORDER
3785
3786
3787/****************************************************************************/
3788// Structure used in SetCRTC_UsingDTDTimingTable
3789/****************************************************************************/
3790typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3791{
3792 USHORT usH_Size;
3793 USHORT usH_Blanking_Time;
3794 USHORT usV_Size;
3795 USHORT usV_Blanking_Time;
3796 USHORT usH_SyncOffset;
3797 USHORT usH_SyncWidth;
3798 USHORT usV_SyncOffset;
3799 USHORT usV_SyncWidth;
3800 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3801 UCHAR ucH_Border; // From DFP EDID
3802 UCHAR ucV_Border;
3803 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3804 UCHAR ucPadding[3];
3805}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3806
3807/****************************************************************************/
3808// Structure used in SetCRTC_TimingTable
3809/****************************************************************************/
3810typedef struct _SET_CRTC_TIMING_PARAMETERS
3811{
3812 USHORT usH_Total; // horizontal total
3813 USHORT usH_Disp; // horizontal display
3814 USHORT usH_SyncStart; // horozontal Sync start
3815 USHORT usH_SyncWidth; // horizontal Sync width
3816 USHORT usV_Total; // vertical total
3817 USHORT usV_Disp; // vertical display
3818 USHORT usV_SyncStart; // vertical Sync start
3819 USHORT usV_SyncWidth; // vertical Sync width
3820 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3821 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3822 UCHAR ucOverscanRight; // right
3823 UCHAR ucOverscanLeft; // left
3824 UCHAR ucOverscanBottom; // bottom
3825 UCHAR ucOverscanTop; // top
3826 UCHAR ucReserved;
3827}SET_CRTC_TIMING_PARAMETERS;
3828#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3829
3830
3831/****************************************************************************/
3832// Structure used in StandardVESA_TimingTable
3833// AnalogTV_InfoTable
3834// ComponentVideoInfoTable
3835/****************************************************************************/
3836typedef struct _ATOM_MODE_TIMING
3837{
3838 USHORT usCRTC_H_Total;
3839 USHORT usCRTC_H_Disp;
3840 USHORT usCRTC_H_SyncStart;
3841 USHORT usCRTC_H_SyncWidth;
3842 USHORT usCRTC_V_Total;
3843 USHORT usCRTC_V_Disp;
3844 USHORT usCRTC_V_SyncStart;
3845 USHORT usCRTC_V_SyncWidth;
3846 USHORT usPixelClock; //in 10Khz unit
3847 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3848 USHORT usCRTC_OverscanRight;
3849 USHORT usCRTC_OverscanLeft;
3850 USHORT usCRTC_OverscanBottom;
3851 USHORT usCRTC_OverscanTop;
3852 USHORT usReserve;
3853 UCHAR ucInternalModeNumber;
3854 UCHAR ucRefreshRate;
3855}ATOM_MODE_TIMING;
3856
3857typedef struct _ATOM_DTD_FORMAT
3858{
3859 USHORT usPixClk;
3860 USHORT usHActive;
3861 USHORT usHBlanking_Time;
3862 USHORT usVActive;
3863 USHORT usVBlanking_Time;
3864 USHORT usHSyncOffset;
3865 USHORT usHSyncWidth;
3866 USHORT usVSyncOffset;
3867 USHORT usVSyncWidth;
3868 USHORT usImageHSize;
3869 USHORT usImageVSize;
3870 UCHAR ucHBorder;
3871 UCHAR ucVBorder;
3872 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3873 UCHAR ucInternalModeNumber;
3874 UCHAR ucRefreshRate;
3875}ATOM_DTD_FORMAT;
3876
3877/****************************************************************************/
3878// Structure used in LVDS_InfoTable
3879// * Need a document to describe this table
3880/****************************************************************************/
3881#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
3882#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
3883#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
3884#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
3885#define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040
3886
3887//ucTableFormatRevision=1
3888//ucTableContentRevision=1
3889typedef struct _ATOM_LVDS_INFO
3890{
3891 ATOM_COMMON_TABLE_HEADER sHeader;
3892 ATOM_DTD_FORMAT sLCDTiming;
3893 USHORT usModePatchTableOffset;
3894 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3895 USHORT usOffDelayInMs;
3896 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3897 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3898 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3899 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3900 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3901 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3902 UCHAR ucPanelDefaultRefreshRate;
3903 UCHAR ucPanelIdentification;
3904 UCHAR ucSS_Id;
3905}ATOM_LVDS_INFO;
3906
3907//ucTableFormatRevision=1
3908//ucTableContentRevision=2
3909typedef struct _ATOM_LVDS_INFO_V12
3910{
3911 ATOM_COMMON_TABLE_HEADER sHeader;
3912 ATOM_DTD_FORMAT sLCDTiming;
3913 USHORT usExtInfoTableOffset;
3914 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3915 USHORT usOffDelayInMs;
3916 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3917 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3918 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3919 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3920 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3921 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3922 UCHAR ucPanelDefaultRefreshRate;
3923 UCHAR ucPanelIdentification;
3924 UCHAR ucSS_Id;
3925 USHORT usLCDVenderID;
3926 USHORT usLCDProductID;
3927 UCHAR ucLCDPanel_SpecialHandlingCap;
3928 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3929 UCHAR ucReserved[2];
3930}ATOM_LVDS_INFO_V12;
3931
3932//Definitions for ucLCDPanel_SpecialHandlingCap:
3933
3934//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3935//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3936#define LCDPANEL_CAP_READ_EDID 0x1
3937
3938//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3939//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3940//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3941#define LCDPANEL_CAP_DRR_SUPPORTED 0x2
3942
3943//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3944#define LCDPANEL_CAP_eDP 0x4
3945
3946
3947//Color Bit Depth definition in EDID V1.4 @BYTE 14h
3948//Bit 6 5 4
3949 // 0 0 0 - Color bit depth is undefined
3950 // 0 0 1 - 6 Bits per Primary Color
3951 // 0 1 0 - 8 Bits per Primary Color
3952 // 0 1 1 - 10 Bits per Primary Color
3953 // 1 0 0 - 12 Bits per Primary Color
3954 // 1 0 1 - 14 Bits per Primary Color
3955 // 1 1 0 - 16 Bits per Primary Color
3956 // 1 1 1 - Reserved
3957
3958#define PANEL_COLOR_BIT_DEPTH_MASK 0x70
3959
3960// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3961#define PANEL_RANDOM_DITHER 0x80
3962#define PANEL_RANDOM_DITHER_MASK 0x80
3963
3964#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3965
3966
3967typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT
3968{
3969 UCHAR ucSupportedRefreshRate;
3970 UCHAR ucMinRefreshRateForDRR;
3971}ATOM_LCD_REFRESH_RATE_SUPPORT;
3972
3973/****************************************************************************/
3974// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3975// ASIC Families: NI
3976// ucTableFormatRevision=1
3977// ucTableContentRevision=3
3978/****************************************************************************/
3979typedef struct _ATOM_LCD_INFO_V13
3980{
3981 ATOM_COMMON_TABLE_HEADER sHeader;
3982 ATOM_DTD_FORMAT sLCDTiming;
3983 USHORT usExtInfoTableOffset;
3984 union
3985 {
3986 USHORT usSupportedRefreshRate;
3987 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport;
3988 };
3989 ULONG ulReserved0;
3990 UCHAR ucLCD_Misc; // Reorganized in V13
3991 // Bit0: {=0:single, =1:dual},
3992 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3993 // Bit3:2: {Grey level}
3994 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3995 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3996 UCHAR ucPanelDefaultRefreshRate;
3997 UCHAR ucPanelIdentification;
3998 UCHAR ucSS_Id;
3999 USHORT usLCDVenderID;
4000 USHORT usLCDProductID;
4001 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
4002 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
4003 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
4004 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
4005 // Bit7-3: Reserved
4006 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
4007 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
4008
4009 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
4010 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
4011 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
4012 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
4013
4014 UCHAR ucOffDelay_in4Ms;
4015 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
4016 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
4017 UCHAR ucReserved1;
4018
4019 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
4020 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
4021 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
4022 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
4023
4024 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
4025 UCHAR uceDPToLVDSRxId;
4026 UCHAR ucLcdReservd;
4027 ULONG ulReserved[2];
4028}ATOM_LCD_INFO_V13;
4029
4030#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
4031
4032//Definitions for ucLCD_Misc
4033#define ATOM_PANEL_MISC_V13_DUAL 0x00000001
4034#define ATOM_PANEL_MISC_V13_FPDI 0x00000002
4035#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
4036#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
4037#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
4038#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
4039#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
4040
4041//Color Bit Depth definition in EDID V1.4 @BYTE 14h
4042//Bit 6 5 4
4043 // 0 0 0 - Color bit depth is undefined
4044 // 0 0 1 - 6 Bits per Primary Color
4045 // 0 1 0 - 8 Bits per Primary Color
4046 // 0 1 1 - 10 Bits per Primary Color
4047 // 1 0 0 - 12 Bits per Primary Color
4048 // 1 0 1 - 14 Bits per Primary Color
4049 // 1 1 0 - 16 Bits per Primary Color
4050 // 1 1 1 - Reserved
4051
4052//Definitions for ucLCDPanel_SpecialHandlingCap:
4053
4054//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
4055//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
4056#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
4057
4058//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
4059//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
4060//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
4061#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
4062
4063//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
4064#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
4065
4066//uceDPToLVDSRxId
4067#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4068#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
4069#define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init
4070
4071typedef struct _ATOM_PATCH_RECORD_MODE
4072{
4073 UCHAR ucRecordType;
4074 USHORT usHDisp;
4075 USHORT usVDisp;
4076}ATOM_PATCH_RECORD_MODE;
4077
4078typedef struct _ATOM_LCD_RTS_RECORD
4079{
4080 UCHAR ucRecordType;
4081 UCHAR ucRTSValue;
4082}ATOM_LCD_RTS_RECORD;
4083
4084//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
4085// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
4086typedef struct _ATOM_LCD_MODE_CONTROL_CAP
4087{
4088 UCHAR ucRecordType;
4089 USHORT usLCDCap;
4090}ATOM_LCD_MODE_CONTROL_CAP;
4091
4092#define LCD_MODE_CAP_BL_OFF 1
4093#define LCD_MODE_CAP_CRTC_OFF 2
4094#define LCD_MODE_CAP_PANEL_OFF 4
4095
4096
4097typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
4098{
4099 UCHAR ucRecordType;
4100 UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
4101 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
4102} ATOM_FAKE_EDID_PATCH_RECORD;
4103
4104typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
4105{
4106 UCHAR ucRecordType;
4107 USHORT usHSize;
4108 USHORT usVSize;
4109}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
4110
4111#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
4112#define LCD_RTS_RECORD_TYPE 2
4113#define LCD_CAP_RECORD_TYPE 3
4114#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
4115#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
4116#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6
4117#define ATOM_RECORD_END_TYPE 0xFF
4118
4119/****************************Spread Spectrum Info Table Definitions **********************/
4120
4121//ucTableFormatRevision=1
4122//ucTableContentRevision=2
4123typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
4124{
4125 USHORT usSpreadSpectrumPercentage;
4126 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
4127 UCHAR ucSS_Step;
4128 UCHAR ucSS_Delay;
4129 UCHAR ucSS_Id;
4130 UCHAR ucRecommendedRef_Div;
4131 UCHAR ucSS_Range; //it was reserved for V11
4132}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
4133
4134#define ATOM_MAX_SS_ENTRY 16
4135#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
4136#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
4137#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
4138#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
4139
4140
4141
4142#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
4143#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
4144#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
4145#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
4146#define ATOM_INTERNAL_SS_MASK 0x00000000
4147#define ATOM_EXTERNAL_SS_MASK 0x00000002
4148#define EXEC_SS_STEP_SIZE_SHIFT 2
4149#define EXEC_SS_DELAY_SHIFT 4
4150#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
4151
4152typedef struct _ATOM_SPREAD_SPECTRUM_INFO
4153{
4154 ATOM_COMMON_TABLE_HEADER sHeader;
4155 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
4156}ATOM_SPREAD_SPECTRUM_INFO;
4157
4158
4159/****************************************************************************/
4160// Structure used in AnalogTV_InfoTable (Top level)
4161/****************************************************************************/
4162//ucTVBootUpDefaultStd definiton:
4163
4164//ATOM_TV_NTSC 1
4165//ATOM_TV_NTSCJ 2
4166//ATOM_TV_PAL 3
4167//ATOM_TV_PALM 4
4168//ATOM_TV_PALCN 5
4169//ATOM_TV_PALN 6
4170//ATOM_TV_PAL60 7
4171//ATOM_TV_SECAM 8
4172
4173//ucTVSuppportedStd definition:
4174#define NTSC_SUPPORT 0x1
4175#define NTSCJ_SUPPORT 0x2
4176
4177#define PAL_SUPPORT 0x4
4178#define PALM_SUPPORT 0x8
4179#define PALCN_SUPPORT 0x10
4180#define PALN_SUPPORT 0x20
4181#define PAL60_SUPPORT 0x40
4182#define SECAM_SUPPORT 0x80
4183
4184#define MAX_SUPPORTED_TV_TIMING 2
4185
4186typedef struct _ATOM_ANALOG_TV_INFO
4187{
4188 ATOM_COMMON_TABLE_HEADER sHeader;
4189 UCHAR ucTV_SuppportedStandard;
4190 UCHAR ucTV_BootUpDefaultStandard;
4191 UCHAR ucExt_TV_ASIC_ID;
4192 UCHAR ucExt_TV_ASIC_SlaveAddr;
4193 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
4194}ATOM_ANALOG_TV_INFO;
4195
4196typedef struct _ATOM_DPCD_INFO
4197{
4198 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
4199 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
4200 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4201 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
4202}ATOM_DPCD_INFO;
4203
4204#define ATOM_DPCD_MAX_LANE_MASK 0x1F
4205
4206/**************************************************************************/
4207// VRAM usage and their defintions
4208
4209// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
4210// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
4211// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
4212// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
4213// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4214
4215// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU).
4216//#ifndef VESA_MEMORY_IN_64K_BLOCK
4217//#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
4218//#endif
4219
4220#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
4221#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
4222#define ATOM_HWICON_INFOTABLE_SIZE 32
4223#define MAX_DTD_MODE_IN_VRAM 6
4224#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
4225#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
4226//20 bytes for Encoder Type and DPCD in STD EDID area
4227#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4228#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
4229
4230#define ATOM_HWICON1_SURFACE_ADDR 0
4231#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
4232#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
4233#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
4234#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4235#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4236
4237#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4238#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4239#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4240
4241#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4242
4243#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4244#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4245#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4246
4247#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4248#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4249#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4250
4251#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4252#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4253#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4254
4255#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4256#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4257#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4258
4259#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4260#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4261#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4262
4263#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4264#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4265#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4266
4267#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4268#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4269#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4270
4271#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4272#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4273#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4274
4275#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4276#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4277#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4278
4279#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4280
4281#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
4282#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
4283
4284//The size below is in Kb!
4285#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
4286
4287#define ATOM_VRAM_RESERVE_V2_SIZE 32
4288
4289#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
4290#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
4291#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
4292#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
4293
4294/***********************************************************************************/
4295// Structure used in VRAM_UsageByFirmwareTable
4296// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
4297// at running time.
4298// note2: From RV770, the memory is more than 32bit addressable, so we will change
4299// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
4300// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
4301// (in offset to start of memory address) is KB aligned instead of byte aligend.
4302// Note3:
4303/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged
4304constant across VGA or non VGA adapter,
4305for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
4306
4307If (ulStartAddrUsedByFirmware!=0)
4308FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4309Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
4310else //Non VGA case
4311 if (FB_Size<=2Gb)
4312 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4313 else
4314 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4315
4316CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
4317
4318/***********************************************************************************/
4319#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
4320
4321typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
4322{
4323 ULONG ulStartAddrUsedByFirmware;
4324 USHORT usFirmwareUseInKb;
4325 USHORT usReserved;
4326}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
4327
4328typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
4329{
4330 ATOM_COMMON_TABLE_HEADER sHeader;
4331 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
4332}ATOM_VRAM_USAGE_BY_FIRMWARE;
4333
4334// change verion to 1.5, when allow driver to allocate the vram area for command table access.
4335typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
4336{
4337 ULONG ulStartAddrUsedByFirmware;
4338 USHORT usFirmwareUseInKb;
4339 USHORT usFBUsedByDrvInKb;
4340}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
4341
4342typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
4343{
4344 ATOM_COMMON_TABLE_HEADER sHeader;
4345 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
4346}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
4347
4348/****************************************************************************/
4349// Structure used in GPIO_Pin_LUTTable
4350/****************************************************************************/
4351typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
4352{
4353 USHORT usGpioPin_AIndex;
4354 UCHAR ucGpioPinBitShift;
4355 UCHAR ucGPIO_ID;
4356}ATOM_GPIO_PIN_ASSIGNMENT;
4357
4358//ucGPIO_ID pre-define id for multiple usage
4359// GPIO use to control PCIE_VDDC in certain SLT board
4360#define PCIE_VDDC_CONTROL_GPIO_PINID 56
4361
4362//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable
4363#define PP_AC_DC_SWITCH_GPIO_PINID 60
4364//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
4365#define VDDC_VRHOT_GPIO_PINID 61
4366//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
4367#define VDDC_PCC_GPIO_PINID 62
4368// Only used on certain SLT/PA board to allow utility to cut Efuse.
4369#define EFUSE_CUT_ENABLE_GPIO_PINID 63
4370// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO=
4371#define DRAM_SELF_REFRESH_GPIO_PINID 64
4372// Thermal interrupt output->system thermal chip GPIO pin
4373#define THERMAL_INT_OUTPUT_GPIO_PINID 65
4374
4375
4376typedef struct _ATOM_GPIO_PIN_LUT
4377{
4378 ATOM_COMMON_TABLE_HEADER sHeader;
4379 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
4380}ATOM_GPIO_PIN_LUT;
4381
4382/****************************************************************************/
4383// Structure used in ComponentVideoInfoTable
4384/****************************************************************************/
4385#define GPIO_PIN_ACTIVE_HIGH 0x1
4386#define MAX_SUPPORTED_CV_STANDARDS 5
4387
4388// definitions for ATOM_D_INFO.ucSettings
4389#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
4390#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
4391#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
4392
4393typedef struct _ATOM_GPIO_INFO
4394{
4395 USHORT usAOffset;
4396 UCHAR ucSettings;
4397 UCHAR ucReserved;
4398}ATOM_GPIO_INFO;
4399
4400// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
4401#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
4402
4403// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
4404#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
4405#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
4406
4407// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
4408//Line 3 out put 5V.
4409#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
4410#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
4411#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
4412
4413//Line 3 out put 2.2V
4414#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
4415#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
4416#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
4417
4418//Line 3 out put 0V
4419#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
4420#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
4421#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
4422
4423#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
4424
4425#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
4426
4427//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
4428#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4429#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4430
4431
4432typedef struct _ATOM_COMPONENT_VIDEO_INFO
4433{
4434 ATOM_COMMON_TABLE_HEADER sHeader;
4435 USHORT usMask_PinRegisterIndex;
4436 USHORT usEN_PinRegisterIndex;
4437 USHORT usY_PinRegisterIndex;
4438 USHORT usA_PinRegisterIndex;
4439 UCHAR ucBitShift;
4440 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4441 ATOM_DTD_FORMAT sReserved; // must be zeroed out
4442 UCHAR ucMiscInfo;
4443 UCHAR uc480i;
4444 UCHAR uc480p;
4445 UCHAR uc720p;
4446 UCHAR uc1080i;
4447 UCHAR ucLetterBoxMode;
4448 UCHAR ucReserved[3];
4449 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4450 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
4451 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
4452}ATOM_COMPONENT_VIDEO_INFO;
4453
4454//ucTableFormatRevision=2
4455//ucTableContentRevision=1
4456typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
4457{
4458 ATOM_COMMON_TABLE_HEADER sHeader;
4459 UCHAR ucMiscInfo;
4460 UCHAR uc480i;
4461 UCHAR uc480p;
4462 UCHAR uc720p;
4463 UCHAR uc1080i;
4464 UCHAR ucReserved;
4465 UCHAR ucLetterBoxMode;
4466 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4467 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
4468 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
4469}ATOM_COMPONENT_VIDEO_INFO_V21;
4470
4471#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
4472
4473/****************************************************************************/
4474// Structure used in object_InfoTable
4475/****************************************************************************/
4476typedef struct _ATOM_OBJECT_HEADER
4477{
4478 ATOM_COMMON_TABLE_HEADER sHeader;
4479 USHORT usDeviceSupport;
4480 USHORT usConnectorObjectTableOffset;
4481 USHORT usRouterObjectTableOffset;
4482 USHORT usEncoderObjectTableOffset;
4483 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
4484 USHORT usDisplayPathTableOffset;
4485}ATOM_OBJECT_HEADER;
4486
4487typedef struct _ATOM_OBJECT_HEADER_V3
4488{
4489 ATOM_COMMON_TABLE_HEADER sHeader;
4490 USHORT usDeviceSupport;
4491 USHORT usConnectorObjectTableOffset;
4492 USHORT usRouterObjectTableOffset;
4493 USHORT usEncoderObjectTableOffset;
4494 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
4495 USHORT usDisplayPathTableOffset;
4496 USHORT usMiscObjectTableOffset;
4497}ATOM_OBJECT_HEADER_V3;
4498
4499
4500typedef struct _ATOM_DISPLAY_OBJECT_PATH
4501{
4502 USHORT usDeviceTag; //supported device
4503 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4504 USHORT usConnObjectId; //Connector Object ID
4505 USHORT usGPUObjectId; //GPU ID
4506 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
4507}ATOM_DISPLAY_OBJECT_PATH;
4508
4509typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
4510{
4511 USHORT usDeviceTag; //supported device
4512 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4513 USHORT usConnObjectId; //Connector Object ID
4514 USHORT usGPUObjectId; //GPU ID
4515 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
4516}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
4517
4518typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
4519{
4520 UCHAR ucNumOfDispPath;
4521 UCHAR ucVersion;
4522 UCHAR ucPadding[2];
4523 ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
4524}ATOM_DISPLAY_OBJECT_PATH_TABLE;
4525
4526typedef struct _ATOM_OBJECT //each object has this structure
4527{
4528 USHORT usObjectID;
4529 USHORT usSrcDstTableOffset;
4530 USHORT usRecordOffset; //this pointing to a bunch of records defined below
4531 USHORT usReserved;
4532}ATOM_OBJECT;
4533
4534typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
4535{
4536 UCHAR ucNumberOfObjects;
4537 UCHAR ucPadding[3];
4538 ATOM_OBJECT asObjects[1];
4539}ATOM_OBJECT_TABLE;
4540
4541typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
4542{
4543 UCHAR ucNumberOfSrc;
4544 USHORT usSrcObjectID[1];
4545 UCHAR ucNumberOfDst;
4546 USHORT usDstObjectID[1];
4547}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
4548
4549
4550//Two definitions below are for OPM on MXM module designs
4551
4552#define EXT_HPDPIN_LUTINDEX_0 0
4553#define EXT_HPDPIN_LUTINDEX_1 1
4554#define EXT_HPDPIN_LUTINDEX_2 2
4555#define EXT_HPDPIN_LUTINDEX_3 3
4556#define EXT_HPDPIN_LUTINDEX_4 4
4557#define EXT_HPDPIN_LUTINDEX_5 5
4558#define EXT_HPDPIN_LUTINDEX_6 6
4559#define EXT_HPDPIN_LUTINDEX_7 7
4560#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
4561
4562#define EXT_AUXDDC_LUTINDEX_0 0
4563#define EXT_AUXDDC_LUTINDEX_1 1
4564#define EXT_AUXDDC_LUTINDEX_2 2
4565#define EXT_AUXDDC_LUTINDEX_3 3
4566#define EXT_AUXDDC_LUTINDEX_4 4
4567#define EXT_AUXDDC_LUTINDEX_5 5
4568#define EXT_AUXDDC_LUTINDEX_6 6
4569#define EXT_AUXDDC_LUTINDEX_7 7
4570#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
4571
4572//ucChannelMapping are defined as following
4573//for DP connector, eDP, DP to VGA/LVDS
4574//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4575//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4576//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4577//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4578typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
4579{
4580#if ATOM_BIG_ENDIAN
4581 UCHAR ucDP_Lane3_Source:2;
4582 UCHAR ucDP_Lane2_Source:2;
4583 UCHAR ucDP_Lane1_Source:2;
4584 UCHAR ucDP_Lane0_Source:2;
4585#else
4586 UCHAR ucDP_Lane0_Source:2;
4587 UCHAR ucDP_Lane1_Source:2;
4588 UCHAR ucDP_Lane2_Source:2;
4589 UCHAR ucDP_Lane3_Source:2;
4590#endif
4591}ATOM_DP_CONN_CHANNEL_MAPPING;
4592
4593//for DVI/HDMI, in dual link case, both links have to have same mapping.
4594//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4595//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4596//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4597//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4598typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
4599{
4600#if ATOM_BIG_ENDIAN
4601 UCHAR ucDVI_CLK_Source:2;
4602 UCHAR ucDVI_DATA0_Source:2;
4603 UCHAR ucDVI_DATA1_Source:2;
4604 UCHAR ucDVI_DATA2_Source:2;
4605#else
4606 UCHAR ucDVI_DATA2_Source:2;
4607 UCHAR ucDVI_DATA1_Source:2;
4608 UCHAR ucDVI_DATA0_Source:2;
4609 UCHAR ucDVI_CLK_Source:2;
4610#endif
4611}ATOM_DVI_CONN_CHANNEL_MAPPING;
4612
4613typedef struct _EXT_DISPLAY_PATH
4614{
4615 USHORT usDeviceTag; //A bit vector to show what devices are supported
4616 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4617 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
4618 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4619 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4620 USHORT usExtEncoderObjId; //external encoder object id
4621 union{
4622 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4623 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
4624 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
4625 };
4626 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4627 USHORT usCaps;
4628 USHORT usReserved;
4629}EXT_DISPLAY_PATH;
4630
4631#define NUMBER_OF_UCHAR_FOR_GUID 16
4632#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
4633
4634//usCaps
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004635#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001
4636#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002
4637#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C
4638#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip
4639#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip
4640#define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip
4641
4642
4643
Alex Deuchera02860aa2015-04-20 16:44:53 -04004644
4645typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
4646{
4647 ATOM_COMMON_TABLE_HEADER sHeader;
4648 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4649 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4650 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4651 UCHAR uc3DStereoPinId; // use for eDP panel
4652 UCHAR ucRemoteDisplayConfig;
4653 UCHAR uceDPToLVDSRxId;
4654 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value
4655 UCHAR Reserved[3]; // for potential expansion
4656}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
4657
4658//Related definitions, all records are differnt but they have a commond header
4659typedef struct _ATOM_COMMON_RECORD_HEADER
4660{
4661 UCHAR ucRecordType; //An emun to indicate the record type
4662 UCHAR ucRecordSize; //The size of the whole record in byte
4663}ATOM_COMMON_RECORD_HEADER;
4664
4665
4666#define ATOM_I2C_RECORD_TYPE 1
4667#define ATOM_HPD_INT_RECORD_TYPE 2
4668#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
4669#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
4670#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4671#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4672#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
4673#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4674#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
4675#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
4676#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
4677#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
4678#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
4679#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
4680#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
4681#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
4682#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
4683#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4684#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
4685#define ATOM_ENCODER_CAP_RECORD_TYPE 20
4686#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004687#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22
Alex Deuchera02860aa2015-04-20 16:44:53 -04004688
4689//Must be updated when new record type is added,equal to that record definition!
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004690#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE
Alex Deuchera02860aa2015-04-20 16:44:53 -04004691
4692typedef struct _ATOM_I2C_RECORD
4693{
4694 ATOM_COMMON_RECORD_HEADER sheader;
4695 ATOM_I2C_ID_CONFIG sucI2cId;
4696 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4697}ATOM_I2C_RECORD;
4698
4699typedef struct _ATOM_HPD_INT_RECORD
4700{
4701 ATOM_COMMON_RECORD_HEADER sheader;
4702 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4703 UCHAR ucPlugged_PinState;
4704}ATOM_HPD_INT_RECORD;
4705
4706
4707typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
4708{
4709 ATOM_COMMON_RECORD_HEADER sheader;
4710 UCHAR ucProtectionFlag;
4711 UCHAR ucReserved;
4712}ATOM_OUTPUT_PROTECTION_RECORD;
4713
4714typedef struct _ATOM_CONNECTOR_DEVICE_TAG
4715{
4716 ULONG ulACPIDeviceEnum; //Reserved for now
4717 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4718 USHORT usPadding;
4719}ATOM_CONNECTOR_DEVICE_TAG;
4720
4721typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
4722{
4723 ATOM_COMMON_RECORD_HEADER sheader;
4724 UCHAR ucNumberOfDevice;
4725 UCHAR ucReserved;
4726 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
4727}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
4728
4729
4730typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
4731{
4732 ATOM_COMMON_RECORD_HEADER sheader;
4733 UCHAR ucConfigGPIOID;
4734 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4735 UCHAR ucFlowinGPIPID;
4736 UCHAR ucExtInGPIPID;
4737}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
4738
4739typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
4740{
4741 ATOM_COMMON_RECORD_HEADER sheader;
4742 UCHAR ucCTL1GPIO_ID;
4743 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4744 UCHAR ucCTL2GPIO_ID;
4745 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4746 UCHAR ucCTL3GPIO_ID;
4747 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4748 UCHAR ucCTLFPGA_IN_ID;
4749 UCHAR ucPadding[3];
4750}ATOM_ENCODER_FPGA_CONTROL_RECORD;
4751
4752typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
4753{
4754 ATOM_COMMON_RECORD_HEADER sheader;
4755 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4756 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4757}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
4758
4759typedef struct _ATOM_JTAG_RECORD
4760{
4761 ATOM_COMMON_RECORD_HEADER sheader;
4762 UCHAR ucTMSGPIO_ID;
4763 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4764 UCHAR ucTCKGPIO_ID;
4765 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4766 UCHAR ucTDOGPIO_ID;
4767 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4768 UCHAR ucTDIGPIO_ID;
4769 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4770 UCHAR ucPadding[2];
4771}ATOM_JTAG_RECORD;
4772
4773
4774//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
4775typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
4776{
4777 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4778 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4779}ATOM_GPIO_PIN_CONTROL_PAIR;
4780
4781typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
4782{
4783 ATOM_COMMON_RECORD_HEADER sheader;
4784 UCHAR ucFlags; // Future expnadibility
4785 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4786 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
4787}ATOM_OBJECT_GPIO_CNTL_RECORD;
4788
4789//Definitions for GPIO pin state
4790#define GPIO_PIN_TYPE_INPUT 0x00
4791#define GPIO_PIN_TYPE_OUTPUT 0x10
4792#define GPIO_PIN_TYPE_HW_CONTROL 0x20
4793
4794//For GPIO_PIN_TYPE_OUTPUT the following is defined
4795#define GPIO_PIN_OUTPUT_STATE_MASK 0x01
4796#define GPIO_PIN_OUTPUT_STATE_SHIFT 0
4797#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
4798#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
4799
4800// Indexes to GPIO array in GLSync record
4801// GLSync record is for Frame Lock/Gen Lock feature.
4802#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
4803#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
4804#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
4805#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
4806#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
4807#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
4808#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
4809#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4810#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
4811#define ATOM_GPIO_INDEX_GLSYNC_MAX 9
4812
4813typedef struct _ATOM_ENCODER_DVO_CF_RECORD
4814{
4815 ATOM_COMMON_RECORD_HEADER sheader;
4816 ULONG ulStrengthControl; // DVOA strength control for CF
4817 UCHAR ucPadding[2];
4818}ATOM_ENCODER_DVO_CF_RECORD;
4819
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004820// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
4821#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
4822#define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not.
Alex Deuchera02860aa2015-04-20 16:44:53 -04004823#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
4824#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not.
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004825#define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board.
Alex Deuchera02860aa2015-04-20 16:44:53 -04004826
4827typedef struct _ATOM_ENCODER_CAP_RECORD
4828{
4829 ATOM_COMMON_RECORD_HEADER sheader;
4830 union {
4831 USHORT usEncoderCap;
4832 struct {
4833#if ATOM_BIG_ENDIAN
4834 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4835 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4836 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4837#else
4838 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4839 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4840 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4841#endif
4842 };
4843 };
4844}ATOM_ENCODER_CAP_RECORD;
4845
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004846// Used after SI
4847typedef struct _ATOM_ENCODER_CAP_RECORD_V2
4848{
4849 ATOM_COMMON_RECORD_HEADER sheader;
4850 union {
4851 USHORT usEncoderCap;
4852 struct {
4853#if ATOM_BIG_ENDIAN
4854 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
4855 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4856 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
4857 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4858 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4859#else
4860 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4861 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4862 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
4863 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4864 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
4865#endif
4866 };
4867 };
4868}ATOM_ENCODER_CAP_RECORD_V2;
4869
4870
Alex Deuchera02860aa2015-04-20 16:44:53 -04004871// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
4872#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
4873#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
4874
4875typedef struct _ATOM_CONNECTOR_CF_RECORD
4876{
4877 ATOM_COMMON_RECORD_HEADER sheader;
4878 USHORT usMaxPixClk;
4879 UCHAR ucFlowCntlGpioId;
4880 UCHAR ucSwapCntlGpioId;
4881 UCHAR ucConnectedDvoBundle;
4882 UCHAR ucPadding;
4883}ATOM_CONNECTOR_CF_RECORD;
4884
4885typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
4886{
4887 ATOM_COMMON_RECORD_HEADER sheader;
4888 ATOM_DTD_FORMAT asTiming;
4889}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
4890
4891typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
4892{
4893 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
4894 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4895 UCHAR ucReserved;
4896}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
4897
4898
4899typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
4900{
4901 ATOM_COMMON_RECORD_HEADER sheader;
4902 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4903 UCHAR ucMuxControlPin;
4904 UCHAR ucMuxState[2]; //for alligment purpose
4905}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
4906
4907typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
4908{
4909 ATOM_COMMON_RECORD_HEADER sheader;
4910 UCHAR ucMuxType;
4911 UCHAR ucMuxControlPin;
4912 UCHAR ucMuxState[2]; //for alligment purpose
4913}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
4914
4915// define ucMuxType
4916#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
4917#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
4918
4919typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
4920{
4921 ATOM_COMMON_RECORD_HEADER sheader;
4922 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4923}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
4924
4925typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
4926{
4927 ATOM_COMMON_RECORD_HEADER sheader;
4928 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
4929}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
4930
4931typedef struct _ATOM_OBJECT_LINK_RECORD
4932{
4933 ATOM_COMMON_RECORD_HEADER sheader;
4934 USHORT usObjectID; //could be connector, encorder or other object in object.h
4935}ATOM_OBJECT_LINK_RECORD;
4936
4937typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4938{
4939 ATOM_COMMON_RECORD_HEADER sheader;
4940 USHORT usReserved;
4941}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4942
Alex Deucher6e14e92b2015-10-15 00:43:41 -04004943
4944typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD
4945{
4946 ATOM_COMMON_RECORD_HEADER sheader;
4947 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
4948 UCHAR ucMaxTmdsClkRateIn2_5Mhz;
4949 UCHAR ucReserved;
4950} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD;
4951
4952
Alex Deuchera02860aa2015-04-20 16:44:53 -04004953typedef struct _ATOM_CONNECTOR_LAYOUT_INFO
4954{
4955 USHORT usConnectorObjectId;
4956 UCHAR ucConnectorType;
4957 UCHAR ucPosition;
4958}ATOM_CONNECTOR_LAYOUT_INFO;
4959
4960// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
4961#define CONNECTOR_TYPE_DVI_D 1
4962#define CONNECTOR_TYPE_DVI_I 2
4963#define CONNECTOR_TYPE_VGA 3
4964#define CONNECTOR_TYPE_HDMI 4
4965#define CONNECTOR_TYPE_DISPLAY_PORT 5
4966#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6
4967
4968typedef struct _ATOM_BRACKET_LAYOUT_RECORD
4969{
4970 ATOM_COMMON_RECORD_HEADER sheader;
4971 UCHAR ucLength;
4972 UCHAR ucWidth;
4973 UCHAR ucConnNum;
4974 UCHAR ucReserved;
4975 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
4976}ATOM_BRACKET_LAYOUT_RECORD;
4977
4978
4979/****************************************************************************/
4980// Structure used in XXXX
4981/****************************************************************************/
4982typedef struct _ATOM_VOLTAGE_INFO_HEADER
4983{
4984 USHORT usVDDCBaseLevel; //In number of 50mv unit
4985 USHORT usReserved; //For possible extension table offset
4986 UCHAR ucNumOfVoltageEntries;
4987 UCHAR ucBytesPerVoltageEntry;
4988 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
4989 UCHAR ucDefaultVoltageEntry;
4990 UCHAR ucVoltageControlI2cLine;
4991 UCHAR ucVoltageControlAddress;
4992 UCHAR ucVoltageControlOffset;
4993}ATOM_VOLTAGE_INFO_HEADER;
4994
4995typedef struct _ATOM_VOLTAGE_INFO
4996{
4997 ATOM_COMMON_TABLE_HEADER sHeader;
4998 ATOM_VOLTAGE_INFO_HEADER viHeader;
4999 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
5000}ATOM_VOLTAGE_INFO;
5001
5002
5003typedef struct _ATOM_VOLTAGE_FORMULA
5004{
5005 USHORT usVoltageBaseLevel; // In number of 1mv unit
5006 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
5007 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5008 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
5009 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
5010 UCHAR ucReserved;
5011 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
5012}ATOM_VOLTAGE_FORMULA;
5013
5014typedef struct _VOLTAGE_LUT_ENTRY
5015{
5016 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
5017 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
5018}VOLTAGE_LUT_ENTRY;
5019
5020typedef struct _ATOM_VOLTAGE_FORMULA_V2
5021{
5022 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5023 UCHAR ucReserved[3];
5024 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
5025}ATOM_VOLTAGE_FORMULA_V2;
5026
5027typedef struct _ATOM_VOLTAGE_CONTROL
5028{
5029 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
5030 UCHAR ucVoltageControlI2cLine;
5031 UCHAR ucVoltageControlAddress;
5032 UCHAR ucVoltageControlOffset;
5033 USHORT usGpioPin_AIndex; //GPIO_PAD register index
5034 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
5035 UCHAR ucReserved;
5036}ATOM_VOLTAGE_CONTROL;
5037
5038// Define ucVoltageControlId
5039#define VOLTAGE_CONTROLLED_BY_HW 0x00
5040#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
5041#define VOLTAGE_CONTROLLED_BY_GPIO 0x80
5042#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
5043#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
5044#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
5045#define VOLTAGE_CONTROL_ID_DS4402 0x04
5046#define VOLTAGE_CONTROL_ID_UP6266 0x05
5047#define VOLTAGE_CONTROL_ID_SCORPIO 0x06
5048#define VOLTAGE_CONTROL_ID_VT1556M 0x07
5049#define VOLTAGE_CONTROL_ID_CHL822x 0x08
5050#define VOLTAGE_CONTROL_ID_VT1586M 0x09
5051#define VOLTAGE_CONTROL_ID_UP1637 0x0A
5052#define VOLTAGE_CONTROL_ID_CHL8214 0x0B
5053#define VOLTAGE_CONTROL_ID_UP1801 0x0C
5054#define VOLTAGE_CONTROL_ID_ST6788A 0x0D
5055#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005056#define VOLTAGE_CONTROL_ID_AD527x 0x0F
5057#define VOLTAGE_CONTROL_ID_NCP81022 0x10
5058#define VOLTAGE_CONTROL_ID_LTC2635 0x11
5059#define VOLTAGE_CONTROL_ID_NCP4208 0x12
Alex Deuchera02860aa2015-04-20 16:44:53 -04005060#define VOLTAGE_CONTROL_ID_IR35xx 0x13
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005061#define VOLTAGE_CONTROL_ID_RT9403 0x14
Alex Deuchera02860aa2015-04-20 16:44:53 -04005062
5063#define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40
5064
5065typedef struct _ATOM_VOLTAGE_OBJECT
5066{
5067 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5068 UCHAR ucSize; //Size of Object
5069 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
5070 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
5071}ATOM_VOLTAGE_OBJECT;
5072
5073typedef struct _ATOM_VOLTAGE_OBJECT_V2
5074{
5075 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5076 UCHAR ucSize; //Size of Object
5077 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
5078 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
5079}ATOM_VOLTAGE_OBJECT_V2;
5080
5081typedef struct _ATOM_VOLTAGE_OBJECT_INFO
5082{
5083 ATOM_COMMON_TABLE_HEADER sHeader;
5084 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
5085}ATOM_VOLTAGE_OBJECT_INFO;
5086
5087typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
5088{
5089 ATOM_COMMON_TABLE_HEADER sHeader;
5090 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
5091}ATOM_VOLTAGE_OBJECT_INFO_V2;
5092
5093typedef struct _ATOM_LEAKID_VOLTAGE
5094{
5095 UCHAR ucLeakageId;
5096 UCHAR ucReserved;
5097 USHORT usVoltage;
5098}ATOM_LEAKID_VOLTAGE;
5099
5100typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
5101 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5102 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
5103 USHORT usSize; //Size of Object
5104}ATOM_VOLTAGE_OBJECT_HEADER_V3;
5105
5106// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode
5107#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
5108#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
5109#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
5110#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
5111#define VOLTAGE_OBJ_EVV 8
5112#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5113#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5114#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5115
5116typedef struct _VOLTAGE_LUT_ENTRY_V2
5117{
5118 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
5119 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
5120}VOLTAGE_LUT_ENTRY_V2;
5121
5122typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
5123{
5124 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
5125 USHORT usVoltageId;
5126 USHORT usLeakageId; // The corresponding Voltage Value, in mV
5127}LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
5128
5129
5130typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
5131{
5132 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
5133 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
5134 UCHAR ucVoltageControlI2cLine;
5135 UCHAR ucVoltageControlAddress;
5136 UCHAR ucVoltageControlOffset;
5137 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5138 UCHAR ulReserved[3];
5139 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
5140}ATOM_I2C_VOLTAGE_OBJECT_V3;
5141
5142// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
5143#define VOLTAGE_DATA_ONE_BYTE 0
5144#define VOLTAGE_DATA_TWO_BYTE 1
5145
5146typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
5147{
5148 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
5149 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
5150 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
5151 UCHAR ucPhaseDelay; // phase delay in unit of micro second
5152 UCHAR ucReserved;
5153 ULONG ulGpioMaskVal; // GPIO Mask value
5154 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
5155}ATOM_GPIO_VOLTAGE_OBJECT_V3;
5156
5157typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5158{
5159 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12
5160 UCHAR ucLeakageCntlId; // default is 0
5161 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
5162 UCHAR ucReserved[2];
5163 ULONG ulMaxVoltageLevel;
5164 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
5165}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
5166
5167
5168typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3
5169{
5170 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
5171// 14:7 � PSI0_VID
5172// 6 � PSI0_EN
5173// 5 � PSI1
5174// 4:2 � load line slope trim.
5175// 1:0 � offset trim,
5176 USHORT usLoadLine_PSI;
5177// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
5178 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
5179 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
5180 ULONG ulReserved;
5181}ATOM_SVID2_VOLTAGE_OBJECT_V3;
5182
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005183
5184
5185typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3
5186{
5187 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
5188 UCHAR ucMergedVType; // VDDC/VDCCI/....
5189 UCHAR ucReserved[3];
5190}ATOM_MERGED_VOLTAGE_OBJECT_V3;
5191
5192
5193typedef struct _ATOM_EVV_DPM_INFO
5194{
5195 ULONG ulDPMSclk; // DPM state SCLK
5196 USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv
5197 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable
5198 UCHAR ucDPMState; // DPMState0~7
5199} ATOM_EVV_DPM_INFO;
5200
5201// ucVoltageMode = VOLTAGE_OBJ_EVV
5202typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3
5203{
5204 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
5205 ATOM_EVV_DPM_INFO asEvvDpmList[8];
5206}ATOM_EVV_VOLTAGE_OBJECT_V3;
5207
5208
Alex Deuchera02860aa2015-04-20 16:44:53 -04005209typedef union _ATOM_VOLTAGE_OBJECT_V3{
5210 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
5211 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
5212 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
5213 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005214 ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj;
Alex Deuchera02860aa2015-04-20 16:44:53 -04005215}ATOM_VOLTAGE_OBJECT_V3;
5216
5217typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1
5218{
5219 ATOM_COMMON_TABLE_HEADER sHeader;
5220 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control
5221}ATOM_VOLTAGE_OBJECT_INFO_V3_1;
5222
5223
5224typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
5225{
5226 UCHAR ucProfileId;
5227 UCHAR ucReserved;
5228 USHORT usSize;
5229 USHORT usEfuseSpareStartAddr;
5230 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
5231 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
5232}ATOM_ASIC_PROFILE_VOLTAGE;
5233
5234//ucProfileId
5235#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
5236#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
5237#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
5238
5239typedef struct _ATOM_ASIC_PROFILING_INFO
5240{
5241 ATOM_COMMON_TABLE_HEADER asHeader;
5242 ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
5243}ATOM_ASIC_PROFILING_INFO;
5244
5245typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1
5246{
5247 ATOM_COMMON_TABLE_HEADER asHeader;
5248 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
5249 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
5250
5251 UCHAR ucElbVDDC_Num;
5252 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
5253 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5254
5255 UCHAR ucElbVDDCI_Num;
5256 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
5257 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5258}ATOM_ASIC_PROFILING_INFO_V2_1;
5259
5260
5261//Here is parameter to convert Efuse value to Measure value
5262//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5263typedef struct _EFUSE_LOGISTIC_FUNC_PARAM
5264{
5265 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
5266 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5267 UCHAR ucEfuseLength; // Efuse bits length,
5268 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5269 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
5270}EFUSE_LOGISTIC_FUNC_PARAM;
5271
5272//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5273typedef struct _EFUSE_LINEAR_FUNC_PARAM
5274{
5275 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
5276 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5277 UCHAR ucEfuseLength; // Efuse bits length,
5278 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5279 ULONG ulEfuseMin; // Min
5280}EFUSE_LINEAR_FUNC_PARAM;
5281
5282
5283typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1
5284{
5285 ATOM_COMMON_TABLE_HEADER asHeader;
5286 ULONG ulEvvDerateTdp;
5287 ULONG ulEvvDerateTdc;
5288 ULONG ulBoardCoreTemp;
5289 ULONG ulMaxVddc;
5290 ULONG ulMinVddc;
5291 ULONG ulLoadLineSlop;
5292 ULONG ulLeakageTemp;
5293 ULONG ulLeakageVoltage;
5294 EFUSE_LINEAR_FUNC_PARAM sCACm;
5295 EFUSE_LINEAR_FUNC_PARAM sCACb;
5296 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5297 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5298 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5299 USHORT usLkgEuseIndex;
5300 UCHAR ucLkgEfuseBitLSB;
5301 UCHAR ucLkgEfuseLength;
5302 ULONG ulLkgEncodeLn_MaxDivMin;
5303 ULONG ulLkgEncodeMax;
5304 ULONG ulLkgEncodeMin;
5305 ULONG ulEfuseLogisticAlpha;
5306 USHORT usPowerDpm0;
5307 USHORT usCurrentDpm0;
5308 USHORT usPowerDpm1;
5309 USHORT usCurrentDpm1;
5310 USHORT usPowerDpm2;
5311 USHORT usCurrentDpm2;
5312 USHORT usPowerDpm3;
5313 USHORT usCurrentDpm3;
5314 USHORT usPowerDpm4;
5315 USHORT usCurrentDpm4;
5316 USHORT usPowerDpm5;
5317 USHORT usCurrentDpm5;
5318 USHORT usPowerDpm6;
5319 USHORT usCurrentDpm6;
5320 USHORT usPowerDpm7;
5321 USHORT usCurrentDpm7;
5322}ATOM_ASIC_PROFILING_INFO_V3_1;
5323
5324
5325typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2
5326{
5327 ATOM_COMMON_TABLE_HEADER asHeader;
5328 ULONG ulEvvLkgFactor;
5329 ULONG ulBoardCoreTemp;
5330 ULONG ulMaxVddc;
5331 ULONG ulMinVddc;
5332 ULONG ulLoadLineSlop;
5333 ULONG ulLeakageTemp;
5334 ULONG ulLeakageVoltage;
5335 EFUSE_LINEAR_FUNC_PARAM sCACm;
5336 EFUSE_LINEAR_FUNC_PARAM sCACb;
5337 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5338 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5339 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5340 USHORT usLkgEuseIndex;
5341 UCHAR ucLkgEfuseBitLSB;
5342 UCHAR ucLkgEfuseLength;
5343 ULONG ulLkgEncodeLn_MaxDivMin;
5344 ULONG ulLkgEncodeMax;
5345 ULONG ulLkgEncodeMin;
5346 ULONG ulEfuseLogisticAlpha;
5347 USHORT usPowerDpm0;
5348 USHORT usPowerDpm1;
5349 USHORT usPowerDpm2;
5350 USHORT usPowerDpm3;
5351 USHORT usPowerDpm4;
5352 USHORT usPowerDpm5;
5353 USHORT usPowerDpm6;
5354 USHORT usPowerDpm7;
5355 ULONG ulTdpDerateDPM0;
5356 ULONG ulTdpDerateDPM1;
5357 ULONG ulTdpDerateDPM2;
5358 ULONG ulTdpDerateDPM3;
5359 ULONG ulTdpDerateDPM4;
5360 ULONG ulTdpDerateDPM5;
5361 ULONG ulTdpDerateDPM6;
5362 ULONG ulTdpDerateDPM7;
5363}ATOM_ASIC_PROFILING_INFO_V3_2;
5364
5365
5366// for Tonga/Fiji speed EVV algorithm
5367typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3
5368{
5369 ATOM_COMMON_TABLE_HEADER asHeader;
5370 ULONG ulEvvLkgFactor;
5371 ULONG ulBoardCoreTemp;
5372 ULONG ulMaxVddc;
5373 ULONG ulMinVddc;
5374 ULONG ulLoadLineSlop;
5375 ULONG ulLeakageTemp;
5376 ULONG ulLeakageVoltage;
5377 EFUSE_LINEAR_FUNC_PARAM sCACm;
5378 EFUSE_LINEAR_FUNC_PARAM sCACb;
5379 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5380 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5381 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5382 USHORT usLkgEuseIndex;
5383 UCHAR ucLkgEfuseBitLSB;
5384 UCHAR ucLkgEfuseLength;
5385 ULONG ulLkgEncodeLn_MaxDivMin;
5386 ULONG ulLkgEncodeMax;
5387 ULONG ulLkgEncodeMin;
5388 ULONG ulEfuseLogisticAlpha;
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005389
5390 union{
Alex Deuchera02860aa2015-04-20 16:44:53 -04005391 USHORT usPowerDpm0;
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005392 USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive
5393 };
Alex Deuchera02860aa2015-04-20 16:44:53 -04005394 USHORT usPowerDpm1;
5395 USHORT usPowerDpm2;
5396 USHORT usPowerDpm3;
5397 USHORT usPowerDpm4;
5398 USHORT usPowerDpm5;
5399 USHORT usPowerDpm6;
5400 USHORT usPowerDpm7;
5401 ULONG ulTdpDerateDPM0;
5402 ULONG ulTdpDerateDPM1;
5403 ULONG ulTdpDerateDPM2;
5404 ULONG ulTdpDerateDPM3;
5405 ULONG ulTdpDerateDPM4;
5406 ULONG ulTdpDerateDPM5;
5407 ULONG ulTdpDerateDPM6;
5408 ULONG ulTdpDerateDPM7;
5409 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5410 ULONG ulRoAlpha;
5411 ULONG ulRoBeta;
5412 ULONG ulRoGamma;
5413 ULONG ulRoEpsilon;
5414 ULONG ulATermRo;
5415 ULONG ulBTermRo;
5416 ULONG ulCTermRo;
5417 ULONG ulSclkMargin;
5418 ULONG ulFmaxPercent;
5419 ULONG ulCRPercent;
5420 ULONG ulSFmaxPercent;
5421 ULONG ulSCRPercent;
5422 ULONG ulSDCMargine;
5423}ATOM_ASIC_PROFILING_INFO_V3_3;
5424
Eric Huang770911a2015-11-09 17:34:31 -05005425// for Fiji speed EVV algorithm
5426typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4
5427{
5428 ATOM_COMMON_TABLE_HEADER asHeader;
5429 ULONG ulEvvLkgFactor;
5430 ULONG ulBoardCoreTemp;
5431 ULONG ulMaxVddc;
5432 ULONG ulMinVddc;
5433 ULONG ulLoadLineSlop;
5434 ULONG ulLeakageTemp;
5435 ULONG ulLeakageVoltage;
5436 EFUSE_LINEAR_FUNC_PARAM sCACm;
5437 EFUSE_LINEAR_FUNC_PARAM sCACb;
5438 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5439 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5440 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5441 USHORT usLkgEuseIndex;
5442 UCHAR ucLkgEfuseBitLSB;
5443 UCHAR ucLkgEfuseLength;
5444 ULONG ulLkgEncodeLn_MaxDivMin;
5445 ULONG ulLkgEncodeMax;
5446 ULONG ulLkgEncodeMin;
5447 ULONG ulEfuseLogisticAlpha;
5448 USHORT usPowerDpm0;
5449 USHORT usPowerDpm1;
5450 USHORT usPowerDpm2;
5451 USHORT usPowerDpm3;
5452 USHORT usPowerDpm4;
5453 USHORT usPowerDpm5;
5454 USHORT usPowerDpm6;
5455 USHORT usPowerDpm7;
5456 ULONG ulTdpDerateDPM0;
5457 ULONG ulTdpDerateDPM1;
5458 ULONG ulTdpDerateDPM2;
5459 ULONG ulTdpDerateDPM3;
5460 ULONG ulTdpDerateDPM4;
5461 ULONG ulTdpDerateDPM5;
5462 ULONG ulTdpDerateDPM6;
5463 ULONG ulTdpDerateDPM7;
5464 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5465 ULONG ulEvvDefaultVddc;
5466 ULONG ulEvvNoCalcVddc;
5467 USHORT usParamNegFlag;
5468 USHORT usSpeed_Model;
5469 ULONG ulSM_A0;
5470 ULONG ulSM_A1;
5471 ULONG ulSM_A2;
5472 ULONG ulSM_A3;
5473 ULONG ulSM_A4;
5474 ULONG ulSM_A5;
5475 ULONG ulSM_A6;
5476 ULONG ulSM_A7;
5477 UCHAR ucSM_A0_sign;
5478 UCHAR ucSM_A1_sign;
5479 UCHAR ucSM_A2_sign;
5480 UCHAR ucSM_A3_sign;
5481 UCHAR ucSM_A4_sign;
5482 UCHAR ucSM_A5_sign;
5483 UCHAR ucSM_A6_sign;
5484 UCHAR ucSM_A7_sign;
5485 ULONG ulMargin_RO_a;
5486 ULONG ulMargin_RO_b;
5487 ULONG ulMargin_RO_c;
5488 ULONG ulMargin_fixed;
5489 ULONG ulMargin_Fmax_mean;
5490 ULONG ulMargin_plat_mean;
5491 ULONG ulMargin_Fmax_sigma;
5492 ULONG ulMargin_plat_sigma;
5493 ULONG ulMargin_DC_sigma;
5494 ULONG ulReserved[8]; // Reserved for future ASIC
5495}ATOM_ASIC_PROFILING_INFO_V3_4;
5496
Flora Cui2cc0c0b2016-03-14 18:33:29 -04005497// for Polaris10/Polaris11 speed EVV algorithm
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005498typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5
5499{
5500 ATOM_COMMON_TABLE_HEADER asHeader;
5501 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv
5502 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv
5503 USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address )
5504 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD
5505 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length
5506 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )
5507 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5508 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5509 EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1.
5510 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>
5511 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>
5512 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>
5513 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>
5514 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>
5515 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>
5516 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>
5517 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>
5518 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>
5519 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>
5520 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>
5521 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
5522 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
5523 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
5524 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
5525 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
5526 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
5527 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>
5528 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>
5529 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
5530 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
5531 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"
5532 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
5533 ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/>
5534 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>
5535 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>
5536 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>
5537 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>
5538 ULONG ulReserved[12];
5539}ATOM_ASIC_PROFILING_INFO_V3_5;
5540
Rex Zhuc11cb702016-06-08 19:17:31 +08005541/* for Polars10/11 AVFS parameters */
5542typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6
5543{
5544 ATOM_COMMON_TABLE_HEADER asHeader;
5545 ULONG ulMaxVddc;
5546 ULONG ulMinVddc;
5547 USHORT usLkgEuseIndex;
5548 UCHAR ucLkgEfuseBitLSB;
5549 UCHAR ucLkgEfuseLength;
5550 ULONG ulLkgEncodeLn_MaxDivMin;
5551 ULONG ulLkgEncodeMax;
5552 ULONG ulLkgEncodeMin;
5553 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5554 ULONG ulEvvDefaultVddc;
5555 ULONG ulEvvNoCalcVddc;
5556 ULONG ulSpeed_Model;
5557 ULONG ulSM_A0;
5558 ULONG ulSM_A1;
5559 ULONG ulSM_A2;
5560 ULONG ulSM_A3;
5561 ULONG ulSM_A4;
5562 ULONG ulSM_A5;
5563 ULONG ulSM_A6;
5564 ULONG ulSM_A7;
5565 UCHAR ucSM_A0_sign;
5566 UCHAR ucSM_A1_sign;
5567 UCHAR ucSM_A2_sign;
5568 UCHAR ucSM_A3_sign;
5569 UCHAR ucSM_A4_sign;
5570 UCHAR ucSM_A5_sign;
5571 UCHAR ucSM_A6_sign;
5572 UCHAR ucSM_A7_sign;
5573 ULONG ulMargin_RO_a;
5574 ULONG ulMargin_RO_b;
5575 ULONG ulMargin_RO_c;
5576 ULONG ulMargin_fixed;
5577 ULONG ulMargin_Fmax_mean;
5578 ULONG ulMargin_plat_mean;
5579 ULONG ulMargin_Fmax_sigma;
5580 ULONG ulMargin_plat_sigma;
5581 ULONG ulMargin_DC_sigma;
5582 ULONG ulLoadLineSlop;
5583 ULONG ulaTDClimitPerDPM[8];
5584 ULONG ulaNoCalcVddcPerDPM[8];
5585 ULONG ulAVFS_meanNsigma_Acontant0;
5586 ULONG ulAVFS_meanNsigma_Acontant1;
5587 ULONG ulAVFS_meanNsigma_Acontant2;
5588 USHORT usAVFS_meanNsigma_DC_tol_sigma;
5589 USHORT usAVFS_meanNsigma_Platform_mean;
5590 USHORT usAVFS_meanNsigma_Platform_sigma;
5591 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
5592 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
5593 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
5594 ULONG ulGB_VDROOP_TABLE_CKSON_a0;
5595 ULONG ulGB_VDROOP_TABLE_CKSON_a1;
5596 ULONG ulGB_VDROOP_TABLE_CKSON_a2;
5597 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
5598 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;
5599 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
5600 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
5601 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;
5602 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
5603 USHORT usMaxVoltage_0_25mv;
5604 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;
5605 UCHAR ucEnableGB_VDROOP_TABLE_CKSON;
5606 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;
5607 UCHAR ucEnableGB_FUSE_TABLE_CKSON;
5608 USHORT usPSM_Age_ComFactor;
5609 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;
5610 UCHAR ucReserved;
5611}ATOM_ASIC_PROFILING_INFO_V3_6;
5612
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005613
5614typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
5615 ULONG ulMaxSclkFreq;
5616 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5617 UCHAR ucPostdiv; // divide by 2^n
5618 USHORT ucFcw_pcc;
5619 USHORT ucFcw_trans_upper;
5620 USHORT ucRcw_trans_lower;
5621}ATOM_SCLK_FCW_RANGE_ENTRY_V1;
5622
5623
Flora Cui2cc0c0b2016-03-14 18:33:29 -04005624// SMU_InfoTable for Polaris10/Polaris11
Alex Deucher6e14e92b2015-10-15 00:43:41 -04005625typedef struct _ATOM_SMU_INFO_V2_1
5626{
5627 ATOM_COMMON_TABLE_HEADER asHeader;
5628 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
5629 UCHAR ucReserved[3];
5630 ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8];
5631}ATOM_SMU_INFO_V2_1;
5632
5633
5634// GFX_InfoTable for Polaris10/Polaris11
5635typedef struct _ATOM_GFX_INFO_V2_1
5636{
5637 ATOM_COMMON_TABLE_HEADER asHeader;
5638 UCHAR GfxIpMinVer;
5639 UCHAR GfxIpMajVer;
5640 UCHAR max_shader_engines;
5641 UCHAR max_tile_pipes;
5642 UCHAR max_cu_per_sh;
5643 UCHAR max_sh_per_se;
5644 UCHAR max_backends_per_se;
5645 UCHAR max_texture_channel_caches;
5646}ATOM_GFX_INFO_V2_1;
5647
5648
Alex Deuchera02860aa2015-04-20 16:44:53 -04005649typedef struct _ATOM_POWER_SOURCE_OBJECT
5650{
5651 UCHAR ucPwrSrcId; // Power source
5652 UCHAR ucPwrSensorType; // GPIO, I2C or none
5653 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
5654 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
5655 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
5656 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
5657 UCHAR ucPwrSensActiveState; // high active or low active
5658 UCHAR ucReserve[3]; // reserve
5659 USHORT usSensPwr; // in unit of watt
5660}ATOM_POWER_SOURCE_OBJECT;
5661
5662typedef struct _ATOM_POWER_SOURCE_INFO
5663{
5664 ATOM_COMMON_TABLE_HEADER asHeader;
5665 UCHAR asPwrbehave[16];
5666 ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
5667}ATOM_POWER_SOURCE_INFO;
5668
5669
5670//Define ucPwrSrcId
5671#define POWERSOURCE_PCIE_ID1 0x00
5672#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
5673#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
5674#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
5675#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
5676
5677//define ucPwrSensorId
5678#define POWER_SENSOR_ALWAYS 0x00
5679#define POWER_SENSOR_GPIO 0x01
5680#define POWER_SENSOR_I2C 0x02
5681
5682typedef struct _ATOM_CLK_VOLT_CAPABILITY
5683{
5684 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
5685 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5686}ATOM_CLK_VOLT_CAPABILITY;
5687
5688
5689typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2
5690{
5691 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv,
5692 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5693}ATOM_CLK_VOLT_CAPABILITY_V2;
5694
5695typedef struct _ATOM_AVAILABLE_SCLK_LIST
5696{
5697 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5698 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
5699 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
5700}ATOM_AVAILABLE_SCLK_LIST;
5701
5702// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
5703#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
5704
5705// this IntegrateSystemInfoTable is used for Liano/Ontario APU
5706typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
5707{
5708 ATOM_COMMON_TABLE_HEADER sHeader;
5709 ULONG ulBootUpEngineClock;
5710 ULONG ulDentistVCOFreq;
5711 ULONG ulBootUpUMAClock;
5712 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5713 ULONG ulBootUpReqDisplayVector;
5714 ULONG ulOtherDisplayMisc;
5715 ULONG ulGPUCapInfo;
5716 ULONG ulSB_MMIO_Base_Addr;
5717 USHORT usRequestedPWMFreqInHz;
5718 UCHAR ucHtcTmpLmt;
5719 UCHAR ucHtcHystLmt;
5720 ULONG ulMinEngineClock;
5721 ULONG ulSystemConfig;
5722 ULONG ulCPUCapInfo;
5723 USHORT usNBP0Voltage;
5724 USHORT usNBP1Voltage;
5725 USHORT usBootUpNBVoltage;
5726 USHORT usExtDispConnInfoOffset;
5727 USHORT usPanelRefreshRateRange;
5728 UCHAR ucMemoryType;
5729 UCHAR ucUMAChannelNumber;
5730 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
5731 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
5732 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
5733 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
5734 ULONG ulGMCRestoreResetTime;
5735 ULONG ulMinimumNClk;
5736 ULONG ulIdleNClk;
5737 ULONG ulDDR_DLL_PowerUpTime;
5738 ULONG ulDDR_PLL_PowerUpTime;
5739 USHORT usPCIEClkSSPercentage;
5740 USHORT usPCIEClkSSType;
5741 USHORT usLvdsSSPercentage;
5742 USHORT usLvdsSSpreadRateIn10Hz;
5743 USHORT usHDMISSPercentage;
5744 USHORT usHDMISSpreadRateIn10Hz;
5745 USHORT usDVISSPercentage;
5746 USHORT usDVISSpreadRateIn10Hz;
5747 ULONG SclkDpmBoostMargin;
5748 ULONG SclkDpmThrottleMargin;
5749 USHORT SclkDpmTdpLimitPG;
5750 USHORT SclkDpmTdpLimitBoost;
5751 ULONG ulBoostEngineCLock;
5752 UCHAR ulBoostVid_2bit;
5753 UCHAR EnableBoost;
5754 USHORT GnbTdpLimit;
5755 USHORT usMaxLVDSPclkFreqInSingleLink;
5756 UCHAR ucLvdsMisc;
5757 UCHAR ucLVDSReserved;
5758 ULONG ulReserved3[15];
5759 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5760}ATOM_INTEGRATED_SYSTEM_INFO_V6;
5761
5762// ulGPUCapInfo
5763#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
5764#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08
5765
5766//ucLVDSMisc:
5767#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01
5768#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02
5769#define SYS_INFO_LVDSMISC__888_BPC 0x04
5770#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08
5771#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10
5772// new since Trinity
5773#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20
5774
5775// not used any more
5776#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04
5777#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08
5778
5779/**********************************************************************************************************************
5780 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
5781ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
5782ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5783ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5784sDISPCLK_Voltage: Report Display clock voltage requirement.
5785
5786ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
5787 ATOM_DEVICE_CRT1_SUPPORT 0x0001
5788 ATOM_DEVICE_CRT2_SUPPORT 0x0010
5789 ATOM_DEVICE_DFP1_SUPPORT 0x0008
5790 ATOM_DEVICE_DFP6_SUPPORT 0x0040
5791 ATOM_DEVICE_DFP2_SUPPORT 0x0080
5792 ATOM_DEVICE_DFP3_SUPPORT 0x0200
5793 ATOM_DEVICE_DFP4_SUPPORT 0x0400
5794 ATOM_DEVICE_DFP5_SUPPORT 0x0800
5795 ATOM_DEVICE_LCD1_SUPPORT 0x0002
5796ulOtherDisplayMisc: Other display related flags, not defined yet.
5797ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5798 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5799 bit[3]=0: Enable HW AUX mode detection logic
5800 =1: Disable HW AUX mode dettion logic
5801ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
5802
5803usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5804 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
5805
5806 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5807 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5808 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5809 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5810 and enabling VariBri under the driver environment from PP table is optional.
5811
5812 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5813 that BL control from GPU is expected.
5814 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5815 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
5816 it's per platform
5817 and enabling VariBri under the driver environment from PP table is optional.
5818
5819ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
5820 Threshold on value to enter HTC_active state.
5821ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
5822 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
5823ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
5824ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
5825 =1: PCIE Power Gating Enabled
5826 Bit[1]=0: DDR-DLL shut-down feature disabled.
5827 1: DDR-DLL shut-down feature enabled.
5828 Bit[2]=0: DDR-PLL Power down feature disabled.
5829 1: DDR-PLL Power down feature enabled.
5830ulCPUCapInfo: TBD
5831usNBP0Voltage: VID for voltage on NB P0 State
5832usNBP1Voltage: VID for voltage on NB P1 State
5833usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
5834usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
5835usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5836 to indicate a range.
5837 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
5838 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
5839 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
5840 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
5841ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5842ucUMAChannelNumber: System memory channel numbers.
5843ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
5844ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
5845ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
5846sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
5847ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5848ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5849ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5850ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
5851ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
5852usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
5853usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
5854usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
5855usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5856usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
5857usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5858usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
5859usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5860usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
5861ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
5862 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
5863 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5864 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
5865 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
5866**********************************************************************************************************************/
5867
5868// this Table is used for Liano/Ontario APU
5869typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
5870{
5871 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;
5872 ULONG ulPowerplayTable[128];
5873}ATOM_FUSION_SYSTEM_INFO_V1;
5874
5875
5876typedef struct _ATOM_TDP_CONFIG_BITS
5877{
5878#if ATOM_BIG_ENDIAN
5879 ULONG uReserved:2;
5880 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5881 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5882 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5883#else
5884 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5885 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5886 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5887 ULONG uReserved:2;
5888#endif
5889}ATOM_TDP_CONFIG_BITS;
5890
5891typedef union _ATOM_TDP_CONFIG
5892{
5893 ATOM_TDP_CONFIG_BITS TDP_config;
5894 ULONG TDP_config_all;
5895}ATOM_TDP_CONFIG;
5896
5897/**********************************************************************************************************************
5898 ATOM_FUSION_SYSTEM_INFO_V1 Description
5899sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
5900ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
5901**********************************************************************************************************************/
5902
5903// this IntegrateSystemInfoTable is used for Trinity APU
5904typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
5905{
5906 ATOM_COMMON_TABLE_HEADER sHeader;
5907 ULONG ulBootUpEngineClock;
5908 ULONG ulDentistVCOFreq;
5909 ULONG ulBootUpUMAClock;
5910 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5911 ULONG ulBootUpReqDisplayVector;
5912 ULONG ulOtherDisplayMisc;
5913 ULONG ulGPUCapInfo;
5914 ULONG ulSB_MMIO_Base_Addr;
5915 USHORT usRequestedPWMFreqInHz;
5916 UCHAR ucHtcTmpLmt;
5917 UCHAR ucHtcHystLmt;
5918 ULONG ulMinEngineClock;
5919 ULONG ulSystemConfig;
5920 ULONG ulCPUCapInfo;
5921 USHORT usNBP0Voltage;
5922 USHORT usNBP1Voltage;
5923 USHORT usBootUpNBVoltage;
5924 USHORT usExtDispConnInfoOffset;
5925 USHORT usPanelRefreshRateRange;
5926 UCHAR ucMemoryType;
5927 UCHAR ucUMAChannelNumber;
5928 UCHAR strVBIOSMsg[40];
5929 ATOM_TDP_CONFIG asTdpConfig;
5930 ULONG ulReserved[19];
5931 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
5932 ULONG ulGMCRestoreResetTime;
5933 ULONG ulMinimumNClk;
5934 ULONG ulIdleNClk;
5935 ULONG ulDDR_DLL_PowerUpTime;
5936 ULONG ulDDR_PLL_PowerUpTime;
5937 USHORT usPCIEClkSSPercentage;
5938 USHORT usPCIEClkSSType;
5939 USHORT usLvdsSSPercentage;
5940 USHORT usLvdsSSpreadRateIn10Hz;
5941 USHORT usHDMISSPercentage;
5942 USHORT usHDMISSpreadRateIn10Hz;
5943 USHORT usDVISSPercentage;
5944 USHORT usDVISSpreadRateIn10Hz;
5945 ULONG SclkDpmBoostMargin;
5946 ULONG SclkDpmThrottleMargin;
5947 USHORT SclkDpmTdpLimitPG;
5948 USHORT SclkDpmTdpLimitBoost;
5949 ULONG ulBoostEngineCLock;
5950 UCHAR ulBoostVid_2bit;
5951 UCHAR EnableBoost;
5952 USHORT GnbTdpLimit;
5953 USHORT usMaxLVDSPclkFreqInSingleLink;
5954 UCHAR ucLvdsMisc;
5955 UCHAR ucTravisLVDSVolAdjust;
5956 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5957 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5958 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5959 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5960 UCHAR ucLVDSOffToOnDelay_in4Ms;
5961 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5962 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5963 UCHAR ucMinAllowedBL_Level;
5964 ULONG ulLCDBitDepthControlVal;
5965 ULONG ulNbpStateMemclkFreq[4];
5966 USHORT usNBP2Voltage;
5967 USHORT usNBP3Voltage;
5968 ULONG ulNbpStateNClkFreq[4];
5969 UCHAR ucNBDPMEnable;
5970 UCHAR ucReserved[3];
5971 UCHAR ucDPMState0VclkFid;
5972 UCHAR ucDPMState0DclkFid;
5973 UCHAR ucDPMState1VclkFid;
5974 UCHAR ucDPMState1DclkFid;
5975 UCHAR ucDPMState2VclkFid;
5976 UCHAR ucDPMState2DclkFid;
5977 UCHAR ucDPMState3VclkFid;
5978 UCHAR ucDPMState3DclkFid;
5979 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5980}ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
5981
5982// ulOtherDisplayMisc
5983#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01
5984#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02
5985#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04
5986#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08
5987
5988// ulGPUCapInfo
5989#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
5990#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02
5991#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08
5992#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10
5993//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
5994#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000
5995
5996//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML
5997#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000
5998
5999/**********************************************************************************************************************
6000 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
6001ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
6002ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6003ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6004sDISPCLK_Voltage: Report Display clock voltage requirement.
6005
6006ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
6007 ATOM_DEVICE_CRT1_SUPPORT 0x0001
6008 ATOM_DEVICE_DFP1_SUPPORT 0x0008
6009 ATOM_DEVICE_DFP6_SUPPORT 0x0040
6010 ATOM_DEVICE_DFP2_SUPPORT 0x0080
6011 ATOM_DEVICE_DFP3_SUPPORT 0x0200
6012 ATOM_DEVICE_DFP4_SUPPORT 0x0400
6013 ATOM_DEVICE_DFP5_SUPPORT 0x0800
6014 ATOM_DEVICE_LCD1_SUPPORT 0x0002
6015ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6016 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6017 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6018 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6019 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6020 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6021 bit[3]=0: VBIOS fast boot is disable
6022 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
6023ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
6024 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
6025 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
6026 =1: DP mode use single PLL mode
6027 bit[3]=0: Enable AUX HW mode detection logic
6028 =1: Disable AUX HW mode detection logic
6029
6030ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
6031
6032usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6033 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
6034
6035 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
6036 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
6037 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
6038 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6039 and enabling VariBri under the driver environment from PP table is optional.
6040
6041 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
6042 that BL control from GPU is expected.
6043 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
6044 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
6045 it's per platform
6046 and enabling VariBri under the driver environment from PP table is optional.
6047
6048ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
6049 Threshold on value to enter HTC_active state.
6050ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
6051 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
6052ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
6053ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
6054 =1: PCIE Power Gating Enabled
6055 Bit[1]=0: DDR-DLL shut-down feature disabled.
6056 1: DDR-DLL shut-down feature enabled.
6057 Bit[2]=0: DDR-PLL Power down feature disabled.
6058 1: DDR-PLL Power down feature enabled.
6059ulCPUCapInfo: TBD
6060usNBP0Voltage: VID for voltage on NB P0 State
6061usNBP1Voltage: VID for voltage on NB P1 State
6062usNBP2Voltage: VID for voltage on NB P2 State
6063usNBP3Voltage: VID for voltage on NB P3 State
6064usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
6065usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
6066usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
6067 to indicate a range.
6068 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
6069 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
6070 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
6071 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
6072ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
6073ucUMAChannelNumber: System memory channel numbers.
6074ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
6075ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
6076ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
6077sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
6078ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
6079ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
6080ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6081ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
6082ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
6083usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
6084usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
6085usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
6086usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6087usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6088usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6089usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6090usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6091usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
6092ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
6093 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
6094 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6095 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
6096 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
6097 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
6098ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
6099 value to program Travis register LVDS_CTRL_4
6100ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
6101 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6102 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6103ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
6104 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6105 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6106
6107ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
6108 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6109 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6110
6111ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
6112 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6113 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6114
6115ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
6116 =0 means to use VBIOS default delay which is 125 ( 500ms ).
6117 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6118
6119ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
6120 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
6121 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6122 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6123
6124ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
6125 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
6126 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6127 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6128
6129ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
6130
6131ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.
6132
6133**********************************************************************************************************************/
6134
6135// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU
6136typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8
6137{
6138 ATOM_COMMON_TABLE_HEADER sHeader;
6139 ULONG ulBootUpEngineClock;
6140 ULONG ulDentistVCOFreq;
6141 ULONG ulBootUpUMAClock;
6142 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
6143 ULONG ulBootUpReqDisplayVector;
6144 ULONG ulVBIOSMisc;
6145 ULONG ulGPUCapInfo;
6146 ULONG ulDISP_CLK2Freq;
6147 USHORT usRequestedPWMFreqInHz;
6148 UCHAR ucHtcTmpLmt;
6149 UCHAR ucHtcHystLmt;
6150 ULONG ulReserved2;
6151 ULONG ulSystemConfig;
6152 ULONG ulCPUCapInfo;
6153 ULONG ulReserved3;
6154 USHORT usGPUReservedSysMemSize;
6155 USHORT usExtDispConnInfoOffset;
6156 USHORT usPanelRefreshRateRange;
6157 UCHAR ucMemoryType;
6158 UCHAR ucUMAChannelNumber;
6159 UCHAR strVBIOSMsg[40];
6160 ATOM_TDP_CONFIG asTdpConfig;
6161 ULONG ulReserved[19];
6162 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
6163 ULONG ulGMCRestoreResetTime;
6164 ULONG ulReserved4;
6165 ULONG ulIdleNClk;
6166 ULONG ulDDR_DLL_PowerUpTime;
6167 ULONG ulDDR_PLL_PowerUpTime;
6168 USHORT usPCIEClkSSPercentage;
6169 USHORT usPCIEClkSSType;
6170 USHORT usLvdsSSPercentage;
6171 USHORT usLvdsSSpreadRateIn10Hz;
6172 USHORT usHDMISSPercentage;
6173 USHORT usHDMISSpreadRateIn10Hz;
6174 USHORT usDVISSPercentage;
6175 USHORT usDVISSpreadRateIn10Hz;
6176 ULONG ulGPUReservedSysMemBaseAddrLo;
6177 ULONG ulGPUReservedSysMemBaseAddrHi;
6178 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage;
6179 ULONG ulReserved5;
6180 USHORT usMaxLVDSPclkFreqInSingleLink;
6181 UCHAR ucLvdsMisc;
6182 UCHAR ucTravisLVDSVolAdjust;
6183 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6184 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6185 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6186 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6187 UCHAR ucLVDSOffToOnDelay_in4Ms;
6188 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6189 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6190 UCHAR ucMinAllowedBL_Level;
6191 ULONG ulLCDBitDepthControlVal;
6192 ULONG ulNbpStateMemclkFreq[4];
6193 ULONG ulPSPVersion;
6194 ULONG ulNbpStateNClkFreq[4];
6195 USHORT usNBPStateVoltage[4];
6196 USHORT usBootUpNBVoltage;
6197 USHORT usReserved2;
6198 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
6199}ATOM_INTEGRATED_SYSTEM_INFO_V1_8;
6200
6201/**********************************************************************************************************************
6202 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description
6203ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
6204ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6205ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6206sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
6207
6208ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
6209 ATOM_DEVICE_CRT1_SUPPORT 0x0001
6210 ATOM_DEVICE_DFP1_SUPPORT 0x0008
6211 ATOM_DEVICE_DFP6_SUPPORT 0x0040
6212 ATOM_DEVICE_DFP2_SUPPORT 0x0080
6213 ATOM_DEVICE_DFP3_SUPPORT 0x0200
6214 ATOM_DEVICE_DFP4_SUPPORT 0x0400
6215 ATOM_DEVICE_DFP5_SUPPORT 0x0800
6216 ATOM_DEVICE_LCD1_SUPPORT 0x0002
6217
6218ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface
6219 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6220 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6221 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6222 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6223 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6224 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6225 bit[3]=0: VBIOS fast boot is disable
6226 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
6227
6228ulGPUCapInfo: bit[0~2]= Reserved
6229 bit[3]=0: Enable AUX HW mode detection logic
6230 =1: Disable AUX HW mode detection logic
6231 bit[4]=0: Disable DFS bypass feature
6232 =1: Enable DFS bypass feature
6233
6234usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6235 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
6236
6237 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
6238 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
6239 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
6240 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6241 and enabling VariBri under the driver environment from PP table is optional.
6242
6243 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
6244 that BL control from GPU is expected.
6245 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
6246 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
6247 it's per platform
6248 and enabling VariBri under the driver environment from PP table is optional.
6249
6250ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.
6251ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
6252 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
6253
6254ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
6255 =1: PCIE Power Gating Enabled
6256 Bit[1]=0: DDR-DLL shut-down feature disabled.
6257 1: DDR-DLL shut-down feature enabled.
6258 Bit[2]=0: DDR-PLL Power down feature disabled.
6259 1: DDR-PLL Power down feature enabled.
6260 Bit[3]=0: GNB DPM is disabled
6261 =1: GNB DPM is enabled
6262ulCPUCapInfo: TBD
6263
6264usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
6265usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
6266 to indicate a range.
6267 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
6268 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
6269 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
6270 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
6271
6272ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
6273ucUMAChannelNumber: System memory channel numbers.
6274
6275strVBIOSMsg[40]: VBIOS boot up customized message string
6276
6277sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
6278
6279ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
6280ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
6281ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
6282ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
6283
6284usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
6285usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
6286usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
6287usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6288usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6289usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6290usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6291usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6292
6293usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.
6294ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory.
6295ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.
6296
6297usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
6298ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
6299 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
6300 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6301 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
6302 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
6303 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
6304ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
6305 value to program Travis register LVDS_CTRL_4
6306ucLVDSPwrOnSeqDIGONtoDE_in4Ms:
6307 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
6308 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6309 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6310ucLVDSPwrOnDEtoVARY_BL_in4Ms:
6311 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
6312 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6313 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6314ucLVDSPwrOffVARY_BLtoDE_in4Ms:
6315 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
6316 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6317 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6318ucLVDSPwrOffDEtoDIGON_in4Ms:
6319 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
6320 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6321 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6322ucLVDSOffToOnDelay_in4Ms:
6323 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
6324 =0 means to use VBIOS default delay which is 125 ( 500ms ).
6325 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6326ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
6327 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
6328 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6329 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6330
6331ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
6332 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
6333 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6334 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6335ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
6336
6337ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
6338
6339ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
6340ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6341usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6342usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6343sExtDispConnInfo: Display connector information table provided to VBIOS
6344
6345**********************************************************************************************************************/
6346
Alex Deuchera02860aa2015-04-20 16:44:53 -04006347typedef struct _ATOM_I2C_REG_INFO
6348{
6349 UCHAR ucI2cRegIndex;
6350 UCHAR ucI2cRegVal;
6351}ATOM_I2C_REG_INFO;
6352
6353// this IntegrateSystemInfoTable is used for Carrizo
6354typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
6355{
6356 ATOM_COMMON_TABLE_HEADER sHeader;
6357 ULONG ulBootUpEngineClock;
6358 ULONG ulDentistVCOFreq;
6359 ULONG ulBootUpUMAClock;
6360 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error
6361 ULONG ulBootUpReqDisplayVector;
6362 ULONG ulVBIOSMisc;
6363 ULONG ulGPUCapInfo;
6364 ULONG ulDISP_CLK2Freq;
6365 USHORT usRequestedPWMFreqInHz;
6366 UCHAR ucHtcTmpLmt;
6367 UCHAR ucHtcHystLmt;
6368 ULONG ulReserved2;
6369 ULONG ulSystemConfig;
6370 ULONG ulCPUCapInfo;
6371 ULONG ulReserved3;
6372 USHORT usGPUReservedSysMemSize;
6373 USHORT usExtDispConnInfoOffset;
6374 USHORT usPanelRefreshRateRange;
6375 UCHAR ucMemoryType;
6376 UCHAR ucUMAChannelNumber;
6377 UCHAR strVBIOSMsg[40];
6378 ATOM_TDP_CONFIG asTdpConfig;
6379 UCHAR ucExtHDMIReDrvSlvAddr;
6380 UCHAR ucExtHDMIReDrvRegNum;
6381 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9];
6382 ULONG ulReserved[2];
6383 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];
6384 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error
6385 ULONG ulGMCRestoreResetTime;
6386 ULONG ulReserved4;
6387 ULONG ulIdleNClk;
6388 ULONG ulDDR_DLL_PowerUpTime;
6389 ULONG ulDDR_PLL_PowerUpTime;
6390 USHORT usPCIEClkSSPercentage;
6391 USHORT usPCIEClkSSType;
6392 USHORT usLvdsSSPercentage;
6393 USHORT usLvdsSSpreadRateIn10Hz;
6394 USHORT usHDMISSPercentage;
6395 USHORT usHDMISSpreadRateIn10Hz;
6396 USHORT usDVISSPercentage;
6397 USHORT usDVISSpreadRateIn10Hz;
6398 ULONG ulGPUReservedSysMemBaseAddrLo;
6399 ULONG ulGPUReservedSysMemBaseAddrHi;
6400 ULONG ulReserved5[3];
6401 USHORT usMaxLVDSPclkFreqInSingleLink;
6402 UCHAR ucLvdsMisc;
6403 UCHAR ucTravisLVDSVolAdjust;
6404 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6405 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6406 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6407 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6408 UCHAR ucLVDSOffToOnDelay_in4Ms;
6409 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6410 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6411 UCHAR ucMinAllowedBL_Level;
6412 ULONG ulLCDBitDepthControlVal;
6413 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6414 ULONG ulPSPVersion;
6415 ULONG ulNbpStateNClkFreq[4];
6416 USHORT usNBPStateVoltage[4];
6417 USHORT usBootUpNBVoltage;
6418 UCHAR ucEDPv1_4VSMode;
6419 UCHAR ucReserved2;
6420 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
6421}ATOM_INTEGRATED_SYSTEM_INFO_V1_9;
6422
6423
6424// definition for ucEDPv1_4VSMode
6425#define EDP_VS_LEGACY_MODE 0
6426#define EDP_VS_LOW_VDIFF_MODE 1
6427#define EDP_VS_HIGH_VDIFF_MODE 2
6428#define EDP_VS_STRETCH_MODE 3
6429#define EDP_VS_SINGLE_VDIFF_MODE 4
6430#define EDP_VS_VARIABLE_PREM_MODE 5
6431
6432
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006433// ulGPUCapInfo
6434#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08
6435#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10
6436//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
6437#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000
6438//ulGPUCapInfo[18]=1 indicate the IOMMU is not available
6439#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000
6440//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened.
6441#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000
6442
6443
6444typedef struct _DPHY_TIMING_PARA
6445{
6446 UCHAR ucProfileID; // SENSOR_PROFILES
6447 ULONG ucPara;
6448} DPHY_TIMING_PARA;
6449
6450typedef struct _DPHY_ELEC_PARA
6451{
6452 USHORT usPara[3];
6453} DPHY_ELEC_PARA;
6454
6455typedef struct _CAMERA_MODULE_INFO
6456{
6457 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
6458 UCHAR strModuleName[8];
6459 DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor
6460} CAMERA_MODULE_INFO;
6461
6462typedef struct _FLASHLIGHT_INFO
6463{
6464 UCHAR ucID; // 0: Rear, 1: Front
6465 UCHAR strName[8];
6466} FLASHLIGHT_INFO;
6467
6468typedef struct _CAMERA_DATA
6469{
6470 ULONG ulVersionCode;
6471 CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max
6472 FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max
6473 DPHY_ELEC_PARA asDphyElecPara;
6474 ULONG ulCrcVal; // CRC
6475}CAMERA_DATA;
6476
Alex Deuchera02860aa2015-04-20 16:44:53 -04006477typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
6478{
6479 ATOM_COMMON_TABLE_HEADER sHeader;
6480 ULONG ulBootUpEngineClock;
6481 ULONG ulDentistVCOFreq;
6482 ULONG ulBootUpUMAClock;
6483 ULONG ulReserved0[8];
6484 ULONG ulBootUpReqDisplayVector;
6485 ULONG ulVBIOSMisc;
6486 ULONG ulGPUCapInfo;
6487 ULONG ulReserved1;
6488 USHORT usRequestedPWMFreqInHz;
6489 UCHAR ucHtcTmpLmt;
6490 UCHAR ucHtcHystLmt;
6491 ULONG ulReserved2;
6492 ULONG ulSystemConfig;
6493 ULONG ulCPUCapInfo;
6494 ULONG ulReserved3;
6495 USHORT usGPUReservedSysMemSize;
6496 USHORT usExtDispConnInfoOffset;
6497 USHORT usPanelRefreshRateRange;
6498 UCHAR ucMemoryType;
6499 UCHAR ucUMAChannelNumber;
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006500 ULONG ulMsgReserved[10];
Alex Deuchera02860aa2015-04-20 16:44:53 -04006501 ATOM_TDP_CONFIG asTdpConfig;
6502 ULONG ulReserved[7];
6503 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];
6504 ULONG ulReserved6[10];
6505 ULONG ulGMCRestoreResetTime;
6506 ULONG ulReserved4;
6507 ULONG ulIdleNClk;
6508 ULONG ulDDR_DLL_PowerUpTime;
6509 ULONG ulDDR_PLL_PowerUpTime;
6510 USHORT usPCIEClkSSPercentage;
6511 USHORT usPCIEClkSSType;
6512 USHORT usLvdsSSPercentage;
6513 USHORT usLvdsSSpreadRateIn10Hz;
6514 USHORT usHDMISSPercentage;
6515 USHORT usHDMISSpreadRateIn10Hz;
6516 USHORT usDVISSPercentage;
6517 USHORT usDVISSpreadRateIn10Hz;
6518 ULONG ulGPUReservedSysMemBaseAddrLo;
6519 ULONG ulGPUReservedSysMemBaseAddrHi;
6520 ULONG ulReserved5[3];
6521 USHORT usMaxLVDSPclkFreqInSingleLink;
6522 UCHAR ucLvdsMisc;
6523 UCHAR ucTravisLVDSVolAdjust;
6524 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6525 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6526 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6527 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6528 UCHAR ucLVDSOffToOnDelay_in4Ms;
6529 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6530 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6531 UCHAR ucMinAllowedBL_Level;
6532 ULONG ulLCDBitDepthControlVal;
6533 ULONG ulNbpStateMemclkFreq[2];
6534 ULONG ulReserved7[2];
6535 ULONG ulPSPVersion;
6536 ULONG ulNbpStateNClkFreq[4];
6537 USHORT usNBPStateVoltage[4];
6538 USHORT usBootUpNBVoltage;
6539 UCHAR ucEDPv1_4VSMode;
6540 UCHAR ucReserved2;
6541 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006542 CAMERA_DATA asCameraInfo;
6543 ULONG ulReserved8[29];
Alex Deuchera02860aa2015-04-20 16:44:53 -04006544}ATOM_INTEGRATED_SYSTEM_INFO_V1_10;
6545
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006546
6547// this Table is used for Kaveri/Kabini APU
6548typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
6549{
6550 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
6551 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
6552}ATOM_FUSION_SYSTEM_INFO_V2;
6553
6554
6555typedef struct _ATOM_FUSION_SYSTEM_INFO_V3
6556{
6557 ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
6558 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable
6559}ATOM_FUSION_SYSTEM_INFO_V3;
6560
6561#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800
6562
Alex Deuchera02860aa2015-04-20 16:44:53 -04006563/**************************************************************************/
6564// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
6565//Memory SS Info Table
6566//Define Memory Clock SS chip ID
6567#define ICS91719 1
6568#define ICS91720 2
6569
6570//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
6571typedef struct _ATOM_I2C_DATA_RECORD
6572{
6573 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
6574 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
6575}ATOM_I2C_DATA_RECORD;
6576
6577
6578//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
6579typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
6580{
6581 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
6582 UCHAR ucSSChipID; //SS chip being used
6583 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
6584 UCHAR ucNumOfI2CDataRecords; //number of data block
6585 ATOM_I2C_DATA_RECORD asI2CData[1];
6586}ATOM_I2C_DEVICE_SETUP_INFO;
6587
6588//==========================================================================================
6589typedef struct _ATOM_ASIC_MVDD_INFO
6590{
6591 ATOM_COMMON_TABLE_HEADER sHeader;
6592 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
6593}ATOM_ASIC_MVDD_INFO;
6594
6595//==========================================================================================
6596#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
6597
6598//==========================================================================================
6599/**************************************************************************/
6600
6601typedef struct _ATOM_ASIC_SS_ASSIGNMENT
6602{
6603 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6604 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
6605 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
6606 UCHAR ucClockIndication; //Indicate which clock source needs SS
6607 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
6608 UCHAR ucReserved[2];
6609}ATOM_ASIC_SS_ASSIGNMENT;
6610
6611//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
6612//SS is not required or enabled if a match is not found.
6613#define ASIC_INTERNAL_MEMORY_SS 1
6614#define ASIC_INTERNAL_ENGINE_SS 2
6615#define ASIC_INTERNAL_UVD_SS 3
6616#define ASIC_INTERNAL_SS_ON_TMDS 4
6617#define ASIC_INTERNAL_SS_ON_HDMI 5
6618#define ASIC_INTERNAL_SS_ON_LVDS 6
6619#define ASIC_INTERNAL_SS_ON_DP 7
6620#define ASIC_INTERNAL_SS_ON_DCPLL 8
6621#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
6622#define ASIC_INTERNAL_VCE_SS 10
6623#define ASIC_INTERNAL_GPUPLL_SS 11
6624
6625
6626typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
6627{
6628 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6629 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
6630 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
6631 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
6632 UCHAR ucClockIndication; //Indicate which clock source needs SS
6633 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6634 UCHAR ucReserved[2];
6635}ATOM_ASIC_SS_ASSIGNMENT_V2;
6636
6637//ucSpreadSpectrumMode
6638//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
6639//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
6640//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
6641//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
6642//#define ATOM_INTERNAL_SS_MASK 0x00000000
6643//#define ATOM_EXTERNAL_SS_MASK 0x00000002
6644
6645typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
6646{
6647 ATOM_COMMON_TABLE_HEADER sHeader;
6648 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
6649}ATOM_ASIC_INTERNAL_SS_INFO;
6650
6651typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
6652{
6653 ATOM_COMMON_TABLE_HEADER sHeader;
6654 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
6655}ATOM_ASIC_INTERNAL_SS_INFO_V2;
6656
6657typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
6658{
6659 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6660 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
6661 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
6662 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
6663 UCHAR ucClockIndication; //Indicate which clock source needs SS
6664 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6665 UCHAR ucReserved[2];
6666}ATOM_ASIC_SS_ASSIGNMENT_V3;
6667
6668//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode
6669#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01
6670#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02
6671#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10
6672
6673typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
6674{
6675 ATOM_COMMON_TABLE_HEADER sHeader;
6676 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
6677}ATOM_ASIC_INTERNAL_SS_INFO_V3;
6678
6679
6680//==============================Scratch Pad Definition Portion===============================
6681#define ATOM_DEVICE_CONNECT_INFO_DEF 0
6682#define ATOM_ROM_LOCATION_DEF 1
6683#define ATOM_TV_STANDARD_DEF 2
6684#define ATOM_ACTIVE_INFO_DEF 3
6685#define ATOM_LCD_INFO_DEF 4
6686#define ATOM_DOS_REQ_INFO_DEF 5
6687#define ATOM_ACC_CHANGE_INFO_DEF 6
6688#define ATOM_DOS_MODE_INFO_DEF 7
6689#define ATOM_I2C_CHANNEL_STATUS_DEF 8
6690#define ATOM_I2C_CHANNEL_STATUS1_DEF 9
6691#define ATOM_INTERNAL_TIMER_DEF 10
6692
6693// BIOS_0_SCRATCH Definition
6694#define ATOM_S0_CRT1_MONO 0x00000001L
6695#define ATOM_S0_CRT1_COLOR 0x00000002L
6696#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
6697
6698#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
6699#define ATOM_S0_TV1_SVIDEO_A 0x00000008L
6700#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
6701
6702#define ATOM_S0_CV_A 0x00000010L
6703#define ATOM_S0_CV_DIN_A 0x00000020L
6704#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
6705
6706
6707#define ATOM_S0_CRT2_MONO 0x00000100L
6708#define ATOM_S0_CRT2_COLOR 0x00000200L
6709#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
6710
6711#define ATOM_S0_TV1_COMPOSITE 0x00000400L
6712#define ATOM_S0_TV1_SVIDEO 0x00000800L
6713#define ATOM_S0_TV1_SCART 0x00004000L
6714#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
6715
6716#define ATOM_S0_CV 0x00001000L
6717#define ATOM_S0_CV_DIN 0x00002000L
6718#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
6719
6720#define ATOM_S0_DFP1 0x00010000L
6721#define ATOM_S0_DFP2 0x00020000L
6722#define ATOM_S0_LCD1 0x00040000L
6723#define ATOM_S0_LCD2 0x00080000L
6724#define ATOM_S0_DFP6 0x00100000L
6725#define ATOM_S0_DFP3 0x00200000L
6726#define ATOM_S0_DFP4 0x00400000L
6727#define ATOM_S0_DFP5 0x00800000L
6728
6729
6730#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
6731
6732#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
6733 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
6734
6735#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
6736#define ATOM_S0_THERMAL_STATE_SHIFT 26
6737
6738#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
6739#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
6740
6741#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
6742#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
6743#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
6744#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
6745
6746//Byte aligned defintion for BIOS usage
6747#define ATOM_S0_CRT1_MONOb0 0x01
6748#define ATOM_S0_CRT1_COLORb0 0x02
6749#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
6750
6751#define ATOM_S0_TV1_COMPOSITEb0 0x04
6752#define ATOM_S0_TV1_SVIDEOb0 0x08
6753#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
6754
6755#define ATOM_S0_CVb0 0x10
6756#define ATOM_S0_CV_DINb0 0x20
6757#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
6758
6759#define ATOM_S0_CRT2_MONOb1 0x01
6760#define ATOM_S0_CRT2_COLORb1 0x02
6761#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
6762
6763#define ATOM_S0_TV1_COMPOSITEb1 0x04
6764#define ATOM_S0_TV1_SVIDEOb1 0x08
6765#define ATOM_S0_TV1_SCARTb1 0x40
6766#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
6767
6768#define ATOM_S0_CVb1 0x10
6769#define ATOM_S0_CV_DINb1 0x20
6770#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
6771
6772#define ATOM_S0_DFP1b2 0x01
6773#define ATOM_S0_DFP2b2 0x02
6774#define ATOM_S0_LCD1b2 0x04
6775#define ATOM_S0_LCD2b2 0x08
6776#define ATOM_S0_DFP6b2 0x10
6777#define ATOM_S0_DFP3b2 0x20
6778#define ATOM_S0_DFP4b2 0x40
6779#define ATOM_S0_DFP5b2 0x80
6780
6781
6782#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
6783#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
6784
6785#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
6786#define ATOM_S0_LCD1_SHIFT 18
6787
6788// BIOS_1_SCRATCH Definition
6789#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
6790#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
6791
6792// BIOS_2_SCRATCH Definition
6793#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
6794#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
6795#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
6796
6797#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
6798#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
6799#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
6800
6801#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
6802#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
6803
6804#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
6805#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
6806#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
6807#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
6808#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
6809#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
6810
6811
6812//Byte aligned defintion for BIOS usage
6813#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
6814#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
6815#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
6816
6817#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
6818#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
6819#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
6820
6821
6822// BIOS_3_SCRATCH Definition
6823#define ATOM_S3_CRT1_ACTIVE 0x00000001L
6824#define ATOM_S3_LCD1_ACTIVE 0x00000002L
6825#define ATOM_S3_TV1_ACTIVE 0x00000004L
6826#define ATOM_S3_DFP1_ACTIVE 0x00000008L
6827#define ATOM_S3_CRT2_ACTIVE 0x00000010L
6828#define ATOM_S3_LCD2_ACTIVE 0x00000020L
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006829#define ATOM_S3_DFP6_ACTIVE 0x00000040L
Alex Deuchera02860aa2015-04-20 16:44:53 -04006830#define ATOM_S3_DFP2_ACTIVE 0x00000080L
6831#define ATOM_S3_CV_ACTIVE 0x00000100L
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006832#define ATOM_S3_DFP3_ACTIVE 0x00000200L
6833#define ATOM_S3_DFP4_ACTIVE 0x00000400L
6834#define ATOM_S3_DFP5_ACTIVE 0x00000800L
Alex Deuchera02860aa2015-04-20 16:44:53 -04006835
6836
6837#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
6838
6839#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
6840#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
6841
6842#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
6843#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
6844#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
6845#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
6846#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
6847#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
6848#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
6849#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
6850#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006851#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
6852#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
6853#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
Alex Deuchera02860aa2015-04-20 16:44:53 -04006854
6855
6856#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
6857#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
6858//Below two definitions are not supported in pplib, but in the old powerplay in DAL
6859#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
6860#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
6861
6862
6863
6864//Byte aligned defintion for BIOS usage
6865#define ATOM_S3_CRT1_ACTIVEb0 0x01
6866#define ATOM_S3_LCD1_ACTIVEb0 0x02
6867#define ATOM_S3_TV1_ACTIVEb0 0x04
6868#define ATOM_S3_DFP1_ACTIVEb0 0x08
6869#define ATOM_S3_CRT2_ACTIVEb0 0x10
6870#define ATOM_S3_LCD2_ACTIVEb0 0x20
6871#define ATOM_S3_DFP6_ACTIVEb0 0x40
6872#define ATOM_S3_DFP2_ACTIVEb0 0x80
6873#define ATOM_S3_CV_ACTIVEb1 0x01
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006874#define ATOM_S3_DFP3_ACTIVEb1 0x02
6875#define ATOM_S3_DFP4_ACTIVEb1 0x04
6876#define ATOM_S3_DFP5_ACTIVEb1 0x08
Alex Deuchera02860aa2015-04-20 16:44:53 -04006877
6878
6879#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
6880
6881#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
6882#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
6883#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
6884#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
6885#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
6886#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
6887#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
6888#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
6889#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
Alex Deucher6e14e92b2015-10-15 00:43:41 -04006890#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
6891#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
6892#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
Alex Deuchera02860aa2015-04-20 16:44:53 -04006893
6894
6895#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
6896
6897
6898// BIOS_4_SCRATCH Definition
6899#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
6900#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
6901#define ATOM_S4_LCD1_REFRESH_SHIFT 8
6902
6903//Byte aligned defintion for BIOS usage
6904#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
6905#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
6906#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
6907
6908// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
6909#define ATOM_S5_DOS_REQ_CRT1b0 0x01
6910#define ATOM_S5_DOS_REQ_LCD1b0 0x02
6911#define ATOM_S5_DOS_REQ_TV1b0 0x04
6912#define ATOM_S5_DOS_REQ_DFP1b0 0x08
6913#define ATOM_S5_DOS_REQ_CRT2b0 0x10
6914#define ATOM_S5_DOS_REQ_LCD2b0 0x20
6915#define ATOM_S5_DOS_REQ_DFP6b0 0x40
6916#define ATOM_S5_DOS_REQ_DFP2b0 0x80
6917#define ATOM_S5_DOS_REQ_CVb1 0x01
6918#define ATOM_S5_DOS_REQ_DFP3b1 0x02
6919#define ATOM_S5_DOS_REQ_DFP4b1 0x04
6920#define ATOM_S5_DOS_REQ_DFP5b1 0x08
6921
6922
6923#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
6924
6925#define ATOM_S5_DOS_REQ_CRT1 0x0001
6926#define ATOM_S5_DOS_REQ_LCD1 0x0002
6927#define ATOM_S5_DOS_REQ_TV1 0x0004
6928#define ATOM_S5_DOS_REQ_DFP1 0x0008
6929#define ATOM_S5_DOS_REQ_CRT2 0x0010
6930#define ATOM_S5_DOS_REQ_LCD2 0x0020
6931#define ATOM_S5_DOS_REQ_DFP6 0x0040
6932#define ATOM_S5_DOS_REQ_DFP2 0x0080
6933#define ATOM_S5_DOS_REQ_CV 0x0100
6934#define ATOM_S5_DOS_REQ_DFP3 0x0200
6935#define ATOM_S5_DOS_REQ_DFP4 0x0400
6936#define ATOM_S5_DOS_REQ_DFP5 0x0800
6937
6938#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
6939#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
6940#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
6941#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
6942#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
6943 (ATOM_S5_DOS_FORCE_CVb3<<8))
6944// BIOS_6_SCRATCH Definition
6945#define ATOM_S6_DEVICE_CHANGE 0x00000001L
6946#define ATOM_S6_SCALER_CHANGE 0x00000002L
6947#define ATOM_S6_LID_CHANGE 0x00000004L
6948#define ATOM_S6_DOCKING_CHANGE 0x00000008L
6949#define ATOM_S6_ACC_MODE 0x00000010L
6950#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
6951#define ATOM_S6_LID_STATE 0x00000040L
6952#define ATOM_S6_DOCK_STATE 0x00000080L
6953#define ATOM_S6_CRITICAL_STATE 0x00000100L
6954#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
6955#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
6956#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
6957#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
6958#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
6959
6960#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
6961#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
6962
6963#define ATOM_S6_ACC_REQ_CRT1 0x00010000L
6964#define ATOM_S6_ACC_REQ_LCD1 0x00020000L
6965#define ATOM_S6_ACC_REQ_TV1 0x00040000L
6966#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
6967#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
6968#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
6969#define ATOM_S6_ACC_REQ_DFP6 0x00400000L
6970#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
6971#define ATOM_S6_ACC_REQ_CV 0x01000000L
6972#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
6973#define ATOM_S6_ACC_REQ_DFP4 0x04000000L
6974#define ATOM_S6_ACC_REQ_DFP5 0x08000000L
6975
6976#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
6977#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
6978#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
6979#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
6980#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
6981
6982//Byte aligned defintion for BIOS usage
6983#define ATOM_S6_DEVICE_CHANGEb0 0x01
6984#define ATOM_S6_SCALER_CHANGEb0 0x02
6985#define ATOM_S6_LID_CHANGEb0 0x04
6986#define ATOM_S6_DOCKING_CHANGEb0 0x08
6987#define ATOM_S6_ACC_MODEb0 0x10
6988#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
6989#define ATOM_S6_LID_STATEb0 0x40
6990#define ATOM_S6_DOCK_STATEb0 0x80
6991#define ATOM_S6_CRITICAL_STATEb1 0x01
6992#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
6993#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
6994#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
6995#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
6996#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
6997
6998#define ATOM_S6_ACC_REQ_CRT1b2 0x01
6999#define ATOM_S6_ACC_REQ_LCD1b2 0x02
7000#define ATOM_S6_ACC_REQ_TV1b2 0x04
7001#define ATOM_S6_ACC_REQ_DFP1b2 0x08
7002#define ATOM_S6_ACC_REQ_CRT2b2 0x10
7003#define ATOM_S6_ACC_REQ_LCD2b2 0x20
7004#define ATOM_S6_ACC_REQ_DFP6b2 0x40
7005#define ATOM_S6_ACC_REQ_DFP2b2 0x80
7006#define ATOM_S6_ACC_REQ_CVb3 0x01
7007#define ATOM_S6_ACC_REQ_DFP3b3 0x02
7008#define ATOM_S6_ACC_REQ_DFP4b3 0x04
7009#define ATOM_S6_ACC_REQ_DFP5b3 0x08
7010
7011#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
7012#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
7013#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
7014#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
7015#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
7016
7017#define ATOM_S6_DEVICE_CHANGE_SHIFT 0
7018#define ATOM_S6_SCALER_CHANGE_SHIFT 1
7019#define ATOM_S6_LID_CHANGE_SHIFT 2
7020#define ATOM_S6_DOCKING_CHANGE_SHIFT 3
7021#define ATOM_S6_ACC_MODE_SHIFT 4
7022#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
7023#define ATOM_S6_LID_STATE_SHIFT 6
7024#define ATOM_S6_DOCK_STATE_SHIFT 7
7025#define ATOM_S6_CRITICAL_STATE_SHIFT 8
7026#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
7027#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
7028#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
7029#define ATOM_S6_REQ_SCALER_SHIFT 12
7030#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
7031#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
7032#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
7033#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
7034#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
7035#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
7036#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
7037
7038// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
7039#define ATOM_S7_DOS_MODE_TYPEb0 0x03
7040#define ATOM_S7_DOS_MODE_VGAb0 0x00
7041#define ATOM_S7_DOS_MODE_VESAb0 0x01
7042#define ATOM_S7_DOS_MODE_EXTb0 0x02
7043#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
7044#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
7045#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
7046#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02
7047#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200
7048#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
7049
7050#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
7051
7052// BIOS_8_SCRATCH Definition
7053#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
7054#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
7055
7056#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
7057#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
7058
7059// BIOS_9_SCRATCH Definition
7060#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
7061#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
7062#endif
7063#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
7064#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
7065#endif
7066#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
7067#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
7068#endif
7069#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
7070#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
7071#endif
7072
7073
7074#define ATOM_FLAG_SET 0x20
7075#define ATOM_FLAG_CLEAR 0
7076#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
7077#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
7078#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
7079#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
7080#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
7081
7082#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
7083#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
7084
7085#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
7086#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
7087#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
7088
7089#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
7090#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
7091#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
7092
7093#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
7094#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
7095
7096#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
7097#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
7098
7099#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
7100#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
7101
7102#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
7103
7104#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
7105
7106#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
7107#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
7108#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
7109#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
7110
7111/****************************************************************************/
7112//Portion II: Definitinos only used in Driver
7113/****************************************************************************/
7114
7115// Macros used by driver
7116
7117#ifdef __cplusplus
7118#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
7119
7120#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
7121#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
7122#else // not __cplusplus
7123#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
7124
7125#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
7126#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
7127#endif // __cplusplus
7128
7129#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
7130#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
7131
7132/****************************************************************************/
7133//Portion III: Definitinos only used in VBIOS
7134/****************************************************************************/
7135#define ATOM_DAC_SRC 0x80
7136#define ATOM_SRC_DAC1 0
7137#define ATOM_SRC_DAC2 0x80
7138
7139
7140
7141typedef struct _MEMORY_PLLINIT_PARAMETERS
7142{
7143 ULONG ulTargetMemoryClock; //In 10Khz unit
7144 UCHAR ucAction; //not define yet
7145 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
7146 UCHAR ucFbDiv; //FB value
7147 UCHAR ucPostDiv; //Post div
7148}MEMORY_PLLINIT_PARAMETERS;
7149
7150#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
7151
7152
7153#define GPIO_PIN_WRITE 0x01
7154#define GPIO_PIN_READ 0x00
7155
7156typedef struct _GPIO_PIN_CONTROL_PARAMETERS
7157{
7158 UCHAR ucGPIO_ID; //return value, read from GPIO pins
7159 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
7160 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
7161 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
7162}GPIO_PIN_CONTROL_PARAMETERS;
7163
7164typedef struct _ENABLE_SCALER_PARAMETERS
7165{
7166 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
7167 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
7168 UCHAR ucTVStandard; //
7169 UCHAR ucPadding[1];
7170}ENABLE_SCALER_PARAMETERS;
7171#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
7172
7173//ucEnable:
7174#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
7175#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
7176#define SCALER_ENABLE_2TAP_ALPHA_MODE 2
7177#define SCALER_ENABLE_MULTITAP_MODE 3
7178
7179typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
7180{
7181 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
7182 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
7183 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
7184 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
7185 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7186}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
7187
7188typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
7189{
7190 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
7191 ENABLE_CRTC_PARAMETERS sReserved;
7192}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
7193
7194typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
7195{
7196 USHORT usHight; // Image Hight
7197 USHORT usWidth; // Image Width
7198 UCHAR ucSurface; // Surface 1 or 2
7199 UCHAR ucPadding[3];
7200}ENABLE_GRAPH_SURFACE_PARAMETERS;
7201
7202typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
7203{
7204 USHORT usHight; // Image Hight
7205 USHORT usWidth; // Image Width
7206 UCHAR ucSurface; // Surface 1 or 2
7207 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7208 UCHAR ucPadding[2];
7209}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
7210
7211typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
7212{
7213 USHORT usHight; // Image Hight
7214 USHORT usWidth; // Image Width
7215 UCHAR ucSurface; // Surface 1 or 2
7216 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7217 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
7218}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
7219
7220typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
7221{
7222 USHORT usHight; // Image Hight
7223 USHORT usWidth; // Image Width
7224 USHORT usGraphPitch;
7225 UCHAR ucColorDepth;
7226 UCHAR ucPixelFormat;
7227 UCHAR ucSurface; // Surface 1 or 2
7228 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7229 UCHAR ucModeType;
7230 UCHAR ucReserved;
7231}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
7232
7233// ucEnable
7234#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f
7235#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10
7236
7237typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
7238{
7239 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
7240 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
7241}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
7242
7243typedef struct _MEMORY_CLEAN_UP_PARAMETERS
7244{
7245 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
7246 USHORT usMemorySize; //8Kb blocks aligned
7247}MEMORY_CLEAN_UP_PARAMETERS;
7248
7249#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
7250
7251typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
7252{
7253 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7254 USHORT usY_Size;
7255}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
7256
7257typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
7258{
7259 union{
7260 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7261 USHORT usSurface;
7262 };
7263 USHORT usY_Size;
7264 USHORT usDispXStart;
7265 USHORT usDispYStart;
7266}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
7267
7268
7269typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
7270{
7271 UCHAR ucLutId;
7272 UCHAR ucAction;
7273 USHORT usLutStartIndex;
7274 USHORT usLutLength;
7275 USHORT usLutOffsetInVram;
7276}PALETTE_DATA_CONTROL_PARAMETERS_V3;
7277
7278// ucAction:
7279#define PALETTE_DATA_AUTO_FILL 1
7280#define PALETTE_DATA_READ 2
7281#define PALETTE_DATA_WRITE 3
7282
7283
7284typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
7285{
7286 UCHAR ucInterruptId;
7287 UCHAR ucServiceId;
7288 UCHAR ucStatus;
7289 UCHAR ucReserved;
7290}INTERRUPT_SERVICE_PARAMETER_V2;
7291
7292// ucInterruptId
7293#define HDP1_INTERRUPT_ID 1
7294#define HDP2_INTERRUPT_ID 2
7295#define HDP3_INTERRUPT_ID 3
7296#define HDP4_INTERRUPT_ID 4
7297#define HDP5_INTERRUPT_ID 5
7298#define HDP6_INTERRUPT_ID 6
7299#define SW_INTERRUPT_ID 11
7300
7301// ucAction
7302#define INTERRUPT_SERVICE_GEN_SW_INT 1
7303#define INTERRUPT_SERVICE_GET_STATUS 2
7304
7305 // ucStatus
7306#define INTERRUPT_STATUS__INT_TRIGGER 1
7307#define INTERRUPT_STATUS__HPD_HIGH 2
7308
7309typedef struct _EFUSE_INPUT_PARAMETER
7310{
7311 USHORT usEfuseIndex;
7312 UCHAR ucBitShift;
7313 UCHAR ucBitLength;
7314}EFUSE_INPUT_PARAMETER;
7315
7316// ReadEfuseValue command table input/output parameter
7317typedef union _READ_EFUSE_VALUE_PARAMETER
7318{
7319 EFUSE_INPUT_PARAMETER sEfuse;
7320 ULONG ulEfuseValue;
7321}READ_EFUSE_VALUE_PARAMETER;
7322
7323typedef struct _INDIRECT_IO_ACCESS
7324{
7325 ATOM_COMMON_TABLE_HEADER sHeader;
7326 UCHAR IOAccessSequence[256];
7327} INDIRECT_IO_ACCESS;
7328
7329#define INDIRECT_READ 0x00
7330#define INDIRECT_WRITE 0x80
7331
7332#define INDIRECT_IO_MM 0
7333#define INDIRECT_IO_PLL 1
7334#define INDIRECT_IO_MC 2
7335#define INDIRECT_IO_PCIE 3
7336#define INDIRECT_IO_PCIEP 4
7337#define INDIRECT_IO_NBMISC 5
7338#define INDIRECT_IO_SMU 5
7339
7340#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
7341#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
7342#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
7343#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
7344#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
7345#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
7346#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
7347#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
7348#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ
7349#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE
7350#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ
7351#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE
7352
7353
7354typedef struct _ATOM_OEM_INFO
7355{
7356 ATOM_COMMON_TABLE_HEADER sHeader;
7357 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
7358}ATOM_OEM_INFO;
7359
7360typedef struct _ATOM_TV_MODE
7361{
7362 UCHAR ucVMode_Num; //Video mode number
7363 UCHAR ucTV_Mode_Num; //Internal TV mode number
7364}ATOM_TV_MODE;
7365
7366typedef struct _ATOM_BIOS_INT_TVSTD_MODE
7367{
7368 ATOM_COMMON_TABLE_HEADER sHeader;
7369 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
7370 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
7371 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
7372 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
7373 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
7374}ATOM_BIOS_INT_TVSTD_MODE;
7375
7376
7377typedef struct _ATOM_TV_MODE_SCALER_PTR
7378{
7379 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
7380 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
7381 UCHAR ucTV_Mode_Num;
7382}ATOM_TV_MODE_SCALER_PTR;
7383
7384typedef struct _ATOM_STANDARD_VESA_TIMING
7385{
7386 ATOM_COMMON_TABLE_HEADER sHeader;
7387 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
7388}ATOM_STANDARD_VESA_TIMING;
7389
7390
7391typedef struct _ATOM_STD_FORMAT
7392{
7393 USHORT usSTD_HDisp;
7394 USHORT usSTD_VDisp;
7395 USHORT usSTD_RefreshRate;
7396 USHORT usReserved;
7397}ATOM_STD_FORMAT;
7398
7399typedef struct _ATOM_VESA_TO_EXTENDED_MODE
7400{
7401 USHORT usVESA_ModeNumber;
7402 USHORT usExtendedModeNumber;
7403}ATOM_VESA_TO_EXTENDED_MODE;
7404
7405typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
7406{
7407 ATOM_COMMON_TABLE_HEADER sHeader;
7408 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
7409}ATOM_VESA_TO_INTENAL_MODE_LUT;
7410
7411/*************** ATOM Memory Related Data Structure ***********************/
7412typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
7413 UCHAR ucMemoryType;
7414 UCHAR ucMemoryVendor;
7415 UCHAR ucAdjMCId;
7416 UCHAR ucDynClkId;
7417 ULONG ulDllResetClkRange;
7418}ATOM_MEMORY_VENDOR_BLOCK;
7419
7420
7421typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
7422#if ATOM_BIG_ENDIAN
7423 ULONG ucMemBlkId:8;
7424 ULONG ulMemClockRange:24;
7425#else
7426 ULONG ulMemClockRange:24;
7427 ULONG ucMemBlkId:8;
7428#endif
7429}ATOM_MEMORY_SETTING_ID_CONFIG;
7430
7431typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
7432{
7433 ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
7434 ULONG ulAccess;
7435}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
7436
7437
7438typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
7439 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
7440 ULONG aulMemData[1];
7441}ATOM_MEMORY_SETTING_DATA_BLOCK;
7442
7443
7444typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
7445 USHORT usRegIndex; // MC register index
7446 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
7447}ATOM_INIT_REG_INDEX_FORMAT;
7448
7449
7450typedef struct _ATOM_INIT_REG_BLOCK{
7451 USHORT usRegIndexTblSize; //size of asRegIndexBuf
7452 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
7453 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
7454 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
7455}ATOM_INIT_REG_BLOCK;
7456
7457#define END_OF_REG_INDEX_BLOCK 0x0ffff
7458#define END_OF_REG_DATA_BLOCK 0x00000000
7459#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS
7460#define CLOCK_RANGE_HIGHEST 0x00ffffff
7461
7462#define VALUE_DWORD SIZEOF ULONG
7463#define VALUE_SAME_AS_ABOVE 0
7464#define VALUE_MASK_DWORD 0x84
7465
7466#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
7467#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
7468#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
7469//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
7470#define ACCESS_PLACEHOLDER 0x80
7471
7472
7473typedef struct _ATOM_MC_INIT_PARAM_TABLE
7474{
7475 ATOM_COMMON_TABLE_HEADER sHeader;
7476 USHORT usAdjustARB_SEQDataOffset;
7477 USHORT usMCInitMemTypeTblOffset;
7478 USHORT usMCInitCommonTblOffset;
7479 USHORT usMCInitPowerDownTblOffset;
7480 ULONG ulARB_SEQDataBuf[32];
7481 ATOM_INIT_REG_BLOCK asMCInitMemType;
7482 ATOM_INIT_REG_BLOCK asMCInitCommon;
7483}ATOM_MC_INIT_PARAM_TABLE;
7484
7485
7486typedef struct _ATOM_REG_INIT_SETTING
7487{
7488 USHORT usRegIndex;
7489 ULONG ulRegValue;
7490}ATOM_REG_INIT_SETTING;
7491
7492typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1
7493{
7494 ATOM_COMMON_TABLE_HEADER sHeader;
7495 ULONG ulMCUcodeVersion;
7496 ULONG ulMCUcodeRomStartAddr;
7497 ULONG ulMCUcodeLength;
7498 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings.
Geliang Tangd0be9f42015-10-18 23:29:48 +08007499 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting
Alex Deuchera02860aa2015-04-20 16:44:53 -04007500}ATOM_MC_INIT_PARAM_TABLE_V2_1;
7501
7502
7503#define _4Mx16 0x2
7504#define _4Mx32 0x3
7505#define _8Mx16 0x12
7506#define _8Mx32 0x13
7507#define _8Mx128 0x15
7508#define _16Mx16 0x22
7509#define _16Mx32 0x23
7510#define _16Mx128 0x25
7511#define _32Mx16 0x32
7512#define _32Mx32 0x33
7513#define _32Mx128 0x35
Alex Deuchera02860aa2015-04-20 16:44:53 -04007514#define _64Mx8 0x41
7515#define _64Mx16 0x42
Alex Deucher6e14e92b2015-10-15 00:43:41 -04007516#define _64Mx32 0x43
7517#define _64Mx128 0x45
Alex Deuchera02860aa2015-04-20 16:44:53 -04007518#define _128Mx8 0x51
7519#define _128Mx16 0x52
7520#define _128Mx32 0x53
7521#define _256Mx8 0x61
7522#define _256Mx16 0x62
Alex Deucher6e14e92b2015-10-15 00:43:41 -04007523#define _256Mx32 0x63
Alex Deuchera02860aa2015-04-20 16:44:53 -04007524#define _512Mx8 0x71
Alex Deucher6e14e92b2015-10-15 00:43:41 -04007525#define _512Mx16 0x72
Alex Deuchera02860aa2015-04-20 16:44:53 -04007526
7527
7528#define SAMSUNG 0x1
7529#define INFINEON 0x2
7530#define ELPIDA 0x3
7531#define ETRON 0x4
7532#define NANYA 0x5
7533#define HYNIX 0x6
7534#define MOSEL 0x7
7535#define WINBOND 0x8
7536#define ESMT 0x9
7537#define MICRON 0xF
7538
7539#define QIMONDA INFINEON
7540#define PROMOS MOSEL
7541#define KRETON INFINEON
7542#define ELIXIR NANYA
7543#define MEZZA ELPIDA
7544
7545
7546/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
7547
7548#define UCODE_ROM_START_ADDRESS 0x1b800
7549#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7550
7551//uCode block header for reference
7552
7553typedef struct _MCuCodeHeader
7554{
7555 ULONG ulSignature;
7556 UCHAR ucRevision;
7557 UCHAR ucChecksum;
7558 UCHAR ucReserved1;
7559 UCHAR ucReserved2;
7560 USHORT usParametersLength;
7561 USHORT usUCodeLength;
7562 USHORT usReserved1;
7563 USHORT usReserved2;
7564} MCuCodeHeader;
7565
7566//////////////////////////////////////////////////////////////////////////////////
7567
7568#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
7569
7570#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
7571typedef struct _ATOM_VRAM_MODULE_V1
7572{
7573 ULONG ulReserved;
7574 USHORT usEMRSValue;
7575 USHORT usMRSValue;
7576 USHORT usReserved;
7577 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7578 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
7579 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
7580 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7581 UCHAR ucRow; // Number of Row,in power of 2;
7582 UCHAR ucColumn; // Number of Column,in power of 2;
7583 UCHAR ucBank; // Nunber of Bank;
7584 UCHAR ucRank; // Number of Rank, in power of 2
7585 UCHAR ucChannelNum; // Number of channel;
7586 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7587 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7588 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7589 UCHAR ucReserved[2];
7590}ATOM_VRAM_MODULE_V1;
7591
7592
7593typedef struct _ATOM_VRAM_MODULE_V2
7594{
7595 ULONG ulReserved;
7596 ULONG ulFlags; // To enable/disable functionalities based on memory type
7597 ULONG ulEngineClock; // Override of default engine clock for particular memory type
7598 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
7599 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7600 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7601 USHORT usEMRSValue;
7602 USHORT usMRSValue;
7603 USHORT usReserved;
7604 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7605 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7606 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7607 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7608 UCHAR ucRow; // Number of Row,in power of 2;
7609 UCHAR ucColumn; // Number of Column,in power of 2;
7610 UCHAR ucBank; // Nunber of Bank;
7611 UCHAR ucRank; // Number of Rank, in power of 2
7612 UCHAR ucChannelNum; // Number of channel;
7613 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7614 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7615 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7616 UCHAR ucRefreshRateFactor;
7617 UCHAR ucReserved[3];
7618}ATOM_VRAM_MODULE_V2;
7619
7620
7621typedef struct _ATOM_MEMORY_TIMING_FORMAT
7622{
7623 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7624 union{
7625 USHORT usMRS; // mode register
7626 USHORT usDDR3_MR0;
7627 };
7628 union{
7629 USHORT usEMRS; // extended mode register
7630 USHORT usDDR3_MR1;
7631 };
7632 UCHAR ucCL; // CAS latency
7633 UCHAR ucWL; // WRITE Latency
7634 UCHAR uctRAS; // tRAS
7635 UCHAR uctRC; // tRC
7636 UCHAR uctRFC; // tRFC
7637 UCHAR uctRCDR; // tRCDR
7638 UCHAR uctRCDW; // tRCDW
7639 UCHAR uctRP; // tRP
7640 UCHAR uctRRD; // tRRD
7641 UCHAR uctWR; // tWR
7642 UCHAR uctWTR; // tWTR
7643 UCHAR uctPDIX; // tPDIX
7644 UCHAR uctFAW; // tFAW
7645 UCHAR uctAOND; // tAOND
7646 union
7647 {
7648 struct {
7649 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7650 UCHAR ucReserved;
7651 };
7652 USHORT usDDR3_MR2;
7653 };
7654}ATOM_MEMORY_TIMING_FORMAT;
7655
7656
7657typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
7658{
7659 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7660 USHORT usMRS; // mode register
7661 USHORT usEMRS; // extended mode register
7662 UCHAR ucCL; // CAS latency
7663 UCHAR ucWL; // WRITE Latency
7664 UCHAR uctRAS; // tRAS
7665 UCHAR uctRC; // tRC
7666 UCHAR uctRFC; // tRFC
7667 UCHAR uctRCDR; // tRCDR
7668 UCHAR uctRCDW; // tRCDW
7669 UCHAR uctRP; // tRP
7670 UCHAR uctRRD; // tRRD
7671 UCHAR uctWR; // tWR
7672 UCHAR uctWTR; // tWTR
7673 UCHAR uctPDIX; // tPDIX
7674 UCHAR uctFAW; // tFAW
7675 UCHAR uctAOND; // tAOND
7676 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7677////////////////////////////////////GDDR parameters///////////////////////////////////
7678 UCHAR uctCCDL; //
7679 UCHAR uctCRCRL; //
7680 UCHAR uctCRCWL; //
7681 UCHAR uctCKE; //
7682 UCHAR uctCKRSE; //
7683 UCHAR uctCKRSX; //
7684 UCHAR uctFAW32; //
7685 UCHAR ucMR5lo; //
7686 UCHAR ucMR5hi; //
7687 UCHAR ucTerminator;
7688}ATOM_MEMORY_TIMING_FORMAT_V1;
7689
7690
7691
7692
7693typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
7694{
7695 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7696 USHORT usMRS; // mode register
7697 USHORT usEMRS; // extended mode register
7698 UCHAR ucCL; // CAS latency
7699 UCHAR ucWL; // WRITE Latency
7700 UCHAR uctRAS; // tRAS
7701 UCHAR uctRC; // tRC
7702 UCHAR uctRFC; // tRFC
7703 UCHAR uctRCDR; // tRCDR
7704 UCHAR uctRCDW; // tRCDW
7705 UCHAR uctRP; // tRP
7706 UCHAR uctRRD; // tRRD
7707 UCHAR uctWR; // tWR
7708 UCHAR uctWTR; // tWTR
7709 UCHAR uctPDIX; // tPDIX
7710 UCHAR uctFAW; // tFAW
7711 UCHAR uctAOND; // tAOND
7712 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7713////////////////////////////////////GDDR parameters///////////////////////////////////
7714 UCHAR uctCCDL; //
7715 UCHAR uctCRCRL; //
7716 UCHAR uctCRCWL; //
7717 UCHAR uctCKE; //
7718 UCHAR uctCKRSE; //
7719 UCHAR uctCKRSX; //
7720 UCHAR uctFAW32; //
7721 UCHAR ucMR4lo; //
7722 UCHAR ucMR4hi; //
7723 UCHAR ucMR5lo; //
7724 UCHAR ucMR5hi; //
7725 UCHAR ucTerminator;
7726 UCHAR ucReserved;
7727}ATOM_MEMORY_TIMING_FORMAT_V2;
7728
7729
7730typedef struct _ATOM_MEMORY_FORMAT
7731{
7732 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
7733 union{
7734 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7735 USHORT usDDR3_Reserved; // Not used for DDR3 memory
7736 };
7737 union{
7738 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7739 USHORT usDDR3_MR3; // Used for DDR3 memory
7740 };
7741 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7742 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7743 UCHAR ucRow; // Number of Row,in power of 2;
7744 UCHAR ucColumn; // Number of Column,in power of 2;
7745 UCHAR ucBank; // Nunber of Bank;
7746 UCHAR ucRank; // Number of Rank, in power of 2
7747 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7748 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
7749 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
7750 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7751 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7752 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
7753 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock
7754}ATOM_MEMORY_FORMAT;
7755
7756
7757typedef struct _ATOM_VRAM_MODULE_V3
7758{
7759 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
7760 USHORT usSize; // size of ATOM_VRAM_MODULE_V3
7761 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
7762 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
7763 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7764 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
7765 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
7766 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7767 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7768 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7769 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
7770}ATOM_VRAM_MODULE_V3;
7771
7772
7773//ATOM_VRAM_MODULE_V3.ucNPL_RT
7774#define NPL_RT_MASK 0x0f
7775#define BATTERY_ODT_MASK 0xc0
7776
7777#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
7778
7779typedef struct _ATOM_VRAM_MODULE_V4
7780{
7781 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7782 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7783 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7784 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7785 USHORT usReserved;
7786 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7787 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7788 UCHAR ucChannelNum; // Number of channels present in this module config
7789 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7790 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7791 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7792 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7793 UCHAR ucVREFI; // board dependent parameter
7794 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7795 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7796 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7797 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7798 UCHAR ucReserved[3];
7799
7800//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7801 union{
7802 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7803 USHORT usDDR3_Reserved;
7804 };
7805 union{
7806 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7807 USHORT usDDR3_MR3; // Used for DDR3 memory
7808 };
7809 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7810 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7811 UCHAR ucReserved2[2];
7812 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7813}ATOM_VRAM_MODULE_V4;
7814
7815#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
7816#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
7817#define VRAM_MODULE_V4_MISC_BL_MASK 0x4
7818#define VRAM_MODULE_V4_MISC_BL8 0x4
7819#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
7820
7821typedef struct _ATOM_VRAM_MODULE_V5
7822{
7823 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7824 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7825 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7826 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7827 USHORT usReserved;
7828 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7829 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7830 UCHAR ucChannelNum; // Number of channels present in this module config
7831 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7832 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7833 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7834 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7835 UCHAR ucVREFI; // board dependent parameter
7836 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7837 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7838 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7839 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7840 UCHAR ucReserved[3];
7841
7842//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7843 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7844 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7845 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7846 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7847 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7848 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7849 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7850}ATOM_VRAM_MODULE_V5;
7851
7852
7853typedef struct _ATOM_VRAM_MODULE_V6
7854{
7855 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7856 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7857 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7858 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7859 USHORT usReserved;
7860 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7861 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7862 UCHAR ucChannelNum; // Number of channels present in this module config
7863 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7864 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7865 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7866 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7867 UCHAR ucVREFI; // board dependent parameter
7868 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7869 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7870 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7871 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7872 UCHAR ucReserved[3];
7873
7874//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7875 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7876 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7877 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7878 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7879 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7880 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7881 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7882}ATOM_VRAM_MODULE_V6;
7883
7884typedef struct _ATOM_VRAM_MODULE_V7
7885{
7886// Design Specific Values
7887 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7888 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
7889 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7890 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7891 UCHAR ucExtMemoryID; // Current memory module ID
7892 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7893 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7894 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7895 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7896 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
7897 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7898 UCHAR ucVREFI; // Not used.
7899 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7900 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7901 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7902 USHORT usSEQSettingOffset;
7903 UCHAR ucReserved;
7904// Memory Module specific values
7905 USHORT usEMRS2Value; // EMRS2/MR2 Value.
7906 USHORT usEMRS3Value; // EMRS3/MR3 Value.
7907 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7908 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7909 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7910 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7911 char strMemPNString[20]; // part number end with '0'.
7912}ATOM_VRAM_MODULE_V7;
7913
7914
7915typedef struct _ATOM_VRAM_MODULE_V8
7916{
7917// Design Specific Values
7918 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7919 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
7920 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7921 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7922 UCHAR ucExtMemoryID; // Current memory module ID
7923 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7924 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7925 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7926 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7927 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
7928 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7929 UCHAR ucVREFI; // Not used.
7930 USHORT usReserved; // Not used
7931 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
7932 UCHAR ucMcTunningSetId; // MC phy registers set per.
7933 UCHAR ucRowNum;
7934// Memory Module specific values
7935 USHORT usEMRS2Value; // EMRS2/MR2 Value.
7936 USHORT usEMRS3Value; // EMRS3/MR3 Value.
7937 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7938 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7939 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7940 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7941
7942 ULONG ulChannelMapCfg1; // channel mapping for channel8~15
7943 ULONG ulBankMapCfg;
7944 ULONG ulReserved;
7945 char strMemPNString[20]; // part number end with '0'.
7946}ATOM_VRAM_MODULE_V8;
7947
7948
7949typedef struct _ATOM_VRAM_INFO_V2
7950{
7951 ATOM_COMMON_TABLE_HEADER sHeader;
7952 UCHAR ucNumOfVRAMModule;
7953 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7954}ATOM_VRAM_INFO_V2;
7955
7956typedef struct _ATOM_VRAM_INFO_V3
7957{
7958 ATOM_COMMON_TABLE_HEADER sHeader;
7959 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7960 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7961 USHORT usRerseved;
7962 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
7963 UCHAR ucNumOfVRAMModule;
7964 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7965 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
7966
7967}ATOM_VRAM_INFO_V3;
7968
7969#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
7970
7971typedef struct _ATOM_VRAM_INFO_V4
7972{
7973 ATOM_COMMON_TABLE_HEADER sHeader;
7974 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7975 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7976 USHORT usRerseved;
7977 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
7978 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
7979 UCHAR ucReservde[4];
7980 UCHAR ucNumOfVRAMModule;
7981 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7982 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
7983}ATOM_VRAM_INFO_V4;
7984
7985typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
7986{
7987 ATOM_COMMON_TABLE_HEADER sHeader;
7988 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7989 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7990 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
7991 USHORT usReserved[3];
7992 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
7993 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
7994 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
7995 UCHAR ucReserved;
7996 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7997}ATOM_VRAM_INFO_HEADER_V2_1;
7998
7999typedef struct _ATOM_VRAM_INFO_HEADER_V2_2
8000{
8001 ATOM_COMMON_TABLE_HEADER sHeader;
8002 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
8003 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
8004 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
8005 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set
8006 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping
8007 USHORT usReserved1;
8008 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
8009 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
8010 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
8011 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
8012 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
8013}ATOM_VRAM_INFO_HEADER_V2_2;
8014
8015
8016typedef struct _ATOM_DRAM_DATA_REMAP
8017{
8018 UCHAR ucByteRemapCh0;
8019 UCHAR ucByteRemapCh1;
8020 ULONG ulByte0BitRemapCh0;
8021 ULONG ulByte1BitRemapCh0;
8022 ULONG ulByte2BitRemapCh0;
8023 ULONG ulByte3BitRemapCh0;
8024 ULONG ulByte0BitRemapCh1;
8025 ULONG ulByte1BitRemapCh1;
8026 ULONG ulByte2BitRemapCh1;
8027 ULONG ulByte3BitRemapCh1;
8028}ATOM_DRAM_DATA_REMAP;
8029
8030typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
8031{
8032 ATOM_COMMON_TABLE_HEADER sHeader;
8033 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
8034}ATOM_VRAM_GPIO_DETECTION_INFO;
8035
8036
8037typedef struct _ATOM_MEMORY_TRAINING_INFO
8038{
8039 ATOM_COMMON_TABLE_HEADER sHeader;
8040 UCHAR ucTrainingLoop;
8041 UCHAR ucReserved[3];
8042 ATOM_INIT_REG_BLOCK asMemTrainingSetting;
8043}ATOM_MEMORY_TRAINING_INFO;
8044
8045
Alex Deucher6e14e92b2015-10-15 00:43:41 -04008046typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1
8047{
8048 ATOM_COMMON_TABLE_HEADER sHeader;
8049 ULONG ulMCUcodeVersion;
8050 USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array
8051 USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array
8052 USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array
8053 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array.
8054}ATOM_MEMORY_TRAINING_INFO_V3_1;
8055
8056
Alex Deuchera02860aa2015-04-20 16:44:53 -04008057typedef struct SW_I2C_CNTL_DATA_PARAMETERS
8058{
8059 UCHAR ucControl;
8060 UCHAR ucData;
8061 UCHAR ucSatus;
8062 UCHAR ucTemp;
8063} SW_I2C_CNTL_DATA_PARAMETERS;
8064
8065#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
8066
8067typedef struct _SW_I2C_IO_DATA_PARAMETERS
8068{
8069 USHORT GPIO_Info;
8070 UCHAR ucAct;
8071 UCHAR ucData;
8072 } SW_I2C_IO_DATA_PARAMETERS;
8073
8074#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
8075
8076/****************************SW I2C CNTL DEFINITIONS**********************/
8077#define SW_I2C_IO_RESET 0
8078#define SW_I2C_IO_GET 1
8079#define SW_I2C_IO_DRIVE 2
8080#define SW_I2C_IO_SET 3
8081#define SW_I2C_IO_START 4
8082
8083#define SW_I2C_IO_CLOCK 0
8084#define SW_I2C_IO_DATA 0x80
8085
8086#define SW_I2C_IO_ZERO 0
8087#define SW_I2C_IO_ONE 0x100
8088
8089#define SW_I2C_CNTL_READ 0
8090#define SW_I2C_CNTL_WRITE 1
8091#define SW_I2C_CNTL_START 2
8092#define SW_I2C_CNTL_STOP 3
8093#define SW_I2C_CNTL_OPEN 4
8094#define SW_I2C_CNTL_CLOSE 5
8095#define SW_I2C_CNTL_WRITE1BIT 6
8096
8097//==============================VESA definition Portion===============================
8098#define VESA_OEM_PRODUCT_REV '01.00'
8099#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
8100#define VESA_MODE_WIN_ATTRIBUTE 7
8101#define VESA_WIN_SIZE 64
8102
8103typedef struct _PTR_32_BIT_STRUCTURE
8104{
8105 USHORT Offset16;
8106 USHORT Segment16;
8107} PTR_32_BIT_STRUCTURE;
8108
8109typedef union _PTR_32_BIT_UNION
8110{
8111 PTR_32_BIT_STRUCTURE SegmentOffset;
8112 ULONG Ptr32_Bit;
8113} PTR_32_BIT_UNION;
8114
8115typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
8116{
8117 UCHAR VbeSignature[4];
8118 USHORT VbeVersion;
8119 PTR_32_BIT_UNION OemStringPtr;
8120 UCHAR Capabilities[4];
8121 PTR_32_BIT_UNION VideoModePtr;
8122 USHORT TotalMemory;
8123} VBE_1_2_INFO_BLOCK_UPDATABLE;
8124
8125
8126typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
8127{
8128 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
8129 USHORT OemSoftRev;
8130 PTR_32_BIT_UNION OemVendorNamePtr;
8131 PTR_32_BIT_UNION OemProductNamePtr;
8132 PTR_32_BIT_UNION OemProductRevPtr;
8133} VBE_2_0_INFO_BLOCK_UPDATABLE;
8134
8135typedef union _VBE_VERSION_UNION
8136{
8137 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
8138 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
8139} VBE_VERSION_UNION;
8140
8141typedef struct _VBE_INFO_BLOCK
8142{
8143 VBE_VERSION_UNION UpdatableVBE_Info;
8144 UCHAR Reserved[222];
8145 UCHAR OemData[256];
8146} VBE_INFO_BLOCK;
8147
8148typedef struct _VBE_FP_INFO
8149{
8150 USHORT HSize;
8151 USHORT VSize;
8152 USHORT FPType;
8153 UCHAR RedBPP;
8154 UCHAR GreenBPP;
8155 UCHAR BlueBPP;
8156 UCHAR ReservedBPP;
8157 ULONG RsvdOffScrnMemSize;
8158 ULONG RsvdOffScrnMEmPtr;
8159 UCHAR Reserved[14];
8160} VBE_FP_INFO;
8161
8162typedef struct _VESA_MODE_INFO_BLOCK
8163{
8164// Mandatory information for all VBE revisions
8165 USHORT ModeAttributes; // dw ? ; mode attributes
8166 UCHAR WinAAttributes; // db ? ; window A attributes
8167 UCHAR WinBAttributes; // db ? ; window B attributes
8168 USHORT WinGranularity; // dw ? ; window granularity
8169 USHORT WinSize; // dw ? ; window size
8170 USHORT WinASegment; // dw ? ; window A start segment
8171 USHORT WinBSegment; // dw ? ; window B start segment
8172 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
8173 USHORT BytesPerScanLine;// dw ? ; bytes per scan line
8174
8175//; Mandatory information for VBE 1.2 and above
8176 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
8177 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
8178 UCHAR XCharSize; // db ? ; character cell width in pixels
8179 UCHAR YCharSize; // db ? ; character cell height in pixels
8180 UCHAR NumberOfPlanes; // db ? ; number of memory planes
8181 UCHAR BitsPerPixel; // db ? ; bits per pixel
8182 UCHAR NumberOfBanks; // db ? ; number of banks
8183 UCHAR MemoryModel; // db ? ; memory model type
8184 UCHAR BankSize; // db ? ; bank size in KB
8185 UCHAR NumberOfImagePages;// db ? ; number of images
8186 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
8187
8188//; Direct Color fields(required for direct/6 and YUV/7 memory models)
8189 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
8190 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
8191 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
8192 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
8193 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
8194 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
8195 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
8196 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
8197 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
8198
8199//; Mandatory information for VBE 2.0 and above
8200 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
8201 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8202 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8203
8204//; Mandatory information for VBE 3.0 and above
8205 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
8206 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
8207 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
8208 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
8209 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
8210 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
8211 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
8212 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
8213 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
8214 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
8215 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
8216 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
8217 UCHAR Reserved; // db 190 dup (0)
8218} VESA_MODE_INFO_BLOCK;
8219
8220// BIOS function CALLS
8221#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
8222#define ATOM_BIOS_FUNCTION_COP_MODE 0x00
8223#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
8224#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
8225#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
8226#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
8227#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
8228#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
8229#define ATOM_BIOS_FUNCTION_STV_STD 0x16
8230#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
8231#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
8232
8233#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
8234#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
8235#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
8236#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
8237#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
8238#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
8239#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
8240
8241#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
8242#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
8243#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
8244#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
8245#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
8246#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
8247#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
8248#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
8249#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
8250#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
8251
8252
8253#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
8254#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
8255#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
8256#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
8257#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
8258#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
8259#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
8260#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
8261
8262#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
8263#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
8264#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
8265
8266// structure used for VBIOS only
8267
8268//DispOutInfoTable
8269typedef struct _ASIC_TRANSMITTER_INFO
8270{
8271 USHORT usTransmitterObjId;
8272 USHORT usSupportDevice;
Alex Deucher6e14e92b2015-10-15 00:43:41 -04008273 UCHAR ucTransmitterCmdTblId;
Alex Deuchera02860aa2015-04-20 16:44:53 -04008274 UCHAR ucConfig;
8275 UCHAR ucEncoderID; //available 1st encoder ( default )
8276 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
8277 UCHAR uc2ndEncoderID;
8278 UCHAR ucReserved;
8279}ASIC_TRANSMITTER_INFO;
8280
8281#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01
8282#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02
8283#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4
8284#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00
8285#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04
8286#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40
8287#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44
8288#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80
8289#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84
8290
8291typedef struct _ASIC_ENCODER_INFO
8292{
8293 UCHAR ucEncoderID;
8294 UCHAR ucEncoderConfig;
8295 USHORT usEncoderCmdTblId;
8296}ASIC_ENCODER_INFO;
8297
8298typedef struct _ATOM_DISP_OUT_INFO
8299{
8300 ATOM_COMMON_TABLE_HEADER sHeader;
8301 USHORT ptrTransmitterInfo;
8302 USHORT ptrEncoderInfo;
8303 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
8304 ASIC_ENCODER_INFO asEncoderInfo[1];
8305}ATOM_DISP_OUT_INFO;
8306
8307
8308typedef struct _ATOM_DISP_OUT_INFO_V2
8309{
8310 ATOM_COMMON_TABLE_HEADER sHeader;
8311 USHORT ptrTransmitterInfo;
8312 USHORT ptrEncoderInfo;
8313 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
8314 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
8315 ASIC_ENCODER_INFO asEncoderInfo[1];
8316}ATOM_DISP_OUT_INFO_V2;
8317
8318
8319typedef struct _ATOM_DISP_CLOCK_ID {
8320 UCHAR ucPpllId;
8321 UCHAR ucPpllAttribute;
8322}ATOM_DISP_CLOCK_ID;
8323
8324// ucPpllAttribute
8325#define CLOCK_SOURCE_SHAREABLE 0x01
8326#define CLOCK_SOURCE_DP_MODE 0x02
8327#define CLOCK_SOURCE_NONE_DP_MODE 0x04
8328
8329//DispOutInfoTable
8330typedef struct _ASIC_TRANSMITTER_INFO_V2
8331{
8332 USHORT usTransmitterObjId;
8333 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object
8334 UCHAR ucTransmitterCmdTblId;
8335 UCHAR ucConfig;
8336 UCHAR ucEncoderID; // available 1st encoder ( default )
8337 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
8338 UCHAR uc2ndEncoderID;
8339 UCHAR ucReserved;
8340}ASIC_TRANSMITTER_INFO_V2;
8341
8342typedef struct _ATOM_DISP_OUT_INFO_V3
8343{
8344 ATOM_COMMON_TABLE_HEADER sHeader;
8345 USHORT ptrTransmitterInfo;
8346 USHORT ptrEncoderInfo;
8347 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
8348 USHORT usReserved;
8349 UCHAR ucDCERevision;
8350 UCHAR ucMaxDispEngineNum;
8351 UCHAR ucMaxActiveDispEngineNum;
8352 UCHAR ucMaxPPLLNum;
8353 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
8354 UCHAR ucDispCaps;
8355 UCHAR ucReserved[2];
8356 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
8357}ATOM_DISP_OUT_INFO_V3;
8358
8359//ucDispCaps
8360#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01
8361#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02
8362
8363typedef enum CORE_REF_CLK_SOURCE{
8364 CLOCK_SRC_XTALIN=0,
8365 CLOCK_SRC_XO_IN=1,
8366 CLOCK_SRC_XO_IN2=2,
8367}CORE_REF_CLK_SOURCE;
8368
8369// DispDevicePriorityInfo
8370typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
8371{
8372 ATOM_COMMON_TABLE_HEADER sHeader;
8373 USHORT asDevicePriority[16];
8374}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
8375
8376//ProcessAuxChannelTransactionTable
8377typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
8378{
8379 USHORT lpAuxRequest;
8380 USHORT lpDataOut;
8381 UCHAR ucChannelID;
8382 union
8383 {
8384 UCHAR ucReplyStatus;
8385 UCHAR ucDelay;
8386 };
8387 UCHAR ucDataOutLen;
8388 UCHAR ucReserved;
8389}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
8390
8391//ProcessAuxChannelTransactionTable
8392typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
8393{
8394 USHORT lpAuxRequest;
8395 USHORT lpDataOut;
8396 UCHAR ucChannelID;
8397 union
8398 {
8399 UCHAR ucReplyStatus;
8400 UCHAR ucDelay;
8401 };
8402 UCHAR ucDataOutLen;
8403 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
8404}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
8405
8406#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
8407
8408//GetSinkType
8409
8410typedef struct _DP_ENCODER_SERVICE_PARAMETERS
8411{
8412 USHORT ucLinkClock;
8413 union
8414 {
8415 UCHAR ucConfig; // for DP training command
8416 UCHAR ucI2cId; // use for GET_SINK_TYPE command
8417 };
8418 UCHAR ucAction;
8419 UCHAR ucStatus;
8420 UCHAR ucLaneNum;
8421 UCHAR ucReserved[2];
8422}DP_ENCODER_SERVICE_PARAMETERS;
8423
8424// ucAction
8425#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
8426
8427#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
8428
8429
8430typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
8431{
8432 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8433 UCHAR ucAuxId;
8434 UCHAR ucAction;
8435 UCHAR ucSinkType; // Iput and Output parameters.
8436 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8437 UCHAR ucReserved[2];
8438}DP_ENCODER_SERVICE_PARAMETERS_V2;
8439
8440typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
8441{
8442 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
8443 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
8444}DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
8445
8446// ucAction
8447#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01
8448#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02
8449
8450
8451// DP_TRAINING_TABLE
8452#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
8453#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
8454#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
8455#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
8456#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
8457#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
8458#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
8459#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
8460#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
8461#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
8462#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
8463#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
8464#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
8465
8466
8467typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
8468{
8469 UCHAR ucI2CSpeed;
8470 union
8471 {
8472 UCHAR ucRegIndex;
8473 UCHAR ucStatus;
8474 };
8475 USHORT lpI2CDataOut;
8476 UCHAR ucFlag;
8477 UCHAR ucTransBytes;
8478 UCHAR ucSlaveAddr;
8479 UCHAR ucLineNumber;
8480}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
8481
8482#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
8483
8484//ucFlag
8485#define HW_I2C_WRITE 1
8486#define HW_I2C_READ 0
8487#define I2C_2BYTE_ADDR 0x02
8488
8489/****************************************************************************/
8490// Structures used by HW_Misc_OperationTable
8491/****************************************************************************/
8492typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
8493{
8494 UCHAR ucCmd; // Input: To tell which action to take
8495 UCHAR ucReserved[3];
8496 ULONG ulReserved;
8497}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
8498
8499typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
8500{
8501 UCHAR ucReturnCode; // Output: Return value base on action was taken
8502 UCHAR ucReserved[3];
8503 ULONG ulReserved;
8504}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
8505
8506// Actions code
8507#define ATOM_GET_SDI_SUPPORT 0xF0
8508
8509// Return code
8510#define ATOM_UNKNOWN_CMD 0
8511#define ATOM_FEATURE_NOT_SUPPORTED 1
8512#define ATOM_FEATURE_SUPPORTED 2
8513
8514typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
8515{
8516 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output;
8517 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved;
8518}ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
8519
8520/****************************************************************************/
8521
8522typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
8523{
8524 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
8525 UCHAR ucReserved[3];
8526}SET_HWBLOCK_INSTANCE_PARAMETER_V2;
8527
8528#define HWBLKINST_INSTANCE_MASK 0x07
8529#define HWBLKINST_HWBLK_MASK 0xF0
8530#define HWBLKINST_HWBLK_SHIFT 0x04
8531
8532//ucHWBlock
8533#define SELECT_DISP_ENGINE 0
8534#define SELECT_DISP_PLL 1
8535#define SELECT_DCIO_UNIPHY_LINK0 2
8536#define SELECT_DCIO_UNIPHY_LINK1 3
8537#define SELECT_DCIO_IMPCAL 4
8538#define SELECT_DCIO_DIG 6
8539#define SELECT_CRTC_PIXEL_RATE 7
8540#define SELECT_VGA_BLK 8
8541
8542// DIGTransmitterInfoTable structure used to program UNIPHY settings
8543typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
8544 ATOM_COMMON_TABLE_HEADER sHeader;
8545 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8546 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8547 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8548 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8549 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8550}DIG_TRANSMITTER_INFO_HEADER_V3_1;
8551
8552typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{
8553 ATOM_COMMON_TABLE_HEADER sHeader;
8554 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8555 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8556 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8557 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8558 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8559 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
8560 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8561}DIG_TRANSMITTER_INFO_HEADER_V3_2;
8562
8563
8564typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{
8565 ATOM_COMMON_TABLE_HEADER sHeader;
8566 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8567 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8568 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8569 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8570 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8571 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
8572 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8573 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock
8574 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8575 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8576 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock
8577 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8578 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock
8579}DIG_TRANSMITTER_INFO_HEADER_V3_3;
8580
8581
8582typedef struct _CLOCK_CONDITION_REGESTER_INFO{
8583 USHORT usRegisterIndex;
8584 UCHAR ucStartBit;
8585 UCHAR ucEndBit;
8586}CLOCK_CONDITION_REGESTER_INFO;
8587
8588typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
8589 USHORT usMaxClockFreq;
8590 UCHAR ucEncodeMode;
8591 UCHAR ucPhySel;
8592 ULONG ulAnalogSetting[1];
8593}CLOCK_CONDITION_SETTING_ENTRY;
8594
8595typedef struct _CLOCK_CONDITION_SETTING_INFO{
8596 USHORT usEntrySize;
8597 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
8598}CLOCK_CONDITION_SETTING_INFO;
8599
8600typedef struct _PHY_CONDITION_REG_VAL{
8601 ULONG ulCondition;
8602 ULONG ulRegVal;
8603}PHY_CONDITION_REG_VAL;
8604
8605typedef struct _PHY_CONDITION_REG_VAL_V2{
8606 ULONG ulCondition;
8607 UCHAR ucCondition2;
8608 ULONG ulRegVal;
8609}PHY_CONDITION_REG_VAL_V2;
8610
8611typedef struct _PHY_CONDITION_REG_INFO{
8612 USHORT usRegIndex;
8613 USHORT usSize;
8614 PHY_CONDITION_REG_VAL asRegVal[1];
8615}PHY_CONDITION_REG_INFO;
8616
8617typedef struct _PHY_CONDITION_REG_INFO_V2{
8618 USHORT usRegIndex;
8619 USHORT usSize;
8620 PHY_CONDITION_REG_VAL_V2 asRegVal[1];
8621}PHY_CONDITION_REG_INFO_V2;
8622
8623typedef struct _PHY_ANALOG_SETTING_INFO{
8624 UCHAR ucEncodeMode;
8625 UCHAR ucPhySel;
8626 USHORT usSize;
8627 PHY_CONDITION_REG_INFO asAnalogSetting[1];
8628}PHY_ANALOG_SETTING_INFO;
8629
8630typedef struct _PHY_ANALOG_SETTING_INFO_V2{
8631 UCHAR ucEncodeMode;
8632 UCHAR ucPhySel;
8633 USHORT usSize;
8634 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1];
8635}PHY_ANALOG_SETTING_INFO_V2;
8636
8637
8638typedef struct _GFX_HAVESTING_PARAMETERS {
8639 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
8640 UCHAR ucReserved; //reserved
8641 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
8642 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
8643} GFX_HAVESTING_PARAMETERS;
8644
8645//ucGfxBlkId
8646#define GFX_HARVESTING_CU_ID 0
8647#define GFX_HARVESTING_RB_ID 1
8648#define GFX_HARVESTING_PRIM_ID 2
8649
8650
8651typedef struct _VBIOS_ROM_HEADER{
8652 UCHAR PciRomSignature[2];
8653 UCHAR ucPciRomSizeIn512bytes;
8654 UCHAR ucJumpCoreMainInitBIOS;
8655 USHORT usLabelCoreMainInitBIOS;
8656 UCHAR PciReservedSpace[18];
8657 USHORT usPciDataStructureOffset;
8658 UCHAR Rsvd1d_1a[4];
8659 char strIbm[3];
8660 UCHAR CheckSum[14];
8661 UCHAR ucBiosMsgNumber;
8662 char str761295520[16];
8663 USHORT usLabelCoreVPOSTNoMode;
8664 USHORT usSpecialPostOffset;
8665 UCHAR ucSpeicalPostImageSizeIn512Bytes;
8666 UCHAR Rsved47_45[3];
8667 USHORT usROM_HeaderInformationTableOffset;
8668 UCHAR Rsved4f_4a[6];
8669 char strBuildTimeStamp[20];
8670 UCHAR ucJumpCoreXFuncFarHandler;
8671 USHORT usCoreXFuncFarHandlerOffset;
8672 UCHAR ucRsved67;
8673 UCHAR ucJumpCoreVFuncFarHandler;
8674 USHORT usCoreVFuncFarHandlerOffset;
8675 UCHAR Rsved6d_6b[3];
8676 USHORT usATOM_BIOS_MESSAGE_Offset;
8677}VBIOS_ROM_HEADER;
8678
8679/****************************************************************************/
8680//Portion VI: Definitinos for vbios MC scratch registers that driver used
8681/****************************************************************************/
8682
8683#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
8684#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
8685#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
8686#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
8687#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
8688#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
8689#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000
8690#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
8691
8692#define ATOM_MEM_TYPE_DDR_STRING "DDR"
8693#define ATOM_MEM_TYPE_DDR2_STRING "DDR2"
8694#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3"
8695#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4"
8696#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5"
8697#define ATOM_MEM_TYPE_HBM_STRING "HBM"
8698#define ATOM_MEM_TYPE_DDR3_STRING "DDR3"
8699
8700/****************************************************************************/
8701//Portion VII: Definitinos being oboselete
8702/****************************************************************************/
8703
8704//==========================================================================================
8705//Remove the definitions below when driver is ready!
8706typedef struct _ATOM_DAC_INFO
8707{
8708 ATOM_COMMON_TABLE_HEADER sHeader;
8709 USHORT usMaxFrequency; // in 10kHz unit
8710 USHORT usReserved;
8711}ATOM_DAC_INFO;
8712
8713
8714typedef struct _COMPASSIONATE_DATA
8715{
8716 ATOM_COMMON_TABLE_HEADER sHeader;
8717
8718 //============================== DAC1 portion
8719 UCHAR ucDAC1_BG_Adjustment;
8720 UCHAR ucDAC1_DAC_Adjustment;
8721 USHORT usDAC1_FORCE_Data;
8722 //============================== DAC2 portion
8723 UCHAR ucDAC2_CRT2_BG_Adjustment;
8724 UCHAR ucDAC2_CRT2_DAC_Adjustment;
8725 USHORT usDAC2_CRT2_FORCE_Data;
8726 USHORT usDAC2_CRT2_MUX_RegisterIndex;
8727 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8728 UCHAR ucDAC2_NTSC_BG_Adjustment;
8729 UCHAR ucDAC2_NTSC_DAC_Adjustment;
8730 USHORT usDAC2_TV1_FORCE_Data;
8731 USHORT usDAC2_TV1_MUX_RegisterIndex;
8732 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8733 UCHAR ucDAC2_CV_BG_Adjustment;
8734 UCHAR ucDAC2_CV_DAC_Adjustment;
8735 USHORT usDAC2_CV_FORCE_Data;
8736 USHORT usDAC2_CV_MUX_RegisterIndex;
8737 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8738 UCHAR ucDAC2_PAL_BG_Adjustment;
8739 UCHAR ucDAC2_PAL_DAC_Adjustment;
8740 USHORT usDAC2_TV2_FORCE_Data;
8741}COMPASSIONATE_DATA;
8742
8743/****************************Supported Device Info Table Definitions**********************/
8744// ucConnectInfo:
8745// [7:4] - connector type
8746// = 1 - VGA connector
8747// = 2 - DVI-I
8748// = 3 - DVI-D
8749// = 4 - DVI-A
8750// = 5 - SVIDEO
8751// = 6 - COMPOSITE
8752// = 7 - LVDS
8753// = 8 - DIGITAL LINK
8754// = 9 - SCART
8755// = 0xA - HDMI_type A
8756// = 0xB - HDMI_type B
8757// = 0xE - Special case1 (DVI+DIN)
8758// Others=TBD
8759// [3:0] - DAC Associated
8760// = 0 - no DAC
8761// = 1 - DACA
8762// = 2 - DACB
8763// = 3 - External DAC
8764// Others=TBD
8765//
8766
8767typedef struct _ATOM_CONNECTOR_INFO
8768{
8769#if ATOM_BIG_ENDIAN
8770 UCHAR bfConnectorType:4;
8771 UCHAR bfAssociatedDAC:4;
8772#else
8773 UCHAR bfAssociatedDAC:4;
8774 UCHAR bfConnectorType:4;
8775#endif
8776}ATOM_CONNECTOR_INFO;
8777
8778typedef union _ATOM_CONNECTOR_INFO_ACCESS
8779{
8780 ATOM_CONNECTOR_INFO sbfAccess;
8781 UCHAR ucAccess;
8782}ATOM_CONNECTOR_INFO_ACCESS;
8783
8784typedef struct _ATOM_CONNECTOR_INFO_I2C
8785{
8786 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
8787 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
8788}ATOM_CONNECTOR_INFO_I2C;
8789
8790
8791typedef struct _ATOM_SUPPORTED_DEVICES_INFO
8792{
8793 ATOM_COMMON_TABLE_HEADER sHeader;
8794 USHORT usDeviceSupport;
8795 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
8796}ATOM_SUPPORTED_DEVICES_INFO;
8797
8798#define NO_INT_SRC_MAPPED 0xFF
8799
8800typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
8801{
8802 UCHAR ucIntSrcBitmap;
8803}ATOM_CONNECTOR_INC_SRC_BITMAP;
8804
8805typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
8806{
8807 ATOM_COMMON_TABLE_HEADER sHeader;
8808 USHORT usDeviceSupport;
8809 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
8810 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
8811}ATOM_SUPPORTED_DEVICES_INFO_2;
8812
8813typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
8814{
8815 ATOM_COMMON_TABLE_HEADER sHeader;
8816 USHORT usDeviceSupport;
8817 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
8818 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
8819}ATOM_SUPPORTED_DEVICES_INFO_2d1;
8820
8821#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
8822
8823
8824
8825typedef struct _ATOM_MISC_CONTROL_INFO
8826{
8827 USHORT usFrequency;
8828 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8829 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
8830 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
8831 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
8832}ATOM_MISC_CONTROL_INFO;
8833
8834
8835#define ATOM_MAX_MISC_INFO 4
8836
8837typedef struct _ATOM_TMDS_INFO
8838{
8839 ATOM_COMMON_TABLE_HEADER sHeader;
8840 USHORT usMaxFrequency; // in 10Khz
8841 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
8842}ATOM_TMDS_INFO;
8843
8844
8845typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
8846{
8847 UCHAR ucTVStandard; //Same as TV standards defined above,
8848 UCHAR ucPadding[1];
8849}ATOM_ENCODER_ANALOG_ATTRIBUTE;
8850
8851typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
8852{
8853 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
8854 UCHAR ucPadding[1];
8855}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
8856
8857typedef union _ATOM_ENCODER_ATTRIBUTE
8858{
8859 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
8860 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
8861}ATOM_ENCODER_ATTRIBUTE;
8862
8863
8864typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
8865{
8866 USHORT usPixelClock;
8867 USHORT usEncoderID;
8868 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
8869 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
8870 ATOM_ENCODER_ATTRIBUTE usDevAttr;
8871}DVO_ENCODER_CONTROL_PARAMETERS;
8872
8873typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
8874{
8875 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
8876 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
8877}DVO_ENCODER_CONTROL_PS_ALLOCATION;
8878
8879
8880#define ATOM_XTMDS_ASIC_SI164_ID 1
8881#define ATOM_XTMDS_ASIC_SI178_ID 2
8882#define ATOM_XTMDS_ASIC_TFP513_ID 3
8883#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
8884#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
8885#define ATOM_XTMDS_MVPU_FPGA 0x00000004
8886
8887
8888typedef struct _ATOM_XTMDS_INFO
8889{
8890 ATOM_COMMON_TABLE_HEADER sHeader;
8891 USHORT usSingleLinkMaxFrequency;
8892 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
8893 UCHAR ucXtransimitterID;
8894 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
8895 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
8896 // due to design. This ID is used to alert driver that the sequence is not "standard"!
8897 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
8898 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
8899}ATOM_XTMDS_INFO;
8900
8901typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
8902{
8903 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
8904 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
8905 UCHAR ucPadding[2];
8906}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
8907
8908/****************************Legacy Power Play Table Definitions **********************/
8909
8910//Definitions for ulPowerPlayMiscInfo
8911#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
8912#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
8913#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
8914
8915#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
8916#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
8917
8918#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
8919
8920#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
8921#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
8922#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
8923
8924#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
8925#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
8926#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
8927#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
8928#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
8929#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
8930#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
8931
8932#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
8933#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
8934#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
8935#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
8936#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
8937
8938#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
8939#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
8940
8941#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
8942#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
8943#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
8944#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
8945#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
8946#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
8947
8948#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
8949#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
8950#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
8951
8952#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
8953#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
8954#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
8955#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
8956#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
8957#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
8958#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
8959 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
8960#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
8961#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
8962#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
8963
8964//ucTableFormatRevision=1
8965//ucTableContentRevision=1
8966typedef struct _ATOM_POWERMODE_INFO
8967{
8968 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8969 ULONG ulReserved1; // must set to 0
8970 ULONG ulReserved2; // must set to 0
8971 USHORT usEngineClock;
8972 USHORT usMemoryClock;
8973 UCHAR ucVoltageDropIndex; // index to GPIO table
8974 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8975 UCHAR ucMinTemperature;
8976 UCHAR ucMaxTemperature;
8977 UCHAR ucNumPciELanes; // number of PCIE lanes
8978}ATOM_POWERMODE_INFO;
8979
8980//ucTableFormatRevision=2
8981//ucTableContentRevision=1
8982typedef struct _ATOM_POWERMODE_INFO_V2
8983{
8984 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8985 ULONG ulMiscInfo2;
8986 ULONG ulEngineClock;
8987 ULONG ulMemoryClock;
8988 UCHAR ucVoltageDropIndex; // index to GPIO table
8989 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8990 UCHAR ucMinTemperature;
8991 UCHAR ucMaxTemperature;
8992 UCHAR ucNumPciELanes; // number of PCIE lanes
8993}ATOM_POWERMODE_INFO_V2;
8994
8995//ucTableFormatRevision=2
8996//ucTableContentRevision=2
8997typedef struct _ATOM_POWERMODE_INFO_V3
8998{
8999 ULONG ulMiscInfo; //The power level should be arranged in ascending order
9000 ULONG ulMiscInfo2;
9001 ULONG ulEngineClock;
9002 ULONG ulMemoryClock;
9003 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
9004 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9005 UCHAR ucMinTemperature;
9006 UCHAR ucMaxTemperature;
9007 UCHAR ucNumPciELanes; // number of PCIE lanes
9008 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
9009}ATOM_POWERMODE_INFO_V3;
9010
9011
9012#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
9013
9014#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
9015#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
9016
9017#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
9018#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
9019#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
9020#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
9021#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
9022#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
9023#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
9024
9025
9026typedef struct _ATOM_POWERPLAY_INFO
9027{
9028 ATOM_COMMON_TABLE_HEADER sHeader;
9029 UCHAR ucOverdriveThermalController;
9030 UCHAR ucOverdriveI2cLine;
9031 UCHAR ucOverdriveIntBitmap;
9032 UCHAR ucOverdriveControllerAddress;
9033 UCHAR ucSizeOfPowerModeEntry;
9034 UCHAR ucNumOfPowerModeEntries;
9035 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
9036}ATOM_POWERPLAY_INFO;
9037
9038typedef struct _ATOM_POWERPLAY_INFO_V2
9039{
9040 ATOM_COMMON_TABLE_HEADER sHeader;
9041 UCHAR ucOverdriveThermalController;
9042 UCHAR ucOverdriveI2cLine;
9043 UCHAR ucOverdriveIntBitmap;
9044 UCHAR ucOverdriveControllerAddress;
9045 UCHAR ucSizeOfPowerModeEntry;
9046 UCHAR ucNumOfPowerModeEntries;
9047 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
9048}ATOM_POWERPLAY_INFO_V2;
9049
9050typedef struct _ATOM_POWERPLAY_INFO_V3
9051{
9052 ATOM_COMMON_TABLE_HEADER sHeader;
9053 UCHAR ucOverdriveThermalController;
9054 UCHAR ucOverdriveI2cLine;
9055 UCHAR ucOverdriveIntBitmap;
9056 UCHAR ucOverdriveControllerAddress;
9057 UCHAR ucSizeOfPowerModeEntry;
9058 UCHAR ucNumOfPowerModeEntries;
9059 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
9060}ATOM_POWERPLAY_INFO_V3;
9061
9062
9063
9064/**************************************************************************/
9065
9066
9067// Following definitions are for compatiblity issue in different SW components.
9068#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
9069#define Object_Info Object_Header
9070#define AdjustARB_SEQ MC_InitParameter
9071#define VRAM_GPIO_DetectionInfo VoltageObjectInfo
9072#define ASIC_VDDCI_Info ASIC_ProfilingInfo
9073#define ASIC_MVDDQ_Info MemoryTrainingInfo
9074#define SS_Info PPLL_SS_Info
9075#define ASIC_MVDDC_Info ASIC_InternalSS_Info
9076#define DispDevicePriorityInfo SaveRestoreInfo
9077#define DispOutInfo TV_VideoMode
9078
9079
9080#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
9081#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
9082
9083//New device naming, remove them when both DAL/VBIOS is ready
9084#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
9085#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
9086
9087#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
9088#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
9089
9090#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
9091#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
9092
9093#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
9094#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
9095
9096#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
9097#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
9098
9099#define ATOM_DEVICE_DFP2I_INDEX 0x00000009
9100#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
9101
9102#define ATOM_S0_DFP1I ATOM_S0_DFP1
9103#define ATOM_S0_DFP1X ATOM_S0_DFP2
9104
9105#define ATOM_S0_DFP2I 0x00200000L
9106#define ATOM_S0_DFP2Ib2 0x20
9107
9108#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
9109#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
9110
9111#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
9112#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
9113
9114#define ATOM_S3_DFP2I_ACTIVEb1 0x02
9115
9116#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
9117#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
9118
9119#define ATOM_S3_DFP2I_ACTIVE 0x00000200L
9120
9121#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
9122#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
9123#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
9124
9125
9126#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
9127#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
9128
9129#define ATOM_S5_DOS_REQ_DFP2I 0x0200
9130#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
9131#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
9132
9133#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
9134#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
9135
9136#define TMDS1XEncoderControl DVOEncoderControl
9137#define DFP1XOutputControl DVOOutputControl
9138
9139#define ExternalDFPOutputControl DFP1XOutputControl
9140#define EnableExternalTMDS_Encoder TMDS1XEncoderControl
9141
9142#define DFP1IOutputControl TMDSAOutputControl
9143#define DFP2IOutputControl LVTMAOutputControl
9144
9145#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
9146#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
9147
9148#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
9149#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
9150
9151#define ucDac1Standard ucDacStandard
9152#define ucDac2Standard ucDacStandard
9153
9154#define TMDS1EncoderControl TMDSAEncoderControl
9155#define TMDS2EncoderControl LVTMAEncoderControl
9156
9157#define DFP1OutputControl TMDSAOutputControl
9158#define DFP2OutputControl LVTMAOutputControl
9159#define CRT1OutputControl DAC1OutputControl
9160#define CRT2OutputControl DAC2OutputControl
9161
9162//These two lines will be removed for sure in a few days, will follow up with Michael V.
9163#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
9164#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
9165
9166#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
9167#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9168#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9169#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9170#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9171
9172#define ATOM_S6_ACC_REQ_TV2 0x00400000L
9173#define ATOM_DEVICE_TV2_INDEX 0x00000006
9174#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
9175#define ATOM_S0_TV2 0x00100000L
9176#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
9177#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
9178
9179/*********************************************************************************/
9180
9181#pragma pack() // BIOS data must use byte aligment
9182
9183#pragma pack(1)
9184
9185typedef struct _ATOM_HOLE_INFO
9186{
9187 USHORT usOffset; // offset of the hole ( from the start of the binary )
9188 USHORT usLength; // length of the hole ( in bytes )
9189}ATOM_HOLE_INFO;
9190
9191typedef struct _ATOM_SERVICE_DESCRIPTION
9192{
9193 UCHAR ucRevision; // Holes set revision
9194 UCHAR ucAlgorithm; // Hash algorithm
9195 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9196 UCHAR ucReserved;
9197 USHORT usSigOffset; // Signature offset ( from the start of the binary )
9198 USHORT usSigLength; // Signature length
9199}ATOM_SERVICE_DESCRIPTION;
9200
9201
9202typedef struct _ATOM_SERVICE_INFO
9203{
9204 ATOM_COMMON_TABLE_HEADER asHeader;
9205 ATOM_SERVICE_DESCRIPTION asDescr;
9206 UCHAR ucholesNo; // number of holes that follow
9207 ATOM_HOLE_INFO holes[1]; // array of hole descriptions
9208}ATOM_SERVICE_INFO;
9209
9210
9211
9212#pragma pack() // BIOS data must use byte aligment
9213
9214//
9215// AMD ACPI Table
9216//
9217#pragma pack(1)
9218
9219typedef struct {
9220 ULONG Signature;
9221 ULONG TableLength; //Length
9222 UCHAR Revision;
9223 UCHAR Checksum;
9224 UCHAR OemId[6];
9225 UCHAR OemTableId[8]; //UINT64 OemTableId;
9226 ULONG OemRevision;
9227 ULONG CreatorId;
9228 ULONG CreatorRevision;
9229} AMD_ACPI_DESCRIPTION_HEADER;
9230/*
9231//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
9232typedef struct {
9233 UINT32 Signature; //0x0
9234 UINT32 Length; //0x4
9235 UINT8 Revision; //0x8
9236 UINT8 Checksum; //0x9
9237 UINT8 OemId[6]; //0xA
9238 UINT64 OemTableId; //0x10
9239 UINT32 OemRevision; //0x18
9240 UINT32 CreatorId; //0x1C
9241 UINT32 CreatorRevision; //0x20
9242}EFI_ACPI_DESCRIPTION_HEADER;
9243*/
9244typedef struct {
9245 AMD_ACPI_DESCRIPTION_HEADER SHeader;
9246 UCHAR TableUUID[16]; //0x24
9247 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
9248 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
9249 ULONG Reserved[4]; //0x3C
9250}UEFI_ACPI_VFCT;
9251
9252typedef struct {
9253 ULONG PCIBus; //0x4C
9254 ULONG PCIDevice; //0x50
9255 ULONG PCIFunction; //0x54
9256 USHORT VendorID; //0x58
9257 USHORT DeviceID; //0x5A
9258 USHORT SSVID; //0x5C
9259 USHORT SSID; //0x5E
9260 ULONG Revision; //0x60
9261 ULONG ImageLength; //0x64
9262}VFCT_IMAGE_HEADER;
9263
9264
9265typedef struct {
9266 VFCT_IMAGE_HEADER VbiosHeader;
9267 UCHAR VbiosContent[1];
9268}GOP_VBIOS_CONTENT;
9269
9270typedef struct {
9271 VFCT_IMAGE_HEADER Lib1Header;
9272 UCHAR Lib1Content[1];
9273}GOP_LIB1_CONTENT;
9274
9275#pragma pack()
9276
9277
9278#endif /* _ATOMBIOS_H */
9279
9280#include "pptable.h"
9281