Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf527/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ |
| 8 | |
| 9 | /* This file shoule be up to date with: |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 10 | * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List |
| 11 | * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #ifndef _MACH_ANOMALY_H_ |
| 15 | #define _MACH_ANOMALY_H_ |
| 16 | |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 17 | #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) |
| 18 | # define ANOMALY_BF526 1 |
| 19 | #else |
| 20 | # define ANOMALY_BF526 0 |
| 21 | #endif |
| 22 | #if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) |
| 23 | # define ANOMALY_BF527 1 |
| 24 | #else |
| 25 | # define ANOMALY_BF527 0 |
| 26 | #endif |
| 27 | |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 28 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 29 | #define ANOMALY_05000074 (1) |
Mike Frysinger | a70ce07 | 2008-05-31 15:47:17 +0800 | [diff] [blame] | 30 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
Mike Frysinger | 3529e04 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 31 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 32 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 33 | #define ANOMALY_05000122 (1) |
| 34 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 35 | #define ANOMALY_05000245 (1) |
| 36 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 37 | #define ANOMALY_05000265 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 38 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 39 | #define ANOMALY_05000310 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 40 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 41 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 43 | #define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 44 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 45 | #define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 46 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 47 | #define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 48 | /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 49 | #define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 50 | /* USB Calibration Value Is Not Initialized */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 51 | #define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Robin Getz | 202d7bd | 2008-10-09 11:59:46 +0800 | [diff] [blame] | 52 | /* USB Calibration Value to use */ |
| 53 | #define ANOMALY_05000346_value 0xE510 |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 54 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 55 | #define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 56 | /* Security Features Are Not Functional */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 57 | #define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) |
| 58 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
| 59 | #define ANOMALY_05000353 (ANOMALY_BF526) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 60 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 61 | #define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 62 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 63 | #define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 64 | /* Incorrect Revision Number in DSPID Register */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 65 | #define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 66 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ |
| 67 | #define ANOMALY_05000366 (1) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 68 | /* Incorrect Default CSEL Value in PLL_DIV */ |
| 69 | #define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 70 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 71 | #define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 72 | /* Authentication Fails To Initiate */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 73 | #define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 74 | /* Data Read From L3 Memory by USB DMA May be Corrupted */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 75 | #define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 76 | /* 8-Bit NAND Flash Boot Mode Not Functional */ |
| 77 | #define ANOMALY_05000382 (__SILICON_REVISION__ < 2) |
| 78 | /* Host Must Not Read Back During Host DMA Boot */ |
| 79 | #define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 80 | /* Boot from OTP Memory Not Functional */ |
| 81 | #define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 82 | /* bfrom_SysControl() Firmware Routine Not Functional */ |
| 83 | #define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 84 | /* Programmable Preboot Settings Not Functional */ |
| 85 | #define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 86 | /* CRC32 Checksum Support Not Functional */ |
| 87 | #define ANOMALY_05000388 (__SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 88 | /* Reset Vector Must Not Be in SDRAM Memory Space */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 89 | #define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 90 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ |
| 91 | #define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 92 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ |
| 93 | #define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 94 | /* Log Buffer Not Functional */ |
| 95 | #define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 96 | /* Hook Routine Not Functional */ |
| 97 | #define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 98 | /* Header Indirect Bit Not Functional */ |
| 99 | #define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 100 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ |
| 101 | #define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 102 | /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ |
| 103 | #define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 104 | /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ |
| 105 | #define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 106 | /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 107 | #define ANOMALY_05000401 (__SILICON_REVISION__ < 2) |
| 108 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
| 109 | #define ANOMALY_05000403 (__SILICON_REVISION__ < 2) |
| 110 | /* Lockbox SESR Disallows Certain User Interrupts */ |
| 111 | #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) |
| 112 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ |
| 113 | #define ANOMALY_05000405 (1) |
| 114 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ |
| 115 | #define ANOMALY_05000407 (__SILICON_REVISION__ < 2) |
| 116 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ |
| 117 | #define ANOMALY_05000408 (1) |
| 118 | /* Lockbox firmware leaves MDMA0 channel enabled */ |
| 119 | #define ANOMALY_05000409 (__SILICON_REVISION__ < 2) |
| 120 | /* Incorrect Default Internal Voltage Regulator Setting */ |
| 121 | #define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 122 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ |
| 123 | #define ANOMALY_05000411 (__SILICON_REVISION__ < 2) |
| 124 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ |
| 125 | #define ANOMALY_05000414 (__SILICON_REVISION__ < 2) |
| 126 | /* DEB2_URGENT Bit Not Functional */ |
| 127 | #define ANOMALY_05000415 (__SILICON_REVISION__ < 2) |
| 128 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ |
| 129 | #define ANOMALY_05000416 (1) |
| 130 | /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ |
| 131 | #define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 132 | /* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ |
| 133 | #define ANOMALY_05000418 (__SILICON_REVISION__ < 2) |
| 134 | /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ |
| 135 | #define ANOMALY_05000420 (__SILICON_REVISION__ < 2) |
| 136 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ |
| 137 | #define ANOMALY_05000421 (1) |
| 138 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ |
| 139 | #define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) |
| 140 | /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ |
| 141 | #define ANOMALY_05000423 (__SILICON_REVISION__ < 2) |
| 142 | /* Internal Voltage Regulator Not Trimmed */ |
| 143 | #define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) |
| 144 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ |
| 145 | #define ANOMALY_05000425 (__SILICON_REVISION__ < 2) |
| 146 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ |
| 147 | #define ANOMALY_05000426 (1) |
| 148 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ |
| 149 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) |
| 150 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 151 | #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) |
| 152 | /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ |
| 153 | #define ANOMALY_05000432 (ANOMALY_BF526) |
Mike Frysinger | 94b2821 | 2008-11-18 17:48:21 +0800 | [diff] [blame^] | 154 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ |
| 155 | #define ANOMALY_05000435 (ANOMALY_BF526 && __SILICON_REVISION__ < 1 || ANOMALY_BF527) |
Mike Frysinger | 3529e04 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 156 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 157 | #define ANOMALY_05000443 (1) |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 158 | |
Michael Hennerich | 2b39331 | 2007-10-10 16:58:49 +0800 | [diff] [blame] | 159 | /* Anomalies that don't exist on this proc */ |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 160 | #define ANOMALY_05000125 (0) |
| 161 | #define ANOMALY_05000158 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 162 | #define ANOMALY_05000183 (0) |
| 163 | #define ANOMALY_05000198 (0) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 164 | #define ANOMALY_05000230 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 165 | #define ANOMALY_05000244 (0) |
| 166 | #define ANOMALY_05000261 (0) |
| 167 | #define ANOMALY_05000263 (0) |
| 168 | #define ANOMALY_05000266 (0) |
| 169 | #define ANOMALY_05000273 (0) |
Mike Frysinger | 4e8086d | 2008-10-10 21:07:55 +0800 | [diff] [blame] | 170 | #define ANOMALY_05000285 (0) |
| 171 | #define ANOMALY_05000307 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 172 | #define ANOMALY_05000311 (0) |
Mike Frysinger | 3529e04 | 2008-10-28 16:22:41 +0800 | [diff] [blame] | 173 | #define ANOMALY_05000312 (0) |
Sonic Zhang | 4d55563 | 2008-04-25 03:28:10 +0800 | [diff] [blame] | 174 | #define ANOMALY_05000323 (0) |
| 175 | #define ANOMALY_05000363 (0) |
| 176 | |
Mike Frysinger | bc8c84c | 2007-08-05 17:32:25 +0800 | [diff] [blame] | 177 | #endif |