blob: a11b6e7b47595eb22a17a4c4d293b7614478e156 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -06005
6/ {
7 model = "NVIDIA Seaboard";
8 compatible = "nvidia,seaboard", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
Grant Likely8e267f32011-07-19 17:26:54 -060015 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060016 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060017 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -070019 host1x@50000000 {
20 hdmi@54280000 {
Stephen Warrena75191e2013-01-02 14:53:20 -070021 status = "okay";
22
23 vdd-supply = <&hdmi_vdd_reg>;
24 pll-supply = <&hdmi_pll_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070027 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
28 GPIO_ACTIVE_HIGH>;
Stephen Warrena75191e2013-01-02 14:53:20 -070029 };
30 };
31
Stephen Warren58ecb232013-11-25 17:53:16 -070032 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060033 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 ata {
38 nvidia,pins = "ata";
39 nvidia,function = "ide";
40 };
41 atb {
42 nvidia,pins = "atb", "gma", "gme";
43 nvidia,function = "sdio4";
44 };
45 atc {
46 nvidia,pins = "atc";
47 nvidia,function = "nand";
48 };
49 atd {
50 nvidia,pins = "atd", "ate", "gmb", "spia",
51 "spib", "spic";
52 nvidia,function = "gmi";
53 };
54 cdev1 {
55 nvidia,pins = "cdev1";
56 nvidia,function = "plla_out";
57 };
58 cdev2 {
59 nvidia,pins = "cdev2";
60 nvidia,function = "pllp_out4";
61 };
62 crtp {
63 nvidia,pins = "crtp", "lm1";
64 nvidia,function = "crt";
65 };
66 csus {
67 nvidia,pins = "csus";
68 nvidia,function = "vi_sensor_clk";
69 };
70 dap1 {
71 nvidia,pins = "dap1";
72 nvidia,function = "dap1";
73 };
74 dap2 {
75 nvidia,pins = "dap2";
76 nvidia,function = "dap2";
77 };
78 dap3 {
79 nvidia,pins = "dap3";
80 nvidia,function = "dap3";
81 };
82 dap4 {
83 nvidia,pins = "dap4";
84 nvidia,function = "dap4";
85 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060086 dta {
87 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
88 nvidia,function = "vi";
89 };
90 dtf {
91 nvidia,pins = "dtf";
92 nvidia,function = "i2c3";
93 };
94 gmc {
95 nvidia,pins = "gmc";
96 nvidia,function = "uartd";
97 };
98 gmd {
99 nvidia,pins = "gmd";
100 nvidia,function = "sflash";
101 };
102 gpu {
103 nvidia,pins = "gpu";
104 nvidia,function = "pwm";
105 };
106 gpu7 {
107 nvidia,pins = "gpu7";
108 nvidia,function = "rtck";
109 };
110 gpv {
111 nvidia,pins = "gpv", "slxa", "slxk";
112 nvidia,function = "pcie";
113 };
114 hdint {
115 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
Stephen Warren802a8492012-04-26 11:21:54 -0600116 "lsck", "lsda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600117 nvidia,function = "hdmi";
118 };
119 i2cp {
120 nvidia,pins = "i2cp";
121 nvidia,function = "i2cp";
122 };
123 irrx {
124 nvidia,pins = "irrx", "irtx";
125 nvidia,function = "uartb";
126 };
127 kbca {
128 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
129 "kbce", "kbcf";
130 nvidia,function = "kbc";
131 };
132 lcsn {
133 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
134 "lsdi", "lvp0";
135 nvidia,function = "rsvd4";
136 };
137 ld0 {
138 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
139 "ld5", "ld6", "ld7", "ld8", "ld9",
140 "ld10", "ld11", "ld12", "ld13", "ld14",
141 "ld15", "ld16", "ld17", "ldi", "lhp0",
142 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
143 "lspi", "lvp1", "lvs";
144 nvidia,function = "displaya";
145 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600146 owc {
147 nvidia,pins = "owc", "spdi", "spdo", "uac";
148 nvidia,function = "rsvd2";
149 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600150 pmc {
151 nvidia,pins = "pmc";
152 nvidia,function = "pwr_on";
153 };
154 rm {
155 nvidia,pins = "rm";
156 nvidia,function = "i2c1";
157 };
158 sdb {
159 nvidia,pins = "sdb", "sdc", "sdd";
160 nvidia,function = "sdio3";
161 };
162 sdio1 {
163 nvidia,pins = "sdio1";
164 nvidia,function = "sdio1";
165 };
166 slxc {
167 nvidia,pins = "slxc", "slxd";
168 nvidia,function = "spdif";
169 };
170 spid {
171 nvidia,pins = "spid", "spie", "spif";
172 nvidia,function = "spi1";
173 };
174 spig {
175 nvidia,pins = "spig", "spih";
176 nvidia,function = "spi2_alt";
177 };
178 uaa {
179 nvidia,pins = "uaa", "uab", "uda";
180 nvidia,function = "ulpi";
181 };
182 uad {
183 nvidia,pins = "uad";
184 nvidia,function = "irda";
185 };
186 uca {
187 nvidia,pins = "uca", "ucb";
188 nvidia,function = "uartc";
189 };
190 conf_ata {
191 nvidia,pins = "ata", "atb", "atc", "atd",
192 "cdev1", "cdev2", "dap1", "dap2",
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600193 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600194 "gme", "gpu", "gpu7", "i2cp", "irrx",
195 "irtx", "pta", "rm", "sdc", "sdd",
196 "slxd", "slxk", "spdi", "spdo", "uac",
197 "uad", "uca", "ucb", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600200 };
201 conf_ate {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600202 nvidia,pins = "ate", "csus", "dap3",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600203 "gpv", "owc", "slxc", "spib", "spid",
204 "spie";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600207 };
208 conf_ck32 {
209 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
210 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600212 };
213 conf_crtp {
214 nvidia,pins = "crtp", "gmb", "slxa", "spia",
215 "spig", "spih";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530216 nvidia,pull = <TEGRA_PIN_PULL_UP>;
217 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600218 };
219 conf_dta {
220 nvidia,pins = "dta", "dtb", "dtc", "dtd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530221 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600223 };
224 conf_dte {
225 nvidia,pins = "dte", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530226 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
227 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600228 };
229 conf_hdint {
230 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
231 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
232 "lvp0";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600234 };
235 conf_kbca {
236 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
237 "kbce", "kbcf", "sdio1", "spic", "uaa",
238 "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
240 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600241 };
242 conf_lc {
243 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600245 };
246 conf_ld0 {
247 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
248 "ld5", "ld6", "ld7", "ld8", "ld9",
249 "ld10", "ld11", "ld12", "ld13", "ld14",
250 "ld15", "ld16", "ld17", "ldi", "lhp0",
251 "lhp1", "lhp2", "lhs", "lm0", "lpp",
252 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
253 "lvs", "pmc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530254 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600255 };
256 conf_ld17_0 {
257 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
258 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600260 };
261 drive_sdio1 {
262 nvidia,pins = "drive_sdio1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530263 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
264 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
265 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600266 nvidia,pull-down-strength = <31>;
267 nvidia,pull-up-strength = <31>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530268 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
269 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600270 };
271 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600272
273 state_i2cmux_ddc: pinmux_i2cmux_ddc {
274 ddc {
275 nvidia,pins = "ddc";
276 nvidia,function = "i2c2";
277 };
278 pta {
279 nvidia,pins = "pta";
280 nvidia,function = "rsvd4";
281 };
282 };
283
284 state_i2cmux_pta: pinmux_i2cmux_pta {
285 ddc {
286 nvidia,pins = "ddc";
287 nvidia,function = "rsvd4";
288 };
289 pta {
290 nvidia,pins = "pta";
291 nvidia,function = "i2c2";
292 };
293 };
294
295 state_i2cmux_idle: pinmux_i2cmux_idle {
296 ddc {
297 nvidia,pins = "ddc";
298 nvidia,function = "rsvd4";
299 };
300 pta {
301 nvidia,pins = "pta";
302 nvidia,function = "rsvd4";
303 };
304 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600305 };
306
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600307 i2s@70002800 {
308 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600309 };
310
311 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600312 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600313 };
314
Stephen Warren88950f3b2011-11-21 14:44:09 -0700315 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600316 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700317 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700318
319 wm8903: wm8903@1a {
320 compatible = "wlf,wm8903";
321 reg = <0x1a>;
322 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700323 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700324
325 gpio-controller;
326 #gpio-cells = <2>;
327
328 micdet-cfg = <0>;
329 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600330 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700331 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530332
333 /* ALS and proximity sensor */
334 isl29018@44 {
335 compatible = "isil,isl29018";
336 reg = <0x44>;
337 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700338 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530339 };
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000340
341 gyrometer@68 {
342 compatible = "invn,mpu3050";
343 reg = <0x68>;
344 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700345 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000346 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700347 };
348
349 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600350 status = "okay";
Stephen Warren22bd1f72012-04-26 11:19:03 -0600351 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700352 };
353
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600354 i2cmux {
355 compatible = "i2c-mux-pinctrl";
356 #address-cells = <1>;
357 #size-cells = <0>;
358
359 i2c-parent = <&{/i2c@7000c400}>;
360
361 pinctrl-names = "ddc", "pta", "idle";
362 pinctrl-0 = <&state_i2cmux_ddc>;
363 pinctrl-1 = <&state_i2cmux_pta>;
364 pinctrl-2 = <&state_i2cmux_idle>;
365
Stephen Warrena75191e2013-01-02 14:53:20 -0700366 hdmi_ddc: i2c@0 {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600367 reg = <0>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 };
371
372 i2c@1 {
373 reg = <1>;
374 #address-cells = <1>;
375 #size-cells = <0>;
Stephen Warren0879c5f2012-04-25 16:57:28 -0600376
377 smart-battery@b {
378 compatible = "ti,bq20z75", "smart-battery-1.1";
379 reg = <0xb>;
380 ti,i2c-retry-count = <2>;
381 ti,poll-retry-count = <10>;
382 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600383 };
384 };
385
Stephen Warren88950f3b2011-11-21 14:44:09 -0700386 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600387 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700388 clock-frequency = <400000>;
389 };
390
391 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600392 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700393 clock-frequency = <400000>;
Stephen Warren401c9a52011-12-17 23:29:32 -0700394
Stephen Warren57899052013-11-26 14:43:45 -0700395 magnetometer@c {
396 compatible = "ak,ak8975";
397 reg = <0xc>;
398 interrupt-parent = <&gpio>;
399 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
400 };
401
Stephen Warren6529e632012-06-20 15:58:34 -0600402 pmic: tps6586x@34 {
403 compatible = "ti,tps6586x";
404 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700405 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600406
Stephen Warren44b12ef2012-09-11 11:42:26 -0600407 ti,system-power-controller;
408
Stephen Warren6529e632012-06-20 15:58:34 -0600409 #gpio-cells = <2>;
410 gpio-controller;
411
412 sys-supply = <&vdd_5v0_reg>;
413 vin-sm0-supply = <&sys_reg>;
414 vin-sm1-supply = <&sys_reg>;
415 vin-sm2-supply = <&sys_reg>;
416 vinldo01-supply = <&sm2_reg>;
417 vinldo23-supply = <&sm2_reg>;
418 vinldo4-supply = <&sm2_reg>;
419 vinldo678-supply = <&sm2_reg>;
420 vinldo9-supply = <&sm2_reg>;
421
422 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600423 sys_reg: sys {
Stephen Warren6529e632012-06-20 15:58:34 -0600424 regulator-name = "vdd_sys";
425 regulator-always-on;
426 };
427
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600428 sm0 {
Stephen Warren6529e632012-06-20 15:58:34 -0600429 regulator-name = "vdd_sm0,vdd_core";
430 regulator-min-microvolt = <1300000>;
431 regulator-max-microvolt = <1300000>;
432 regulator-always-on;
433 };
434
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600435 sm1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600436 regulator-name = "vdd_sm1,vdd_cpu";
437 regulator-min-microvolt = <1125000>;
438 regulator-max-microvolt = <1125000>;
439 regulator-always-on;
440 };
441
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600442 sm2_reg: sm2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600443 regulator-name = "vdd_sm2,vin_ldo*";
444 regulator-min-microvolt = <3700000>;
445 regulator-max-microvolt = <3700000>;
446 regulator-always-on;
447 };
448
449 /* LDO0 is not connected to anything */
450
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600451 ldo1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600452 regulator-name = "vdd_ldo1,avdd_pll*";
453 regulator-min-microvolt = <1100000>;
454 regulator-max-microvolt = <1100000>;
455 regulator-always-on;
456 };
457
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600458 ldo2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600459 regulator-name = "vdd_ldo2,vdd_rtc";
460 regulator-min-microvolt = <1200000>;
461 regulator-max-microvolt = <1200000>;
462 };
463
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600464 ldo3 {
Stephen Warren6529e632012-06-20 15:58:34 -0600465 regulator-name = "vdd_ldo3,avdd_usb*";
466 regulator-min-microvolt = <3300000>;
467 regulator-max-microvolt = <3300000>;
468 regulator-always-on;
469 };
470
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600471 ldo4 {
Stephen Warren6529e632012-06-20 15:58:34 -0600472 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
473 regulator-min-microvolt = <1800000>;
474 regulator-max-microvolt = <1800000>;
475 regulator-always-on;
476 };
477
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600478 ldo5 {
Stephen Warren6529e632012-06-20 15:58:34 -0600479 regulator-name = "vdd_ldo5,vcore_mmc";
480 regulator-min-microvolt = <2850000>;
481 regulator-max-microvolt = <2850000>;
482 regulator-always-on;
483 };
484
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600485 ldo6 {
Stephen Warren6529e632012-06-20 15:58:34 -0600486 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
487 regulator-min-microvolt = <1800000>;
488 regulator-max-microvolt = <1800000>;
489 };
490
Stephen Warrena75191e2013-01-02 14:53:20 -0700491 hdmi_vdd_reg: ldo7 {
Stephen Warren6529e632012-06-20 15:58:34 -0600492 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
493 regulator-min-microvolt = <3300000>;
494 regulator-max-microvolt = <3300000>;
495 };
496
Stephen Warrena75191e2013-01-02 14:53:20 -0700497 hdmi_pll_reg: ldo8 {
Stephen Warren6529e632012-06-20 15:58:34 -0600498 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
499 regulator-min-microvolt = <1800000>;
500 regulator-max-microvolt = <1800000>;
501 };
502
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600503 ldo9 {
Stephen Warren6529e632012-06-20 15:58:34 -0600504 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
505 regulator-min-microvolt = <2850000>;
506 regulator-max-microvolt = <2850000>;
507 regulator-always-on;
508 };
509
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600510 ldo_rtc {
Stephen Warren6529e632012-06-20 15:58:34 -0600511 regulator-name = "vdd_rtc_out,vdd_cell";
512 regulator-min-microvolt = <3300000>;
513 regulator-max-microvolt = <3300000>;
514 regulator-always-on;
515 };
516 };
517 };
518
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000519 temperature-sensor@4c {
Stephen Warren98462102012-11-19 15:34:44 -0700520 compatible = "onnn,nct1008";
Stephen Warren401c9a52011-12-17 23:29:32 -0700521 reg = <0x4c>;
522 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600523 };
524
Stephen Warren58ecb232013-11-25 17:53:16 -0700525 kbc@7000e200 {
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530526 status = "okay";
527 nvidia,debounce-delay-ms = <32>;
528 nvidia,repeat-delay-ms = <160>;
529 nvidia,ghost-filter;
530 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
531 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530532 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
533 MATRIX_KEY(0x00, 0x03, KEY_S)
534 MATRIX_KEY(0x00, 0x04, KEY_A)
535 MATRIX_KEY(0x00, 0x05, KEY_Z)
536 MATRIX_KEY(0x00, 0x07, KEY_FN)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530537
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530538 MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
539 MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
540 MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530541
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530542 MATRIX_KEY(0x03, 0x00, KEY_5)
543 MATRIX_KEY(0x03, 0x01, KEY_4)
544 MATRIX_KEY(0x03, 0x02, KEY_R)
545 MATRIX_KEY(0x03, 0x03, KEY_E)
546 MATRIX_KEY(0x03, 0x04, KEY_F)
547 MATRIX_KEY(0x03, 0x05, KEY_D)
548 MATRIX_KEY(0x03, 0x06, KEY_X)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530549
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530550 MATRIX_KEY(0x04, 0x00, KEY_7)
551 MATRIX_KEY(0x04, 0x01, KEY_6)
552 MATRIX_KEY(0x04, 0x02, KEY_T)
553 MATRIX_KEY(0x04, 0x03, KEY_H)
554 MATRIX_KEY(0x04, 0x04, KEY_G)
555 MATRIX_KEY(0x04, 0x05, KEY_V)
556 MATRIX_KEY(0x04, 0x06, KEY_C)
557 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530558
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530559 MATRIX_KEY(0x05, 0x00, KEY_9)
560 MATRIX_KEY(0x05, 0x01, KEY_8)
561 MATRIX_KEY(0x05, 0x02, KEY_U)
562 MATRIX_KEY(0x05, 0x03, KEY_Y)
563 MATRIX_KEY(0x05, 0x04, KEY_J)
564 MATRIX_KEY(0x05, 0x05, KEY_N)
565 MATRIX_KEY(0x05, 0x06, KEY_B)
566 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530567
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530568 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
569 MATRIX_KEY(0x06, 0x01, KEY_0)
570 MATRIX_KEY(0x06, 0x02, KEY_O)
571 MATRIX_KEY(0x06, 0x03, KEY_I)
572 MATRIX_KEY(0x06, 0x04, KEY_L)
573 MATRIX_KEY(0x06, 0x05, KEY_K)
574 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
575 MATRIX_KEY(0x06, 0x07, KEY_M)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530576
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530577 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
578 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
579 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
580 MATRIX_KEY(0x07, 0x07, KEY_MENU)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530581
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530582 MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
583 MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530584
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530585 MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
586 MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530587
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530588 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
589 MATRIX_KEY(0x0B, 0x01, KEY_P)
590 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
591 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
592 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
593 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530594
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530595 MATRIX_KEY(0x0C, 0x00, KEY_F10)
596 MATRIX_KEY(0x0C, 0x01, KEY_F9)
597 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
598 MATRIX_KEY(0x0C, 0x03, KEY_3)
599 MATRIX_KEY(0x0C, 0x04, KEY_2)
600 MATRIX_KEY(0x0C, 0x05, KEY_UP)
601 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
602 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530603
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530604 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
605 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
606 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
607 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
608 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
609 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
610 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530611
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530612 MATRIX_KEY(0x0E, 0x00, KEY_F11)
613 MATRIX_KEY(0x0E, 0x01, KEY_F12)
614 MATRIX_KEY(0x0E, 0x02, KEY_F8)
615 MATRIX_KEY(0x0E, 0x03, KEY_Q)
616 MATRIX_KEY(0x0E, 0x04, KEY_F4)
617 MATRIX_KEY(0x0E, 0x05, KEY_F3)
618 MATRIX_KEY(0x0E, 0x06, KEY_1)
619 MATRIX_KEY(0x0E, 0x07, KEY_F7)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530620
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530621 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
622 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
623 MATRIX_KEY(0x0F, 0x02, KEY_F5)
624 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
625 MATRIX_KEY(0x0F, 0x04, KEY_F1)
626 MATRIX_KEY(0x0F, 0x05, KEY_F2)
627 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
628 MATRIX_KEY(0x0F, 0x07, KEY_F6)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530629
630 /* Software Handled Function Keys */
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530631 MATRIX_KEY(0x14, 0x00, KEY_KP7)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530632
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530633 MATRIX_KEY(0x15, 0x00, KEY_KP9)
634 MATRIX_KEY(0x15, 0x01, KEY_KP8)
635 MATRIX_KEY(0x15, 0x02, KEY_KP4)
636 MATRIX_KEY(0x15, 0x04, KEY_KP1)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530637
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530638 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
639 MATRIX_KEY(0x16, 0x02, KEY_KP6)
640 MATRIX_KEY(0x16, 0x03, KEY_KP5)
641 MATRIX_KEY(0x16, 0x04, KEY_KP3)
642 MATRIX_KEY(0x16, 0x05, KEY_KP2)
643 MATRIX_KEY(0x16, 0x07, KEY_KP0)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530644
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530645 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
646 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
647 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
648 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530649
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530650 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530651
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530652 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
653 MATRIX_KEY(0x1D, 0x04, KEY_END)
654 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
655 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
656 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530657
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530658 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
659 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
660 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530661
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530662 MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530663 };
Stephen Warren57899052013-11-26 14:43:45 -0700664
665 pmc@7000e400 {
666 nvidia,invert-interrupt;
667 nvidia,suspend-mode = <1>;
668 nvidia,cpu-pwr-good-time = <5000>;
669 nvidia,cpu-pwr-off-time = <5000>;
670 nvidia,core-pwr-good-time = <3845 3845>;
671 nvidia,core-pwr-off-time = <3875>;
672 nvidia,sys-clock-req-active-high;
673 };
674
675 memory-controller@7000f400 {
676 emc-table@190000 {
677 reg = <190000>;
678 compatible = "nvidia,tegra20-emc-table";
679 clock-frequency = <190000>;
680 nvidia,emc-registers = <0x0000000c 0x00000026
681 0x00000009 0x00000003 0x00000004 0x00000004
682 0x00000002 0x0000000c 0x00000003 0x00000003
683 0x00000002 0x00000001 0x00000004 0x00000005
684 0x00000004 0x00000009 0x0000000d 0x0000059f
685 0x00000000 0x00000003 0x00000003 0x00000003
686 0x00000003 0x00000001 0x0000000b 0x000000c8
687 0x00000003 0x00000007 0x00000004 0x0000000f
688 0x00000002 0x00000000 0x00000000 0x00000002
689 0x00000000 0x00000000 0x00000083 0xa06204ae
690 0x007dc010 0x00000000 0x00000000 0x00000000
691 0x00000000 0x00000000 0x00000000 0x00000000>;
692 };
693
694 emc-table@380000 {
695 reg = <380000>;
696 compatible = "nvidia,tegra20-emc-table";
697 clock-frequency = <380000>;
698 nvidia,emc-registers = <0x00000017 0x0000004b
699 0x00000012 0x00000006 0x00000004 0x00000005
700 0x00000003 0x0000000c 0x00000006 0x00000006
701 0x00000003 0x00000001 0x00000004 0x00000005
702 0x00000004 0x00000009 0x0000000d 0x00000b5f
703 0x00000000 0x00000003 0x00000003 0x00000006
704 0x00000006 0x00000001 0x00000011 0x000000c8
705 0x00000003 0x0000000e 0x00000007 0x0000000f
706 0x00000002 0x00000000 0x00000000 0x00000002
707 0x00000000 0x00000000 0x00000083 0xe044048b
708 0x007d8010 0x00000000 0x00000000 0x00000000
709 0x00000000 0x00000000 0x00000000 0x00000000>;
710 };
711 };
712
713 usb@c5000000 {
714 status = "okay";
715 dr_mode = "otg";
716 };
717
718 usb-phy@c5000000 {
719 status = "okay";
720 vbus-supply = <&vbus_reg>;
721 dr_mode = "otg";
722 };
723
724 usb@c5004000 {
725 status = "okay";
726 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
727 GPIO_ACTIVE_LOW>;
728 };
729
730 usb-phy@c5004000 {
731 status = "okay";
732 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
733 GPIO_ACTIVE_LOW>;
734 };
735
736 usb@c5008000 {
737 status = "okay";
738 };
739
740 usb-phy@c5008000 {
741 status = "okay";
742 };
743
744 sdhci@c8000000 {
745 status = "okay";
746 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
747 bus-width = <4>;
748 keep-power-in-suspend;
749 };
750
751 sdhci@c8000400 {
752 status = "okay";
753 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
754 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
755 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
756 bus-width = <4>;
757 };
758
759 sdhci@c8000600 {
760 status = "okay";
761 bus-width = <8>;
762 non-removable;
763 };
764
765 clocks {
766 compatible = "simple-bus";
767 #address-cells = <1>;
768 #size-cells = <0>;
769
770 clk32k_in: clock@0 {
771 compatible = "fixed-clock";
772 reg=<0>;
773 #clock-cells = <0>;
774 clock-frequency = <32768>;
775 };
776 };
777
778 gpio-keys {
779 compatible = "gpio-keys";
780
781 power {
782 label = "Power";
783 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530784 linux,code = <KEY_POWER>;
Stephen Warren57899052013-11-26 14:43:45 -0700785 gpio-key,wakeup;
786 };
787
788 lid {
789 label = "Lid";
790 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
791 linux,input-type = <5>; /* EV_SW */
792 linux,code = <0>; /* SW_LID */
793 debounce-interval = <1>;
794 gpio-key,wakeup;
795 };
796 };
797
Stephen Warren6529e632012-06-20 15:58:34 -0600798 regulators {
799 compatible = "simple-bus";
800 #address-cells = <1>;
801 #size-cells = <0>;
802
803 vdd_5v0_reg: regulator@0 {
804 compatible = "regulator-fixed";
805 reg = <0>;
806 regulator-name = "vdd_5v0";
807 regulator-min-microvolt = <5000000>;
808 regulator-max-microvolt = <5000000>;
809 regulator-always-on;
810 };
811
812 regulator@1 {
813 compatible = "regulator-fixed";
814 reg = <1>;
815 regulator-name = "vdd_1v5";
816 regulator-min-microvolt = <1500000>;
817 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700818 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600819 };
820
821 regulator@2 {
822 compatible = "regulator-fixed";
823 reg = <2>;
824 regulator-name = "vdd_1v2";
825 regulator-min-microvolt = <1200000>;
826 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700827 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600828 enable-active-high;
829 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530830
831 vbus_reg: regulator@3 {
832 compatible = "regulator-fixed";
833 reg = <3>;
834 regulator-name = "vdd_vbus_wup1";
835 regulator-min-microvolt = <5000000>;
836 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600837 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600838 gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600839 regulator-always-on;
840 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530841 };
Stephen Warren6529e632012-06-20 15:58:34 -0600842 };
843
Stephen Warrenc04abb32012-05-11 17:03:26 -0600844 sound {
845 compatible = "nvidia,tegra-audio-wm8903-seaboard",
846 "nvidia,tegra-audio-wm8903";
847 nvidia,model = "NVIDIA Tegra Seaboard";
848
849 nvidia,audio-routing =
850 "Headphone Jack", "HPOUTR",
851 "Headphone Jack", "HPOUTL",
852 "Int Spk", "ROP",
853 "Int Spk", "RON",
854 "Int Spk", "LOP",
855 "Int Spk", "LON",
856 "Mic Jack", "MICBIAS",
857 "IN1R", "Mic Jack";
858
859 nvidia,i2s-controller = <&tegra_i2s1>;
860 nvidia,audio-codec = <&wm8903>;
861
Stephen Warren3325f1b2013-02-12 17:25:15 -0700862 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
863 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600864
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300865 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
866 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
867 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600868 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600869 };
Grant Likely8e267f32011-07-19 17:26:54 -0600870};