blob: 89816f89ff3f4b6f5cb0e7782ae9f4e34cebcb7c [file] [log] [blame]
Stephen Boyddd15ab82011-11-08 10:34:05 -08001/*
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -08002 *
3 * Copyright (C) 2007 Google, Inc.
Kumar Gala3f8e8ce2014-01-29 16:17:30 -06004 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -08005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Stephen Boyd4a184072011-11-08 10:34:04 -080017#include <linux/clocksource.h>
18#include <linux/clockchips.h>
Stephen Boyd4d70c592013-02-15 17:31:31 -080019#include <linux/cpu.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080020#include <linux/init.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080021#include <linux/interrupt.h>
22#include <linux/irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Stephen Boyd6e332162012-09-05 12:28:53 -070024#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070027#include <linux/sched_clock.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080028
Stephen Boyd013be5a2014-05-13 16:01:00 -070029#include <asm/delay.h>
30
Stephen Boyde25e3d12013-03-14 20:31:39 -070031#define TIMER_MATCH_VAL 0x0000
32#define TIMER_COUNT_VAL 0x0004
33#define TIMER_ENABLE 0x0008
34#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
35#define TIMER_ENABLE_EN BIT(0)
36#define TIMER_CLEAR 0x000C
37#define DGT_CLK_CTL 0x10
38#define DGT_CLK_CTL_DIV_4 0x3
39#define TIMER_STS_GPT0_CLR_PEND BIT(10)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080040
41#define GPT_HZ 32768
Jeff Ohlstein672039f2010-10-05 15:23:57 -070042
Stephen Boyd2a00c102011-11-08 10:34:07 -080043static void __iomem *event_base;
Stephen Boyde25e3d12013-03-14 20:31:39 -070044static void __iomem *sts_base;
Stephen Boyda850c3f2011-11-08 10:34:06 -080045
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080046static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
47{
Stephen Boyd4d70c592013-02-15 17:31:31 -080048 struct clock_event_device *evt = dev_id;
Stephen Boyda850c3f2011-11-08 10:34:06 -080049 /* Stop the timer tick */
Viresh Kumar736b2df2015-06-18 16:24:31 +053050 if (clockevent_state_oneshot(evt)) {
Stephen Boyd2a00c102011-11-08 10:34:07 -080051 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080052 ctrl &= ~TIMER_ENABLE_EN;
Stephen Boyd2a00c102011-11-08 10:34:07 -080053 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080054 }
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080055 evt->event_handler(evt);
56 return IRQ_HANDLED;
57}
58
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080059static int msm_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
61{
Stephen Boyd2a00c102011-11-08 10:34:07 -080062 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080063
Stephen Boyd4080d2d2013-03-14 20:31:37 -070064 ctrl &= ~TIMER_ENABLE_EN;
65 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
66
67 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
Stephen Boyd2a00c102011-11-08 10:34:07 -080068 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
Stephen Boyde25e3d12013-03-14 20:31:39 -070069
70 if (sts_base)
71 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
72 cpu_relax();
73
Stephen Boyd2a00c102011-11-08 10:34:07 -080074 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080075 return 0;
76}
77
Viresh Kumar736b2df2015-06-18 16:24:31 +053078static int msm_timer_shutdown(struct clock_event_device *evt)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080079{
Stephen Boyda850c3f2011-11-08 10:34:06 -080080 u32 ctrl;
81
Stephen Boyd2a00c102011-11-08 10:34:07 -080082 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080083 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
Stephen Boyd2a00c102011-11-08 10:34:07 -080084 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
Viresh Kumar736b2df2015-06-18 16:24:31 +053085 return 0;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080086}
87
Stephen Boyd4d70c592013-02-15 17:31:31 -080088static struct clock_event_device __percpu *msm_evt;
Stephen Boyd2a00c102011-11-08 10:34:07 -080089
90static void __iomem *source_base;
91
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +010092static notrace u64 msm_read_timer_count(struct clocksource *cs)
Stephen Boyd2a00c102011-11-08 10:34:07 -080093{
Stephen Boyd2081a6b2011-11-08 10:34:08 -080094 return readl_relaxed(source_base + TIMER_COUNT_VAL);
95}
96
Stephen Boyd2a00c102011-11-08 10:34:07 -080097static struct clocksource msm_clocksource = {
98 .name = "dg_timer",
99 .rating = 300,
100 .read = msm_read_timer_count,
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800101 .mask = CLOCKSOURCE_MASK(32),
Stephen Boyd2a00c102011-11-08 10:34:07 -0800102 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800103};
104
Stephen Boyd4d70c592013-02-15 17:31:31 -0800105static int msm_timer_irq;
106static int msm_timer_has_ppi;
107
Richard Cochranb0404162016-07-13 17:16:43 +0000108static int msm_local_timer_starting_cpu(unsigned int cpu)
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000109{
Richard Cochranb0404162016-07-13 17:16:43 +0000110 struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
Stephen Boyd4d70c592013-02-15 17:31:31 -0800111 int err;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000112
Stephen Boyd4d70c592013-02-15 17:31:31 -0800113 evt->irq = msm_timer_irq;
114 evt->name = "msm_timer";
115 evt->features = CLOCK_EVT_FEAT_ONESHOT;
116 evt->rating = 200;
Viresh Kumar736b2df2015-06-18 16:24:31 +0530117 evt->set_state_shutdown = msm_timer_shutdown;
118 evt->set_state_oneshot = msm_timer_shutdown;
119 evt->tick_resume = msm_timer_shutdown;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000120 evt->set_next_event = msm_timer_set_next_event;
Stephen Boyd4d70c592013-02-15 17:31:31 -0800121 evt->cpumask = cpumask_of(cpu);
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000122
Stephen Boyd4d70c592013-02-15 17:31:31 -0800123 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
124
125 if (msm_timer_has_ppi) {
126 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
127 } else {
128 err = request_irq(evt->irq, msm_timer_interrupt,
129 IRQF_TIMER | IRQF_NOBALANCING |
130 IRQF_TRIGGER_RISING, "gp_timer", evt);
131 if (err)
132 pr_err("request_irq failed\n");
133 }
134
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000135 return 0;
136}
137
Richard Cochranb0404162016-07-13 17:16:43 +0000138static int msm_local_timer_dying_cpu(unsigned int cpu)
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000139{
Richard Cochranb0404162016-07-13 17:16:43 +0000140 struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
141
Viresh Kumar736b2df2015-06-18 16:24:31 +0530142 evt->set_state_shutdown(evt);
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000143 disable_percpu_irq(evt->irq);
Richard Cochranb0404162016-07-13 17:16:43 +0000144 return 0;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000145}
146
Stephen Boyd6aa16a22013-11-15 15:26:16 -0800147static u64 notrace msm_sched_clock_read(void)
Stephen Boydf8e56c42012-02-22 01:39:37 +0000148{
149 return msm_clocksource.read(&msm_clocksource);
150}
151
Stephen Boyd013be5a2014-05-13 16:01:00 -0700152static unsigned long msm_read_current_timer(void)
153{
154 return msm_clocksource.read(&msm_clocksource);
155}
156
157static struct delay_timer msm_delay_timer = {
158 .read_current_timer = msm_read_current_timer,
159};
160
Daniel Lezcanoab511892016-06-06 17:58:43 +0200161static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700162 bool percpu)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800163{
Stephen Boyd2a00c102011-11-08 10:34:07 -0800164 struct clocksource *cs = &msm_clocksource;
Stephen Boyd4d70c592013-02-15 17:31:31 -0800165 int res = 0;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800166
Stephen Boyd4d70c592013-02-15 17:31:31 -0800167 msm_timer_irq = irq;
168 msm_timer_has_ppi = percpu;
David Brown8c27e6f2011-01-07 10:20:49 -0800169
Stephen Boyd4d70c592013-02-15 17:31:31 -0800170 msm_evt = alloc_percpu(struct clock_event_device);
171 if (!msm_evt) {
172 pr_err("memory allocation failed for clockevents\n");
173 goto err;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800174 }
Stephen Boyddd15ab82011-11-08 10:34:05 -0800175
Stephen Boyd4d70c592013-02-15 17:31:31 -0800176 if (percpu)
177 res = request_percpu_irq(irq, msm_timer_interrupt,
178 "gp_timer", msm_evt);
179
180 if (res) {
181 pr_err("request_percpu_irq failed\n");
182 } else {
Richard Cochranb0404162016-07-13 17:16:43 +0000183 /* Install and invoke hotplug callbacks */
184 res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
Thomas Gleixner73c1b412016-12-21 20:19:54 +0100185 "clockevents/qcom/timer:starting",
Richard Cochranb0404162016-07-13 17:16:43 +0000186 msm_local_timer_starting_cpu,
187 msm_local_timer_dying_cpu);
Stephen Boyd4d70c592013-02-15 17:31:31 -0800188 if (res) {
189 free_percpu_irq(irq, msm_evt);
190 goto err;
191 }
Stephen Boyd4d70c592013-02-15 17:31:31 -0800192 }
193
Stephen Boyddd15ab82011-11-08 10:34:05 -0800194err:
Stephen Boyd2a00c102011-11-08 10:34:07 -0800195 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800196 res = clocksource_register_hz(cs, dgt_hz);
Stephen Boyddd15ab82011-11-08 10:34:05 -0800197 if (res)
Stephen Boyd2a00c102011-11-08 10:34:07 -0800198 pr_err("clocksource_register failed\n");
Stephen Boyd6aa16a22013-11-15 15:26:16 -0800199 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
Stephen Boyd013be5a2014-05-13 16:01:00 -0700200 msm_delay_timer.freq = dgt_hz;
201 register_current_timer_delay(&msm_delay_timer);
Daniel Lezcanoab511892016-06-06 17:58:43 +0200202
203 return res;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800204}
205
Daniel Lezcanoab511892016-06-06 17:58:43 +0200206static int __init msm_dt_timer_init(struct device_node *np)
Stephen Boyd6e332162012-09-05 12:28:53 -0700207{
Stephen Boyd6e332162012-09-05 12:28:53 -0700208 u32 freq;
Daniel Lezcanoab511892016-06-06 17:58:43 +0200209 int irq, ret;
Stephen Boyd6e332162012-09-05 12:28:53 -0700210 struct resource res;
211 u32 percpu_offset;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700212 void __iomem *base;
213 void __iomem *cpu0_base;
Stephen Boyd6e332162012-09-05 12:28:53 -0700214
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700215 base = of_iomap(np, 0);
216 if (!base) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700217 pr_err("Failed to map event base\n");
Daniel Lezcanoab511892016-06-06 17:58:43 +0200218 return -ENXIO;
Stephen Boyd6e332162012-09-05 12:28:53 -0700219 }
220
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700221 /* We use GPT0 for the clockevent */
222 irq = irq_of_parse_and_map(np, 1);
Stephen Boyd6e332162012-09-05 12:28:53 -0700223 if (irq <= 0) {
224 pr_err("Can't get irq\n");
Daniel Lezcanoab511892016-06-06 17:58:43 +0200225 return -EINVAL;
Stephen Boyd6e332162012-09-05 12:28:53 -0700226 }
Stephen Boyd6e332162012-09-05 12:28:53 -0700227
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700228 /* We use CPU0's DGT for the clocksource */
Stephen Boyd6e332162012-09-05 12:28:53 -0700229 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
230 percpu_offset = 0;
231
Daniel Lezcanoab511892016-06-06 17:58:43 +0200232 ret = of_address_to_resource(np, 0, &res);
233 if (ret) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700234 pr_err("Failed to parse DGT resource\n");
Daniel Lezcanoab511892016-06-06 17:58:43 +0200235 return ret;
Stephen Boyd6e332162012-09-05 12:28:53 -0700236 }
237
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700238 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
239 if (!cpu0_base) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700240 pr_err("Failed to map source base\n");
Daniel Lezcanoab511892016-06-06 17:58:43 +0200241 return -EINVAL;
Stephen Boyd6e332162012-09-05 12:28:53 -0700242 }
243
Stephen Boyd6e332162012-09-05 12:28:53 -0700244 if (of_property_read_u32(np, "clock-frequency", &freq)) {
245 pr_err("Unknown frequency\n");
Daniel Lezcanoab511892016-06-06 17:58:43 +0200246 return -EINVAL;
Stephen Boyd6e332162012-09-05 12:28:53 -0700247 }
Stephen Boyd6e332162012-09-05 12:28:53 -0700248
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700249 event_base = base + 0x4;
Stephen Boyde25e3d12013-03-14 20:31:39 -0700250 sts_base = base + 0x88;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700251 source_base = cpu0_base + 0x24;
252 freq /= 4;
253 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
254
Daniel Lezcanoab511892016-06-06 17:58:43 +0200255 return msm_timer_init(freq, 32, irq, !!percpu_offset);
Stephen Boyd6e332162012-09-05 12:28:53 -0700256}
Daniel Lezcano17273392017-05-26 16:56:11 +0200257TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
258TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);