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Russell King6ebbf2c2014-06-30 16:29:12 +01001#include <asm/assembler.h>
Will Deaconc36ef4b2011-11-23 11:28:25 +01002#include <asm/unwind.h>
3
Russell King6323f0c2011-01-16 18:02:17 +00004#if __LINUX_ARM_ARCH__ >= 6
Will Deaconc36ef4b2011-11-23 11:28:25 +01005 .macro bitop, name, instr
6ENTRY( \name )
7UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +00008 ands ip, r1, #3
9 strneb r1, [ip] @ assert word-aligned
Russell King54ea06f2005-07-16 15:21:51 +010010 mov r2, #1
Russell King6323f0c2011-01-16 18:02:17 +000011 and r3, r0, #31 @ Get bit offset
12 mov r0, r0, lsr #5
13 add r1, r1, r0, lsl #2 @ Get word offset
Will Deaconb7ec6992013-11-19 15:46:11 +010014#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
Will Deacond779c072013-06-27 12:01:51 +010015 .arch_extension mp
16 ALT_SMP(W(pldw) [r1])
17 ALT_UP(W(nop))
18#endif
Russell King54ea06f2005-07-16 15:21:51 +010019 mov r3, r2, lsl r3
Russell King6323f0c2011-01-16 18:02:17 +0000201: ldrex r2, [r1]
Russell King54ea06f2005-07-16 15:21:51 +010021 \instr r2, r2, r3
Russell King6323f0c2011-01-16 18:02:17 +000022 strex r0, r2, [r1]
Russell Kinge7ec0292005-07-28 20:36:26 +010023 cmp r0, #0
Russell King54ea06f2005-07-16 15:21:51 +010024 bne 1b
Dave Martin3ba6e692011-02-08 12:09:52 +010025 bx lr
Will Deaconc36ef4b2011-11-23 11:28:25 +010026UNWIND( .fnend )
27ENDPROC(\name )
Russell King54ea06f2005-07-16 15:21:51 +010028 .endm
29
Will Deaconc36ef4b2011-11-23 11:28:25 +010030 .macro testop, name, instr, store
31ENTRY( \name )
32UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +000033 ands ip, r1, #3
34 strneb r1, [ip] @ assert word-aligned
Russell King54ea06f2005-07-16 15:21:51 +010035 mov r2, #1
Russell King6323f0c2011-01-16 18:02:17 +000036 and r3, r0, #31 @ Get bit offset
37 mov r0, r0, lsr #5
38 add r1, r1, r0, lsl #2 @ Get word offset
Russell King54ea06f2005-07-16 15:21:51 +010039 mov r3, r2, lsl r3 @ create mask
Russell Kingbac4e962009-05-25 20:58:00 +010040 smp_dmb
Will Deaconc32ffce2014-02-21 17:01:48 +010041#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
42 .arch_extension mp
43 ALT_SMP(W(pldw) [r1])
44 ALT_UP(W(nop))
45#endif
Russell King6323f0c2011-01-16 18:02:17 +0000461: ldrex r2, [r1]
Russell King54ea06f2005-07-16 15:21:51 +010047 ands r0, r2, r3 @ save old value of bit
Russell King6323f0c2011-01-16 18:02:17 +000048 \instr r2, r2, r3 @ toggle bit
49 strex ip, r2, [r1]
Russell King614d73e2005-07-27 23:00:05 +010050 cmp ip, #0
Russell King54ea06f2005-07-16 15:21:51 +010051 bne 1b
Russell Kingbac4e962009-05-25 20:58:00 +010052 smp_dmb
Russell King54ea06f2005-07-16 15:21:51 +010053 cmp r0, #0
54 movne r0, #1
Dave Martin3ba6e692011-02-08 12:09:52 +0100552: bx lr
Will Deaconc36ef4b2011-11-23 11:28:25 +010056UNWIND( .fnend )
57ENDPROC(\name )
Russell King54ea06f2005-07-16 15:21:51 +010058 .endm
59#else
Will Deaconc36ef4b2011-11-23 11:28:25 +010060 .macro bitop, name, instr
61ENTRY( \name )
62UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +000063 ands ip, r1, #3
64 strneb r1, [ip] @ assert word-aligned
Russell King6323f0c2011-01-16 18:02:17 +000065 and r2, r0, #31
66 mov r0, r0, lsr #5
Russell King7a55fd02005-04-18 22:50:01 +010067 mov r3, #1
68 mov r3, r3, lsl r2
Russell King59d1ff32005-11-09 15:04:22 +000069 save_and_disable_irqs ip
Russell King6323f0c2011-01-16 18:02:17 +000070 ldr r2, [r1, r0, lsl #2]
Russell King7a55fd02005-04-18 22:50:01 +010071 \instr r2, r2, r3
Russell King6323f0c2011-01-16 18:02:17 +000072 str r2, [r1, r0, lsl #2]
Russell King7a55fd02005-04-18 22:50:01 +010073 restore_irqs ip
Russell King6ebbf2c2014-06-30 16:29:12 +010074 ret lr
Will Deaconc36ef4b2011-11-23 11:28:25 +010075UNWIND( .fnend )
76ENDPROC(\name )
Russell King7a55fd02005-04-18 22:50:01 +010077 .endm
78
79/**
80 * testop - implement a test_and_xxx_bit operation.
81 * @instr: operational instruction
82 * @store: store instruction
83 *
84 * Note: we can trivially conditionalise the store instruction
Simon Arlott6cbdc8c2007-05-11 20:40:30 +010085 * to avoid dirtying the data cache.
Russell King7a55fd02005-04-18 22:50:01 +010086 */
Will Deaconc36ef4b2011-11-23 11:28:25 +010087 .macro testop, name, instr, store
88ENTRY( \name )
89UNWIND( .fnstart )
Russell Kinga16ede32011-01-16 17:59:44 +000090 ands ip, r1, #3
91 strneb r1, [ip] @ assert word-aligned
Russell King6323f0c2011-01-16 18:02:17 +000092 and r3, r0, #31
93 mov r0, r0, lsr #5
Russell King59d1ff32005-11-09 15:04:22 +000094 save_and_disable_irqs ip
Russell King6323f0c2011-01-16 18:02:17 +000095 ldr r2, [r1, r0, lsl #2]!
96 mov r0, #1
Russell King7a55fd02005-04-18 22:50:01 +010097 tst r2, r0, lsl r3
98 \instr r2, r2, r0, lsl r3
99 \store r2, [r1]
Russell King7a55fd02005-04-18 22:50:01 +0100100 moveq r0, #0
Uwe Kleine-König0d928b02009-08-13 20:38:17 +0200101 restore_irqs ip
Russell King6ebbf2c2014-06-30 16:29:12 +0100102 ret lr
Will Deaconc36ef4b2011-11-23 11:28:25 +0100103UNWIND( .fnend )
104ENDPROC(\name )
Russell King7a55fd02005-04-18 22:50:01 +0100105 .endm
Russell King54ea06f2005-07-16 15:21:51 +0100106#endif