Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 1 | #include <asm/assembler.h> |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 2 | #include <asm/unwind.h> |
| 3 | |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 4 | #if __LINUX_ARM_ARCH__ >= 6 |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 5 | .macro bitop, name, instr |
| 6 | ENTRY( \name ) |
| 7 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 8 | ands ip, r1, #3 |
| 9 | strneb r1, [ip] @ assert word-aligned |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 10 | mov r2, #1 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 11 | and r3, r0, #31 @ Get bit offset |
| 12 | mov r0, r0, lsr #5 |
| 13 | add r1, r1, r0, lsl #2 @ Get word offset |
Will Deacon | b7ec699 | 2013-11-19 15:46:11 +0100 | [diff] [blame] | 14 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
Will Deacon | d779c07 | 2013-06-27 12:01:51 +0100 | [diff] [blame] | 15 | .arch_extension mp |
| 16 | ALT_SMP(W(pldw) [r1]) |
| 17 | ALT_UP(W(nop)) |
| 18 | #endif |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 19 | mov r3, r2, lsl r3 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 20 | 1: ldrex r2, [r1] |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 21 | \instr r2, r2, r3 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 22 | strex r0, r2, [r1] |
Russell King | e7ec029 | 2005-07-28 20:36:26 +0100 | [diff] [blame] | 23 | cmp r0, #0 |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 24 | bne 1b |
Dave Martin | 3ba6e69 | 2011-02-08 12:09:52 +0100 | [diff] [blame] | 25 | bx lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 26 | UNWIND( .fnend ) |
| 27 | ENDPROC(\name ) |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 28 | .endm |
| 29 | |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 30 | .macro testop, name, instr, store |
| 31 | ENTRY( \name ) |
| 32 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 33 | ands ip, r1, #3 |
| 34 | strneb r1, [ip] @ assert word-aligned |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 35 | mov r2, #1 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 36 | and r3, r0, #31 @ Get bit offset |
| 37 | mov r0, r0, lsr #5 |
| 38 | add r1, r1, r0, lsl #2 @ Get word offset |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 39 | mov r3, r2, lsl r3 @ create mask |
Russell King | bac4e96 | 2009-05-25 20:58:00 +0100 | [diff] [blame] | 40 | smp_dmb |
Will Deacon | c32ffce | 2014-02-21 17:01:48 +0100 | [diff] [blame] | 41 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
| 42 | .arch_extension mp |
| 43 | ALT_SMP(W(pldw) [r1]) |
| 44 | ALT_UP(W(nop)) |
| 45 | #endif |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 46 | 1: ldrex r2, [r1] |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 47 | ands r0, r2, r3 @ save old value of bit |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 48 | \instr r2, r2, r3 @ toggle bit |
| 49 | strex ip, r2, [r1] |
Russell King | 614d73e | 2005-07-27 23:00:05 +0100 | [diff] [blame] | 50 | cmp ip, #0 |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 51 | bne 1b |
Russell King | bac4e96 | 2009-05-25 20:58:00 +0100 | [diff] [blame] | 52 | smp_dmb |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 53 | cmp r0, #0 |
| 54 | movne r0, #1 |
Dave Martin | 3ba6e69 | 2011-02-08 12:09:52 +0100 | [diff] [blame] | 55 | 2: bx lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 56 | UNWIND( .fnend ) |
| 57 | ENDPROC(\name ) |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 58 | .endm |
| 59 | #else |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 60 | .macro bitop, name, instr |
| 61 | ENTRY( \name ) |
| 62 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 63 | ands ip, r1, #3 |
| 64 | strneb r1, [ip] @ assert word-aligned |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 65 | and r2, r0, #31 |
| 66 | mov r0, r0, lsr #5 |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 67 | mov r3, #1 |
| 68 | mov r3, r3, lsl r2 |
Russell King | 59d1ff3 | 2005-11-09 15:04:22 +0000 | [diff] [blame] | 69 | save_and_disable_irqs ip |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 70 | ldr r2, [r1, r0, lsl #2] |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 71 | \instr r2, r2, r3 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 72 | str r2, [r1, r0, lsl #2] |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 73 | restore_irqs ip |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 74 | ret lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 75 | UNWIND( .fnend ) |
| 76 | ENDPROC(\name ) |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 77 | .endm |
| 78 | |
| 79 | /** |
| 80 | * testop - implement a test_and_xxx_bit operation. |
| 81 | * @instr: operational instruction |
| 82 | * @store: store instruction |
| 83 | * |
| 84 | * Note: we can trivially conditionalise the store instruction |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 85 | * to avoid dirtying the data cache. |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 86 | */ |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 87 | .macro testop, name, instr, store |
| 88 | ENTRY( \name ) |
| 89 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 90 | ands ip, r1, #3 |
| 91 | strneb r1, [ip] @ assert word-aligned |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 92 | and r3, r0, #31 |
| 93 | mov r0, r0, lsr #5 |
Russell King | 59d1ff3 | 2005-11-09 15:04:22 +0000 | [diff] [blame] | 94 | save_and_disable_irqs ip |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 95 | ldr r2, [r1, r0, lsl #2]! |
| 96 | mov r0, #1 |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 97 | tst r2, r0, lsl r3 |
| 98 | \instr r2, r2, r0, lsl r3 |
| 99 | \store r2, [r1] |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 100 | moveq r0, #0 |
Uwe Kleine-König | 0d928b0 | 2009-08-13 20:38:17 +0200 | [diff] [blame] | 101 | restore_irqs ip |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 102 | ret lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 103 | UNWIND( .fnend ) |
| 104 | ENDPROC(\name ) |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 105 | .endm |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 106 | #endif |