blob: c425826b1fc0f25c10989a500a037680d59e1de9 [file] [log] [blame]
Roland Dreier225c7b12007-05-08 18:00:38 -07001/*
Jack Morgenstein51a379d2008-07-25 10:32:52 -07002 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
Roland Dreier225c7b12007-05-08 18:00:38 -07003 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
Jack Morgensteinacba2422011-12-13 04:13:58 +000034#include <linux/init.h>
Roland Dreier225c7b12007-05-08 18:00:38 -070035#include <linux/interrupt.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090036#include <linux/slab.h>
Paul Gortmakeree40fa02011-05-27 16:14:23 -040037#include <linux/export.h>
Andrea Righi27ac7922008-07-23 21:28:13 -070038#include <linux/mm.h>
Al Viro9cbe05c2007-05-15 20:36:30 +010039#include <linux/dma-mapping.h>
Roland Dreier225c7b12007-05-08 18:00:38 -070040
41#include <linux/mlx4/cmd.h>
Amir Vadaid9236c32012-07-18 22:33:51 +000042#include <linux/cpu_rmap.h>
Roland Dreier225c7b12007-05-08 18:00:38 -070043
44#include "mlx4.h"
45#include "fw.h"
46
47enum {
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +000048 MLX4_IRQNAME_SIZE = 32
Arputham Benjaminf5f59512009-09-05 20:24:50 -070049};
50
51enum {
Roland Dreier225c7b12007-05-08 18:00:38 -070052 MLX4_NUM_ASYNC_EQE = 0x100,
53 MLX4_NUM_SPARE_EQE = 0x80,
54 MLX4_EQ_ENTRY_SIZE = 0x20
55};
56
Roland Dreier225c7b12007-05-08 18:00:38 -070057#define MLX4_EQ_STATUS_OK ( 0 << 28)
58#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
59#define MLX4_EQ_OWNER_SW ( 0 << 24)
60#define MLX4_EQ_OWNER_HW ( 1 << 24)
61#define MLX4_EQ_FLAG_EC ( 1 << 18)
62#define MLX4_EQ_FLAG_OI ( 1 << 17)
63#define MLX4_EQ_STATE_ARMED ( 9 << 8)
64#define MLX4_EQ_STATE_FIRED (10 << 8)
65#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66
67#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
Roland Dreier225c7b12007-05-08 18:00:38 -070076 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
Jack Morgensteinacba2422011-12-13 04:13:58 +000081 (1ull << MLX4_EVENT_TYPE_CMD) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
Jack Morgenstein5984be92012-03-06 15:50:49 +020083 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
Roland Dreier225c7b12007-05-08 18:00:38 -070085
Jack Morgenstein00f5ce92012-06-19 11:21:40 +030086static u64 get_async_ev_mask(struct mlx4_dev *dev)
87{
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
91
92 return async_ev_mask;
93}
94
Roland Dreier225c7b12007-05-08 18:00:38 -070095static void eq_set_ci(struct mlx4_eq *eq, int req_not)
96{
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
98 req_not << 31),
99 eq->doorbell);
100 /* We still want ordering, just not swabbing, so add a barrier */
101 mb();
102}
103
104static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
105{
106 unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
107 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
108}
109
110static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
111{
112 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
113 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
114}
115
Jack Morgensteinacba2422011-12-13 04:13:58 +0000116static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
117{
118 struct mlx4_eqe *eqe =
119 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
120 return (!!(eqe->owner & 0x80) ^
121 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
122 eqe : NULL;
123}
124
Jack Morgensteinacba2422011-12-13 04:13:58 +0000125void mlx4_gen_slave_eqe(struct work_struct *work)
126{
127 struct mlx4_mfunc_master_ctx *master =
128 container_of(work, struct mlx4_mfunc_master_ctx,
129 slave_event_work);
130 struct mlx4_mfunc *mfunc =
131 container_of(master, struct mlx4_mfunc, master);
132 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
133 struct mlx4_dev *dev = &priv->dev;
134 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
135 struct mlx4_eqe *eqe;
136 u8 slave;
137 int i;
138
139 for (eqe = next_slave_event_eqe(slave_eq); eqe;
140 eqe = next_slave_event_eqe(slave_eq)) {
141 slave = eqe->slave_id;
142
143 /* All active slaves need to receive the event */
144 if (slave == ALL_SLAVES) {
145 for (i = 0; i < dev->num_slaves; i++) {
146 if (i != dev->caps.function &&
147 master->slave_state[i].active)
148 if (mlx4_GEN_EQE(dev, i, eqe))
149 mlx4_warn(dev, "Failed to "
150 " generate event "
151 "for slave %d\n", i);
152 }
153 } else {
154 if (mlx4_GEN_EQE(dev, slave, eqe))
155 mlx4_warn(dev, "Failed to generate event "
156 "for slave %d\n", slave);
157 }
158 ++slave_eq->cons;
159 }
160}
161
162
163static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
164{
165 struct mlx4_priv *priv = mlx4_priv(dev);
166 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
167 struct mlx4_eqe *s_eqe =
168 &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
169
170 if ((!!(s_eqe->owner & 0x80)) ^
171 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
172 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
173 "No free EQE on slave events queue\n", slave);
174 return;
175 }
176
177 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1);
178 s_eqe->slave_id = slave;
179 /* ensure all information is written before setting the ownersip bit */
180 wmb();
181 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
182 ++slave_eq->prod;
183
184 queue_work(priv->mfunc.master.comm_wq,
185 &priv->mfunc.master.slave_event_work);
186}
187
188static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
189 struct mlx4_eqe *eqe)
190{
191 struct mlx4_priv *priv = mlx4_priv(dev);
192 struct mlx4_slave_state *s_slave =
193 &priv->mfunc.master.slave_state[slave];
194
195 if (!s_slave->active) {
196 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
197 return;
198 }
199
200 slave_event(dev, slave, eqe);
201}
202
Jack Morgenstein993c4012012-08-03 08:40:48 +0000203int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
204{
205 struct mlx4_eqe eqe;
206
207 struct mlx4_priv *priv = mlx4_priv(dev);
208 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
209
210 if (!s_slave->active)
211 return 0;
212
213 memset(&eqe, 0, sizeof eqe);
214
215 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
216 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
217 eqe.event.port_mgmt_change.port = port;
218
219 return mlx4_GEN_EQE(dev, slave, &eqe);
220}
221EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
222
223int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
224{
225 struct mlx4_eqe eqe;
226
227 /*don't send if we don't have the that slave */
228 if (dev->num_vfs < slave)
229 return 0;
230 memset(&eqe, 0, sizeof eqe);
231
232 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
233 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
234 eqe.event.port_mgmt_change.port = port;
235
236 return mlx4_GEN_EQE(dev, slave, &eqe);
237}
238EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
239
240int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
241 u8 port_subtype_change)
242{
243 struct mlx4_eqe eqe;
244
245 /*don't send if we don't have the that slave */
246 if (dev->num_vfs < slave)
247 return 0;
248 memset(&eqe, 0, sizeof eqe);
249
250 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
251 eqe.subtype = port_subtype_change;
252 eqe.event.port_change.port = cpu_to_be32(port << 28);
253
254 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
255 port_subtype_change, slave, port);
256 return mlx4_GEN_EQE(dev, slave, &eqe);
257}
258EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
259
260enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
261{
262 struct mlx4_priv *priv = mlx4_priv(dev);
263 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
264 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) {
265 pr_err("%s: Error: asking for slave:%d, port:%d\n",
266 __func__, slave, port);
267 return SLAVE_PORT_DOWN;
268 }
269 return s_state[slave].port_state[port];
270}
271EXPORT_SYMBOL(mlx4_get_slave_port_state);
272
273static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
274 enum slave_port_state state)
275{
276 struct mlx4_priv *priv = mlx4_priv(dev);
277 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
278
279 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
280 pr_err("%s: Error: asking for slave:%d, port:%d\n",
281 __func__, slave, port);
282 return -1;
283 }
284 s_state[slave].port_state[port] = state;
285
286 return 0;
287}
288
289static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
290{
291 int i;
292 enum slave_port_gen_event gen_event;
293
294 for (i = 0; i < dev->num_slaves; i++)
295 set_and_calc_slave_port_state(dev, i, port, event, &gen_event);
296}
297/**************************************************************************
298 The function get as input the new event to that port,
299 and according to the prev state change the slave's port state.
300 The events are:
301 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
302 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
303 MLX4_PORT_STATE_IB_EVENT_GID_VALID
304 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
305***************************************************************************/
306int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
307 u8 port, int event,
308 enum slave_port_gen_event *gen_event)
309{
310 struct mlx4_priv *priv = mlx4_priv(dev);
311 struct mlx4_slave_state *ctx = NULL;
312 unsigned long flags;
313 int ret = -1;
314 enum slave_port_state cur_state =
315 mlx4_get_slave_port_state(dev, slave, port);
316
317 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
318
319 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
320 pr_err("%s: Error: asking for slave:%d, port:%d\n",
321 __func__, slave, port);
322 return ret;
323 }
324
325 ctx = &priv->mfunc.master.slave_state[slave];
326 spin_lock_irqsave(&ctx->lock, flags);
327
328 mlx4_dbg(dev, "%s: slave: %d, current state: %d new event :%d\n",
329 __func__, slave, cur_state, event);
330
331 switch (cur_state) {
332 case SLAVE_PORT_DOWN:
333 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
334 mlx4_set_slave_port_state(dev, slave, port,
335 SLAVE_PENDING_UP);
336 break;
337 case SLAVE_PENDING_UP:
338 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
339 mlx4_set_slave_port_state(dev, slave, port,
340 SLAVE_PORT_DOWN);
341 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
342 mlx4_set_slave_port_state(dev, slave, port,
343 SLAVE_PORT_UP);
344 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
345 }
346 break;
347 case SLAVE_PORT_UP:
348 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
349 mlx4_set_slave_port_state(dev, slave, port,
350 SLAVE_PORT_DOWN);
351 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
352 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
353 event) {
354 mlx4_set_slave_port_state(dev, slave, port,
355 SLAVE_PENDING_UP);
356 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
357 }
358 break;
359 default:
360 pr_err("%s: BUG!!! UNKNOWN state: "
361 "slave:%d, port:%d\n", __func__, slave, port);
362 goto out;
363 }
364 ret = mlx4_get_slave_port_state(dev, slave, port);
365 mlx4_dbg(dev, "%s: slave: %d, current state: %d new event"
366 " :%d gen_event: %d\n",
367 __func__, slave, cur_state, event, *gen_event);
368
369out:
370 spin_unlock_irqrestore(&ctx->lock, flags);
371 return ret;
372}
373
374EXPORT_SYMBOL(set_and_calc_slave_port_state);
375
376int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
377{
378 struct mlx4_eqe eqe;
379
380 memset(&eqe, 0, sizeof eqe);
381
382 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
383 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
384 eqe.event.port_mgmt_change.port = port;
385 eqe.event.port_mgmt_change.params.port_info.changed_attr =
386 cpu_to_be32((u32) attr);
387
388 slave_event(dev, ALL_SLAVES, &eqe);
389 return 0;
390}
391EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
392
Jack Morgensteinacba2422011-12-13 04:13:58 +0000393void mlx4_master_handle_slave_flr(struct work_struct *work)
394{
395 struct mlx4_mfunc_master_ctx *master =
396 container_of(work, struct mlx4_mfunc_master_ctx,
397 slave_flr_event_work);
398 struct mlx4_mfunc *mfunc =
399 container_of(master, struct mlx4_mfunc, master);
400 struct mlx4_priv *priv =
401 container_of(mfunc, struct mlx4_priv, mfunc);
402 struct mlx4_dev *dev = &priv->dev;
403 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
404 int i;
405 int err;
406
407 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
408
409 for (i = 0 ; i < dev->num_slaves; i++) {
410
411 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
412 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
413 "clean slave: %d\n", i);
414
415 mlx4_delete_all_resources_for_slave(dev, i);
416 /*return the slave to running mode*/
417 spin_lock(&priv->mfunc.master.slave_state_lock);
418 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
419 slave_state[i].is_slave_going_down = 0;
420 spin_unlock(&priv->mfunc.master.slave_state_lock);
421 /*notify the FW:*/
422 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
423 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
424 if (err)
425 mlx4_warn(dev, "Failed to notify FW on "
426 "FLR done (slave:%d)\n", i);
427 }
428 }
429}
430
Roland Dreier225c7b12007-05-08 18:00:38 -0700431static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
432{
Jack Morgensteinacba2422011-12-13 04:13:58 +0000433 struct mlx4_priv *priv = mlx4_priv(dev);
Roland Dreier225c7b12007-05-08 18:00:38 -0700434 struct mlx4_eqe *eqe;
435 int cqn;
436 int eqes_found = 0;
437 int set_ci = 0;
Yevgeny Petrilin27bf91d2009-03-18 19:45:11 -0700438 int port;
Jack Morgensteinacba2422011-12-13 04:13:58 +0000439 int slave = 0;
440 int ret;
441 u32 flr_slave;
442 u8 update_slave_state;
443 int i;
Jack Morgenstein993c4012012-08-03 08:40:48 +0000444 enum slave_port_gen_event gen_event;
Roland Dreier225c7b12007-05-08 18:00:38 -0700445
446 while ((eqe = next_eqe_sw(eq))) {
447 /*
448 * Make sure we read EQ entry contents after we've
449 * checked the ownership bit.
450 */
451 rmb();
452
453 switch (eqe->type) {
454 case MLX4_EVENT_TYPE_COMP:
455 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
456 mlx4_cq_completion(dev, cqn);
457 break;
458
459 case MLX4_EVENT_TYPE_PATH_MIG:
460 case MLX4_EVENT_TYPE_COMM_EST:
461 case MLX4_EVENT_TYPE_SQ_DRAINED:
462 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
463 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
464 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
465 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
466 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
Jack Morgensteinacba2422011-12-13 04:13:58 +0000467 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
468 if (mlx4_is_master(dev)) {
469 /* forward only to slave owning the QP */
470 ret = mlx4_get_slave_from_resource_id(dev,
471 RES_QP,
472 be32_to_cpu(eqe->event.qp.qpn)
473 & 0xffffff, &slave);
474 if (ret && ret != -ENOENT) {
475 mlx4_dbg(dev, "QP event %02x(%02x) on "
476 "EQ %d at index %u: could "
477 "not get slave id (%d)\n",
478 eqe->type, eqe->subtype,
479 eq->eqn, eq->cons_index, ret);
480 break;
481 }
482
483 if (!ret && slave != dev->caps.function) {
484 mlx4_slave_event(dev, slave, eqe);
485 break;
486 }
487
488 }
489 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
490 0xffffff, eqe->type);
Roland Dreier225c7b12007-05-08 18:00:38 -0700491 break;
492
493 case MLX4_EVENT_TYPE_SRQ_LIMIT:
Jack Morgensteinacba2422011-12-13 04:13:58 +0000494 mlx4_warn(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
495 __func__);
Roland Dreier225c7b12007-05-08 18:00:38 -0700496 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
Jack Morgensteinacba2422011-12-13 04:13:58 +0000497 if (mlx4_is_master(dev)) {
498 /* forward only to slave owning the SRQ */
499 ret = mlx4_get_slave_from_resource_id(dev,
500 RES_SRQ,
501 be32_to_cpu(eqe->event.srq.srqn)
502 & 0xffffff,
503 &slave);
504 if (ret && ret != -ENOENT) {
505 mlx4_warn(dev, "SRQ event %02x(%02x) "
506 "on EQ %d at index %u: could"
507 " not get slave id (%d)\n",
508 eqe->type, eqe->subtype,
509 eq->eqn, eq->cons_index, ret);
510 break;
511 }
512 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
513 " event: %02x(%02x)\n", __func__,
514 slave,
515 be32_to_cpu(eqe->event.srq.srqn),
516 eqe->type, eqe->subtype);
517
518 if (!ret && slave != dev->caps.function) {
519 mlx4_warn(dev, "%s: sending event "
520 "%02x(%02x) to slave:%d\n",
521 __func__, eqe->type,
522 eqe->subtype, slave);
523 mlx4_slave_event(dev, slave, eqe);
524 break;
525 }
526 }
527 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
528 0xffffff, eqe->type);
Roland Dreier225c7b12007-05-08 18:00:38 -0700529 break;
530
531 case MLX4_EVENT_TYPE_CMD:
532 mlx4_cmd_event(dev,
533 be16_to_cpu(eqe->event.cmd.token),
534 eqe->event.cmd.status,
535 be64_to_cpu(eqe->event.cmd.out_param));
536 break;
537
538 case MLX4_EVENT_TYPE_PORT_CHANGE:
Yevgeny Petrilin27bf91d2009-03-18 19:45:11 -0700539 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
540 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
Jack Morgenstein993c4012012-08-03 08:40:48 +0000541 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
Yevgeny Petrilin27bf91d2009-03-18 19:45:11 -0700542 port);
543 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
Jack Morgenstein993c4012012-08-03 08:40:48 +0000544 if (!mlx4_is_master(dev))
545 break;
546 for (i = 0; i < dev->num_slaves; i++) {
547 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
548 if (i == mlx4_master_func_num(dev))
549 continue;
550 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
Jack Morgensteinacba2422011-12-13 04:13:58 +0000551 " to slave: %d, port:%d\n",
552 __func__, i, port);
Jack Morgensteinacba2422011-12-13 04:13:58 +0000553 mlx4_slave_event(dev, i, eqe);
Jack Morgenstein993c4012012-08-03 08:40:48 +0000554 } else { /* IB port */
555 set_and_calc_slave_port_state(dev, i, port,
556 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
557 &gen_event);
558 /*we can be in pending state, then do not send port_down event*/
559 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
560 if (i == mlx4_master_func_num(dev))
561 continue;
562 mlx4_slave_event(dev, i, eqe);
563 }
Jack Morgensteinacba2422011-12-13 04:13:58 +0000564 }
565 }
Jack Morgenstein993c4012012-08-03 08:40:48 +0000566 } else {
567 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
568
569 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
570
571 if (!mlx4_is_master(dev))
572 break;
573 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
574 for (i = 0; i < dev->num_slaves; i++) {
575 if (i == mlx4_master_func_num(dev))
576 continue;
577 mlx4_slave_event(dev, i, eqe);
578 }
579 else /* IB port */
580 /* port-up event will be sent to a slave when the
581 * slave's alias-guid is set. This is done in alias_GUID.c
582 */
583 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
Yevgeny Petrilin27bf91d2009-03-18 19:45:11 -0700584 }
Roland Dreier225c7b12007-05-08 18:00:38 -0700585 break;
586
587 case MLX4_EVENT_TYPE_CQ_ERROR:
588 mlx4_warn(dev, "CQ %s on CQN %06x\n",
589 eqe->event.cq_err.syndrome == 1 ?
590 "overrun" : "access violation",
591 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
Jack Morgensteinacba2422011-12-13 04:13:58 +0000592 if (mlx4_is_master(dev)) {
593 ret = mlx4_get_slave_from_resource_id(dev,
594 RES_CQ,
595 be32_to_cpu(eqe->event.cq_err.cqn)
596 & 0xffffff, &slave);
597 if (ret && ret != -ENOENT) {
598 mlx4_dbg(dev, "CQ event %02x(%02x) on "
599 "EQ %d at index %u: could "
600 "not get slave id (%d)\n",
601 eqe->type, eqe->subtype,
602 eq->eqn, eq->cons_index, ret);
603 break;
604 }
605
606 if (!ret && slave != dev->caps.function) {
607 mlx4_slave_event(dev, slave, eqe);
608 break;
609 }
610 }
611 mlx4_cq_event(dev,
612 be32_to_cpu(eqe->event.cq_err.cqn)
613 & 0xffffff,
Roland Dreier225c7b12007-05-08 18:00:38 -0700614 eqe->type);
615 break;
616
617 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
618 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
619 break;
620
Jack Morgensteinacba2422011-12-13 04:13:58 +0000621 case MLX4_EVENT_TYPE_COMM_CHANNEL:
622 if (!mlx4_is_master(dev)) {
623 mlx4_warn(dev, "Received comm channel event "
624 "for non master device\n");
625 break;
626 }
627 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
628 eqe->event.comm_channel_arm.bit_vec,
629 sizeof eqe->event.comm_channel_arm.bit_vec);
630 queue_work(priv->mfunc.master.comm_wq,
631 &priv->mfunc.master.comm_work);
632 break;
633
634 case MLX4_EVENT_TYPE_FLR_EVENT:
635 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
636 if (!mlx4_is_master(dev)) {
637 mlx4_warn(dev, "Non-master function received"
638 "FLR event\n");
639 break;
640 }
641
642 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
643
Jack Morgenstein30f7c732012-05-30 09:14:50 +0000644 if (flr_slave >= dev->num_slaves) {
Jack Morgensteinacba2422011-12-13 04:13:58 +0000645 mlx4_warn(dev,
646 "Got FLR for unknown function: %d\n",
647 flr_slave);
648 update_slave_state = 0;
649 } else
650 update_slave_state = 1;
651
652 spin_lock(&priv->mfunc.master.slave_state_lock);
653 if (update_slave_state) {
654 priv->mfunc.master.slave_state[flr_slave].active = false;
655 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
656 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
657 }
658 spin_unlock(&priv->mfunc.master.slave_state_lock);
659 queue_work(priv->mfunc.master.comm_wq,
660 &priv->mfunc.master.slave_flr_event_work);
661 break;
Jack Morgenstein5984be92012-03-06 15:50:49 +0200662
663 case MLX4_EVENT_TYPE_FATAL_WARNING:
664 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
665 if (mlx4_is_master(dev))
666 for (i = 0; i < dev->num_slaves; i++) {
667 mlx4_dbg(dev, "%s: Sending "
668 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
669 " to slave: %d\n", __func__, i);
670 if (i == dev->caps.function)
671 continue;
672 mlx4_slave_event(dev, i, eqe);
673 }
674 mlx4_err(dev, "Temperature Threshold was reached! "
675 "Threshold: %d celsius degrees; "
676 "Current Temperature: %d\n",
677 be16_to_cpu(eqe->event.warming.warning_threshold),
678 be16_to_cpu(eqe->event.warming.current_temperature));
679 } else
680 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
681 "subtype %02x on EQ %d at index %u. owner=%x, "
682 "nent=0x%x, slave=%x, ownership=%s\n",
683 eqe->type, eqe->subtype, eq->eqn,
684 eq->cons_index, eqe->owner, eq->nent,
685 eqe->slave_id,
686 !!(eqe->owner & 0x80) ^
687 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
688
689 break;
690
Jack Morgenstein00f5ce92012-06-19 11:21:40 +0300691 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
692 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
693 (unsigned long) eqe);
694 break;
695
Roland Dreier225c7b12007-05-08 18:00:38 -0700696 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
697 case MLX4_EVENT_TYPE_ECC_DETECT:
698 default:
Jack Morgensteinacba2422011-12-13 04:13:58 +0000699 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
700 "index %u. owner=%x, nent=0x%x, slave=%x, "
701 "ownership=%s\n",
702 eqe->type, eqe->subtype, eq->eqn,
703 eq->cons_index, eqe->owner, eq->nent,
704 eqe->slave_id,
705 !!(eqe->owner & 0x80) ^
706 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
Roland Dreier225c7b12007-05-08 18:00:38 -0700707 break;
Jack Morgensteinacba2422011-12-13 04:13:58 +0000708 };
Roland Dreier225c7b12007-05-08 18:00:38 -0700709
710 ++eq->cons_index;
711 eqes_found = 1;
712 ++set_ci;
713
714 /*
715 * The HCA will think the queue has overflowed if we
716 * don't tell it we've been processing events. We
717 * create our EQs with MLX4_NUM_SPARE_EQE extra
718 * entries, so we must update our consumer index at
719 * least that often.
720 */
721 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
Roland Dreier225c7b12007-05-08 18:00:38 -0700722 eq_set_ci(eq, 0);
723 set_ci = 0;
724 }
725 }
726
727 eq_set_ci(eq, 1);
728
729 return eqes_found;
730}
731
732static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
733{
734 struct mlx4_dev *dev = dev_ptr;
735 struct mlx4_priv *priv = mlx4_priv(dev);
736 int work = 0;
737 int i;
738
739 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
740
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -0800741 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
Roland Dreier225c7b12007-05-08 18:00:38 -0700742 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
743
744 return IRQ_RETVAL(work);
745}
746
747static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
748{
749 struct mlx4_eq *eq = eq_ptr;
750 struct mlx4_dev *dev = eq->dev;
751
752 mlx4_eq_int(dev, eq);
753
754 /* MSI-X vectors always belong to us */
755 return IRQ_HANDLED;
756}
757
Jack Morgensteinacba2422011-12-13 04:13:58 +0000758int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
759 struct mlx4_vhcr *vhcr,
760 struct mlx4_cmd_mailbox *inbox,
761 struct mlx4_cmd_mailbox *outbox,
762 struct mlx4_cmd_info *cmd)
763{
764 struct mlx4_priv *priv = mlx4_priv(dev);
765 struct mlx4_slave_event_eq_info *event_eq =
Marcel Apfelbaum803143f2012-01-19 09:45:46 +0000766 priv->mfunc.master.slave_state[slave].event_eq;
Jack Morgensteinacba2422011-12-13 04:13:58 +0000767 u32 in_modifier = vhcr->in_modifier;
768 u32 eqn = in_modifier & 0x1FF;
769 u64 in_param = vhcr->in_param;
770 int err = 0;
Marcel Apfelbaum803143f2012-01-19 09:45:46 +0000771 int i;
Jack Morgensteinacba2422011-12-13 04:13:58 +0000772
773 if (slave == dev->caps.function)
774 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
775 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
776 MLX4_CMD_NATIVE);
Marcel Apfelbaum803143f2012-01-19 09:45:46 +0000777 if (!err)
778 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
779 if (in_param & (1LL << i))
780 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
781
Jack Morgensteinacba2422011-12-13 04:13:58 +0000782 return err;
783}
784
Roland Dreier225c7b12007-05-08 18:00:38 -0700785static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
786 int eq_num)
787{
788 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
Jack Morgensteinf9baff52011-12-13 04:10:51 +0000789 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
790 MLX4_CMD_WRAPPED);
Roland Dreier225c7b12007-05-08 18:00:38 -0700791}
792
793static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
794 int eq_num)
795{
Marcel Apfelbaumeb410492012-01-19 09:45:19 +0000796 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
Jack Morgensteinacba2422011-12-13 04:13:58 +0000797 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
Jack Morgensteinf9baff52011-12-13 04:10:51 +0000798 MLX4_CMD_WRAPPED);
Roland Dreier225c7b12007-05-08 18:00:38 -0700799}
800
801static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
802 int eq_num)
803{
Marcel Apfelbaumeb410492012-01-19 09:45:19 +0000804 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
Jack Morgensteinacba2422011-12-13 04:13:58 +0000805 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
Jack Morgensteinf9baff52011-12-13 04:10:51 +0000806 MLX4_CMD_WRAPPED);
Roland Dreier225c7b12007-05-08 18:00:38 -0700807}
808
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -0800809static int mlx4_num_eq_uar(struct mlx4_dev *dev)
810{
811 /*
812 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
813 * we need to map, take the difference of highest index and
814 * the lowest index we'll use and add 1.
815 */
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +0000816 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
817 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -0800818}
819
Roland Dreier3d73c282007-10-10 15:43:54 -0700820static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
Roland Dreier225c7b12007-05-08 18:00:38 -0700821{
822 struct mlx4_priv *priv = mlx4_priv(dev);
823 int index;
824
825 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
826
827 if (!priv->eq_table.uar_map[index]) {
828 priv->eq_table.uar_map[index] =
829 ioremap(pci_resource_start(dev->pdev, 2) +
830 ((eq->eqn / 4) << PAGE_SHIFT),
831 PAGE_SIZE);
832 if (!priv->eq_table.uar_map[index]) {
833 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
834 eq->eqn);
835 return NULL;
836 }
837 }
838
839 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
840}
841
Roland Dreier3d73c282007-10-10 15:43:54 -0700842static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
843 u8 intr, struct mlx4_eq *eq)
Roland Dreier225c7b12007-05-08 18:00:38 -0700844{
845 struct mlx4_priv *priv = mlx4_priv(dev);
846 struct mlx4_cmd_mailbox *mailbox;
847 struct mlx4_eq_context *eq_context;
848 int npages;
849 u64 *dma_list = NULL;
850 dma_addr_t t;
851 u64 mtt_addr;
852 int err = -ENOMEM;
853 int i;
854
855 eq->dev = dev;
856 eq->nent = roundup_pow_of_two(max(nent, 2));
857 npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
858
859 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
860 GFP_KERNEL);
861 if (!eq->page_list)
862 goto err_out;
863
864 for (i = 0; i < npages; ++i)
865 eq->page_list[i].buf = NULL;
866
867 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
868 if (!dma_list)
869 goto err_out_free;
870
871 mailbox = mlx4_alloc_cmd_mailbox(dev);
872 if (IS_ERR(mailbox))
873 goto err_out_free;
874 eq_context = mailbox->buf;
875
876 for (i = 0; i < npages; ++i) {
877 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
878 PAGE_SIZE, &t, GFP_KERNEL);
879 if (!eq->page_list[i].buf)
880 goto err_out_free_pages;
881
882 dma_list[i] = t;
883 eq->page_list[i].map = t;
884
885 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
886 }
887
888 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
889 if (eq->eqn == -1)
890 goto err_out_free_pages;
891
892 eq->doorbell = mlx4_get_eq_uar(dev, eq);
893 if (!eq->doorbell) {
894 err = -ENOMEM;
895 goto err_out_free_eq;
896 }
897
898 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
899 if (err)
900 goto err_out_free_eq;
901
902 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
903 if (err)
904 goto err_out_free_mtt;
905
906 memset(eq_context, 0, sizeof *eq_context);
907 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
908 MLX4_EQ_STATE_ARMED);
909 eq_context->log_eq_size = ilog2(eq->nent);
910 eq_context->intr = intr;
911 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
912
913 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
914 eq_context->mtt_base_addr_h = mtt_addr >> 32;
915 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
916
917 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
918 if (err) {
919 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
920 goto err_out_free_mtt;
921 }
922
923 kfree(dma_list);
924 mlx4_free_cmd_mailbox(dev, mailbox);
925
926 eq->cons_index = 0;
927
928 return err;
929
930err_out_free_mtt:
931 mlx4_mtt_cleanup(dev, &eq->mtt);
932
933err_out_free_eq:
934 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
935
936err_out_free_pages:
937 for (i = 0; i < npages; ++i)
938 if (eq->page_list[i].buf)
939 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
940 eq->page_list[i].buf,
941 eq->page_list[i].map);
942
943 mlx4_free_cmd_mailbox(dev, mailbox);
944
945err_out_free:
946 kfree(eq->page_list);
947 kfree(dma_list);
948
949err_out:
950 return err;
951}
952
953static void mlx4_free_eq(struct mlx4_dev *dev,
954 struct mlx4_eq *eq)
955{
956 struct mlx4_priv *priv = mlx4_priv(dev);
957 struct mlx4_cmd_mailbox *mailbox;
958 int err;
959 int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
960 int i;
961
962 mailbox = mlx4_alloc_cmd_mailbox(dev);
963 if (IS_ERR(mailbox))
964 return;
965
966 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
967 if (err)
968 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
969
970 if (0) {
971 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
972 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
973 if (i % 4 == 0)
Joe Perches0a645e82010-07-10 07:22:46 +0000974 pr_cont("[%02x] ", i * 4);
975 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
Roland Dreier225c7b12007-05-08 18:00:38 -0700976 if ((i + 1) % 4 == 0)
Joe Perches0a645e82010-07-10 07:22:46 +0000977 pr_cont("\n");
Roland Dreier225c7b12007-05-08 18:00:38 -0700978 }
979 }
980
981 mlx4_mtt_cleanup(dev, &eq->mtt);
982 for (i = 0; i < npages; ++i)
Dotan Baraka8dc0df2011-10-06 09:33:12 -0700983 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
Roland Dreier225c7b12007-05-08 18:00:38 -0700984 eq->page_list[i].buf,
985 eq->page_list[i].map);
986
987 kfree(eq->page_list);
988 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
989 mlx4_free_cmd_mailbox(dev, mailbox);
990}
991
992static void mlx4_free_irqs(struct mlx4_dev *dev)
993{
994 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +0000995 struct mlx4_priv *priv = mlx4_priv(dev);
996 int i, vec;
Roland Dreier225c7b12007-05-08 18:00:38 -0700997
998 if (eq_table->have_irq)
999 free_irq(dev->pdev->irq, dev);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001000
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001001 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
Roland Dreierd1fdf242009-06-14 13:30:45 -07001002 if (eq_table->eq[i].have_irq) {
Roland Dreier225c7b12007-05-08 18:00:38 -07001003 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
Roland Dreierd1fdf242009-06-14 13:30:45 -07001004 eq_table->eq[i].have_irq = 0;
1005 }
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001006
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001007 for (i = 0; i < dev->caps.comp_pool; i++) {
1008 /*
1009 * Freeing the assigned irq's
1010 * all bits should be 0, but we need to validate
1011 */
1012 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1013 /* NO need protecting*/
1014 vec = dev->caps.num_comp_vectors + 1 + i;
1015 free_irq(priv->eq_table.eq[vec].irq,
1016 &priv->eq_table.eq[vec]);
1017 }
1018 }
1019
1020
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001021 kfree(eq_table->irq_names);
Roland Dreier225c7b12007-05-08 18:00:38 -07001022}
1023
Roland Dreier3d73c282007-10-10 15:43:54 -07001024static int mlx4_map_clr_int(struct mlx4_dev *dev)
Roland Dreier225c7b12007-05-08 18:00:38 -07001025{
1026 struct mlx4_priv *priv = mlx4_priv(dev);
1027
1028 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1029 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1030 if (!priv->clr_base) {
1031 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1032 return -ENOMEM;
1033 }
1034
1035 return 0;
1036}
1037
1038static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1039{
1040 struct mlx4_priv *priv = mlx4_priv(dev);
1041
1042 iounmap(priv->clr_base);
1043}
1044
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001045int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1046{
1047 struct mlx4_priv *priv = mlx4_priv(dev);
1048
1049 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1050 sizeof *priv->eq_table.eq, GFP_KERNEL);
1051 if (!priv->eq_table.eq)
1052 return -ENOMEM;
1053
1054 return 0;
1055}
1056
1057void mlx4_free_eq_table(struct mlx4_dev *dev)
1058{
1059 kfree(mlx4_priv(dev)->eq_table.eq);
1060}
1061
Roland Dreier3d73c282007-10-10 15:43:54 -07001062int mlx4_init_eq_table(struct mlx4_dev *dev)
Roland Dreier225c7b12007-05-08 18:00:38 -07001063{
1064 struct mlx4_priv *priv = mlx4_priv(dev);
1065 int err;
1066 int i;
1067
Axel Lin758ff232012-02-12 15:14:39 +00001068 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1069 sizeof *priv->eq_table.uar_map,
1070 GFP_KERNEL);
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001071 if (!priv->eq_table.uar_map) {
1072 err = -ENOMEM;
1073 goto err_out_free;
1074 }
1075
Roland Dreier225c7b12007-05-08 18:00:38 -07001076 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
Yevgeny Petrilin93fc9e12008-10-22 10:25:29 -07001077 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
Roland Dreier225c7b12007-05-08 18:00:38 -07001078 if (err)
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001079 goto err_out_free;
Roland Dreier225c7b12007-05-08 18:00:38 -07001080
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001081 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
Roland Dreier225c7b12007-05-08 18:00:38 -07001082 priv->eq_table.uar_map[i] = NULL;
1083
Jack Morgensteinacba2422011-12-13 04:13:58 +00001084 if (!mlx4_is_slave(dev)) {
1085 err = mlx4_map_clr_int(dev);
1086 if (err)
1087 goto err_out_bitmap;
Roland Dreier225c7b12007-05-08 18:00:38 -07001088
Jack Morgensteinacba2422011-12-13 04:13:58 +00001089 priv->eq_table.clr_mask =
1090 swab32(1 << (priv->eq_table.inta_pin & 31));
1091 priv->eq_table.clr_int = priv->clr_base +
1092 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1093 }
Roland Dreier225c7b12007-05-08 18:00:38 -07001094
Arputham Benjaminf5f59512009-09-05 20:24:50 -07001095 priv->eq_table.irq_names =
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001096 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1097 dev->caps.comp_pool),
Arputham Benjaminf5f59512009-09-05 20:24:50 -07001098 GFP_KERNEL);
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001099 if (!priv->eq_table.irq_names) {
1100 err = -ENOMEM;
1101 goto err_out_bitmap;
1102 }
1103
1104 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
Yevgeny Petrilinc3794742011-03-30 23:30:17 +00001105 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1106 dev->caps.reserved_cqs +
1107 MLX4_NUM_SPARE_EQE,
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001108 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1109 &priv->eq_table.eq[i]);
Yevgeny Petrilina5b19b62009-06-08 00:39:58 -07001110 if (err) {
1111 --i;
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001112 goto err_out_unmap;
Yevgeny Petrilina5b19b62009-06-08 00:39:58 -07001113 }
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001114 }
Roland Dreier225c7b12007-05-08 18:00:38 -07001115
1116 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001117 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1118 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
Roland Dreier225c7b12007-05-08 18:00:38 -07001119 if (err)
1120 goto err_out_comp;
1121
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001122 /*if additional completion vectors poolsize is 0 this loop will not run*/
1123 for (i = dev->caps.num_comp_vectors + 1;
1124 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1125
1126 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1127 dev->caps.reserved_cqs +
1128 MLX4_NUM_SPARE_EQE,
1129 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1130 &priv->eq_table.eq[i]);
1131 if (err) {
1132 --i;
1133 goto err_out_unmap;
1134 }
1135 }
1136
1137
Roland Dreier225c7b12007-05-08 18:00:38 -07001138 if (dev->flags & MLX4_FLAG_MSI_X) {
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001139 const char *eq_name;
Roland Dreier225c7b12007-05-08 18:00:38 -07001140
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001141 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1142 if (i < dev->caps.num_comp_vectors) {
Arputham Benjaminf5f59512009-09-05 20:24:50 -07001143 snprintf(priv->eq_table.irq_names +
1144 i * MLX4_IRQNAME_SIZE,
1145 MLX4_IRQNAME_SIZE,
1146 "mlx4-comp-%d@pci:%s", i,
1147 pci_name(dev->pdev));
1148 } else {
1149 snprintf(priv->eq_table.irq_names +
1150 i * MLX4_IRQNAME_SIZE,
1151 MLX4_IRQNAME_SIZE,
1152 "mlx4-async@pci:%s",
1153 pci_name(dev->pdev));
1154 }
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001155
Arputham Benjaminf5f59512009-09-05 20:24:50 -07001156 eq_name = priv->eq_table.irq_names +
1157 i * MLX4_IRQNAME_SIZE;
Roland Dreier225c7b12007-05-08 18:00:38 -07001158 err = request_irq(priv->eq_table.eq[i].irq,
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001159 mlx4_msi_x_interrupt, 0, eq_name,
1160 priv->eq_table.eq + i);
Roland Dreier225c7b12007-05-08 18:00:38 -07001161 if (err)
Jack Morgensteinee49bd92007-07-12 17:50:45 +03001162 goto err_out_async;
Roland Dreier225c7b12007-05-08 18:00:38 -07001163
1164 priv->eq_table.eq[i].have_irq = 1;
1165 }
Roland Dreier225c7b12007-05-08 18:00:38 -07001166 } else {
Arputham Benjaminf5f59512009-09-05 20:24:50 -07001167 snprintf(priv->eq_table.irq_names,
1168 MLX4_IRQNAME_SIZE,
1169 DRV_NAME "@pci:%s",
1170 pci_name(dev->pdev));
Roland Dreier225c7b12007-05-08 18:00:38 -07001171 err = request_irq(dev->pdev->irq, mlx4_interrupt,
Arputham Benjaminf5f59512009-09-05 20:24:50 -07001172 IRQF_SHARED, priv->eq_table.irq_names, dev);
Roland Dreier225c7b12007-05-08 18:00:38 -07001173 if (err)
1174 goto err_out_async;
1175
1176 priv->eq_table.have_irq = 1;
1177 }
1178
Jack Morgenstein00f5ce92012-06-19 11:21:40 +03001179 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001180 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
Roland Dreier225c7b12007-05-08 18:00:38 -07001181 if (err)
1182 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001183 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
Roland Dreier225c7b12007-05-08 18:00:38 -07001184
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001185 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
Roland Dreier225c7b12007-05-08 18:00:38 -07001186 eq_set_ci(&priv->eq_table.eq[i], 1);
1187
Roland Dreier225c7b12007-05-08 18:00:38 -07001188 return 0;
1189
Roland Dreier225c7b12007-05-08 18:00:38 -07001190err_out_async:
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001191 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
Roland Dreier225c7b12007-05-08 18:00:38 -07001192
1193err_out_comp:
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001194 i = dev->caps.num_comp_vectors - 1;
Roland Dreier225c7b12007-05-08 18:00:38 -07001195
1196err_out_unmap:
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001197 while (i >= 0) {
1198 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1199 --i;
1200 }
Jack Morgensteinacba2422011-12-13 04:13:58 +00001201 if (!mlx4_is_slave(dev))
1202 mlx4_unmap_clr_int(dev);
Roland Dreier225c7b12007-05-08 18:00:38 -07001203 mlx4_free_irqs(dev);
1204
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001205err_out_bitmap:
Roland Dreier225c7b12007-05-08 18:00:38 -07001206 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001207
1208err_out_free:
1209 kfree(priv->eq_table.uar_map);
1210
Roland Dreier225c7b12007-05-08 18:00:38 -07001211 return err;
1212}
1213
1214void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1215{
1216 struct mlx4_priv *priv = mlx4_priv(dev);
1217 int i;
1218
Jack Morgenstein00f5ce92012-06-19 11:21:40 +03001219 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001220 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
Roland Dreier225c7b12007-05-08 18:00:38 -07001221
1222 mlx4_free_irqs(dev);
1223
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001224 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
Roland Dreier225c7b12007-05-08 18:00:38 -07001225 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
Roland Dreier225c7b12007-05-08 18:00:38 -07001226
Jack Morgensteinacba2422011-12-13 04:13:58 +00001227 if (!mlx4_is_slave(dev))
1228 mlx4_unmap_clr_int(dev);
Roland Dreier225c7b12007-05-08 18:00:38 -07001229
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001230 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
Roland Dreier225c7b12007-05-08 18:00:38 -07001231 if (priv->eq_table.uar_map[i])
1232 iounmap(priv->eq_table.uar_map[i]);
1233
1234 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -08001235
1236 kfree(priv->eq_table.uar_map);
Roland Dreier225c7b12007-05-08 18:00:38 -07001237}
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +00001238
1239/* A test that verifies that we can accept interrupts on all
1240 * the irq vectors of the device.
1241 * Interrupts are checked using the NOP command.
1242 */
1243int mlx4_test_interrupts(struct mlx4_dev *dev)
1244{
1245 struct mlx4_priv *priv = mlx4_priv(dev);
1246 int i;
1247 int err;
1248
1249 err = mlx4_NOP(dev);
1250 /* When not in MSI_X, there is only one irq to check */
Jack Morgensteinacba2422011-12-13 04:13:58 +00001251 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +00001252 return err;
1253
1254 /* A loop over all completion vectors, for each vector we will check
1255 * whether it works by mapping command completions to that vector
1256 * and performing a NOP command
1257 */
1258 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1259 /* Temporary use polling for command completions */
1260 mlx4_cmd_use_polling(dev);
1261
1262 /* Map the new eq to handle all asyncronous events */
Jack Morgenstein00f5ce92012-06-19 11:21:40 +03001263 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +00001264 priv->eq_table.eq[i].eqn);
1265 if (err) {
1266 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1267 mlx4_cmd_use_events(dev);
1268 break;
1269 }
1270
1271 /* Go back to using events */
1272 mlx4_cmd_use_events(dev);
1273 err = mlx4_NOP(dev);
1274 }
1275
1276 /* Return to default */
Jack Morgenstein00f5ce92012-06-19 11:21:40 +03001277 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +00001278 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1279 return err;
1280}
1281EXPORT_SYMBOL(mlx4_test_interrupts);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001282
Amir Vadaid9236c32012-07-18 22:33:51 +00001283int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1284 int *vector)
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001285{
1286
1287 struct mlx4_priv *priv = mlx4_priv(dev);
1288 int vec = 0, err = 0, i;
1289
Yevgeny Petrilin730c41d2012-02-21 03:39:32 +00001290 mutex_lock(&priv->msix_ctl.pool_lock);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001291 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1292 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1293 priv->msix_ctl.pool_bm |= 1ULL << i;
1294 vec = dev->caps.num_comp_vectors + 1 + i;
1295 snprintf(priv->eq_table.irq_names +
1296 vec * MLX4_IRQNAME_SIZE,
1297 MLX4_IRQNAME_SIZE, "%s", name);
Amir Vadaid9236c32012-07-18 22:33:51 +00001298#ifdef CONFIG_RFS_ACCEL
1299 if (rmap) {
1300 err = irq_cpu_rmap_add(rmap,
1301 priv->eq_table.eq[vec].irq);
1302 if (err)
1303 mlx4_warn(dev, "Failed adding irq rmap\n");
1304 }
1305#endif
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001306 err = request_irq(priv->eq_table.eq[vec].irq,
1307 mlx4_msi_x_interrupt, 0,
1308 &priv->eq_table.irq_names[vec<<5],
1309 priv->eq_table.eq + vec);
1310 if (err) {
1311 /*zero out bit by fliping it*/
1312 priv->msix_ctl.pool_bm ^= 1 << i;
1313 vec = 0;
1314 continue;
1315 /*we dont want to break here*/
1316 }
1317 eq_set_ci(&priv->eq_table.eq[vec], 1);
1318 }
1319 }
Yevgeny Petrilin730c41d2012-02-21 03:39:32 +00001320 mutex_unlock(&priv->msix_ctl.pool_lock);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001321
1322 if (vec) {
1323 *vector = vec;
1324 } else {
1325 *vector = 0;
1326 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1327 }
1328 return err;
1329}
1330EXPORT_SYMBOL(mlx4_assign_eq);
1331
1332void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1333{
1334 struct mlx4_priv *priv = mlx4_priv(dev);
1335 /*bm index*/
1336 int i = vec - dev->caps.num_comp_vectors - 1;
1337
1338 if (likely(i >= 0)) {
1339 /*sanity check , making sure were not trying to free irq's
1340 Belonging to a legacy EQ*/
Yevgeny Petrilin730c41d2012-02-21 03:39:32 +00001341 mutex_lock(&priv->msix_ctl.pool_lock);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001342 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1343 free_irq(priv->eq_table.eq[vec].irq,
1344 &priv->eq_table.eq[vec]);
1345 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1346 }
Yevgeny Petrilin730c41d2012-02-21 03:39:32 +00001347 mutex_unlock(&priv->msix_ctl.pool_lock);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +00001348 }
1349
1350}
1351EXPORT_SYMBOL(mlx4_release_eq);
1352