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Tzachi Perelstein038ee082007-10-23 15:14:42 -04001/*
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -04002 * arch/arm/mach-orion5x/pci.c
Tzachi Perelstein038ee082007-10-23 15:14:42 -04003 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -04004 * PCI and PCIe functions for Marvell Orion System On Chip
Tzachi Perelstein038ee082007-10-23 15:14:42 -04005 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -04008 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
Tzachi Perelstein038ee082007-10-23 15:14:42 -040010 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -040016#include <linux/mbus.h>
Bryan Wu158c0c62011-08-17 17:29:38 +080017#include <video/vga.h>
Nicolas Pitreff89c462009-01-07 04:52:58 +010018#include <asm/irq.h>
Tzachi Perelstein038ee082007-10-23 15:14:42 -040019#include <asm/mach/pci.h>
Lennert Buytenhek6f088f12008-08-09 13:44:58 +020020#include <plat/pcie.h>
Andrew Lunn45173d52011-12-07 21:48:06 +010021#include <plat/addr-map.h>
Rob Herring8a52dd42012-02-10 18:29:09 -060022#include <mach/orion5x.h>
Tzachi Perelstein038ee082007-10-23 15:14:42 -040023#include "common.h"
24
25/*****************************************************************************
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040026 * Orion has one PCIe controller and one PCI controller.
Tzachi Perelstein038ee082007-10-23 15:14:42 -040027 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040028 * Note1: The local PCIe bus number is '0'. The local PCI bus number
29 * follows the scanned PCIe bridged busses, if any.
Tzachi Perelstein038ee082007-10-23 15:14:42 -040030 *
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040031 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
Tzachi Perelstein038ee082007-10-23 15:14:42 -040032 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
33 * device bus, Orion registers, etc. However this code only enable the
34 * access to DDR banks.
35 ****************************************************************************/
36
37
38/*****************************************************************************
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040039 * PCIe controller
Tzachi Perelstein038ee082007-10-23 15:14:42 -040040 ****************************************************************************/
Thomas Petazzoni3904a392012-09-11 14:27:21 +020041#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
Tzachi Perelstein038ee082007-10-23 15:14:42 -040042
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040043void __init orion5x_pcie_id(u32 *dev, u32 *rev)
Lennert Buytenhekabc01972008-03-27 14:51:40 -040044{
45 *dev = orion_pcie_dev_id(PCIE_BASE);
46 *rev = orion_pcie_rev(PCIE_BASE);
47}
Tzachi Perelstein038ee082007-10-23 15:14:42 -040048
Lennert Buytenhekabc01972008-03-27 14:51:40 -040049static int pcie_valid_config(int bus, int dev)
50{
51 /*
52 * Don't go out when trying to access --
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -040053 * 1. nonexisting device on local bus
Lennert Buytenhekabc01972008-03-27 14:51:40 -040054 * 2. where there's no device connected (no link)
55 */
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -040056 if (bus == 0 && dev == 0)
57 return 1;
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -040058
Lennert Buytenhekabc01972008-03-27 14:51:40 -040059 if (!orion_pcie_link_up(PCIE_BASE))
60 return 0;
61
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -040062 if (bus == 0 && dev != 1)
63 return 0;
64
Lennert Buytenhekabc01972008-03-27 14:51:40 -040065 return 1;
66}
67
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -040068
69/*
Lennert Buytenhek159ffb32008-03-27 14:51:41 -040070 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
Tzachi Perelstein038ee082007-10-23 15:14:42 -040071 * and then reading the PCIE_CONF_DATA register. Need to make sure these
72 * transactions are atomic.
73 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040074static DEFINE_SPINLOCK(orion5x_pcie_lock);
Tzachi Perelstein038ee082007-10-23 15:14:42 -040075
Lennert Buytenhekabc01972008-03-27 14:51:40 -040076static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
77 int size, u32 *val)
Tzachi Perelstein038ee082007-10-23 15:14:42 -040078{
79 unsigned long flags;
Lennert Buytenhekabc01972008-03-27 14:51:40 -040080 int ret;
Tzachi Perelstein038ee082007-10-23 15:14:42 -040081
Lennert Buytenhekabc01972008-03-27 14:51:40 -040082 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
Tzachi Perelstein038ee082007-10-23 15:14:42 -040083 *val = 0xffffffff;
84 return PCIBIOS_DEVICE_NOT_FOUND;
85 }
86
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040087 spin_lock_irqsave(&orion5x_pcie_lock, flags);
Lennert Buytenhekabc01972008-03-27 14:51:40 -040088 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -040089 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -040090
91 return ret;
92}
93
Lennert Buytenhekabc01972008-03-27 14:51:40 -040094static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
95 int where, int size, u32 *val)
96{
97 int ret;
98
99 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
100 *val = 0xffffffff;
101 return PCIBIOS_DEVICE_NOT_FOUND;
102 }
103
104 /*
105 * We only support access to the non-extended configuration
106 * space when using the WA access method (or we would have to
107 * sacrifice 256M of CPU virtual address space.)
108 */
109 if (where >= 0x100) {
110 *val = 0xffffffff;
111 return PCIBIOS_DEVICE_NOT_FOUND;
112 }
113
Thomas Petazzoni3904a392012-09-11 14:27:21 +0200114 ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400115 bus, devfn, where, size, val);
116
117 return ret;
118}
119
120static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
121 int where, int size, u32 val)
122{
123 unsigned long flags;
124 int ret;
125
126 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
127 return PCIBIOS_DEVICE_NOT_FOUND;
128
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400129 spin_lock_irqsave(&orion5x_pcie_lock, flags);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400130 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400131 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400132
133 return ret;
134}
135
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400136static struct pci_ops pcie_ops = {
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400137 .read = pcie_rd_conf,
138 .write = pcie_wr_conf,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400139};
140
141
Lennert Buytenheka9984272008-03-27 14:51:41 -0400142static int __init pcie_setup(struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400143{
144 struct resource *res;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400145 int dev;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400146
147 /*
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400148 * Generic PCIe unit setup.
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400149 */
Andrew Lunn63a93322011-12-07 21:48:07 +0100150 orion_pcie_setup(PCIE_BASE);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400151
152 /*
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400153 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 * read transaction workaround.
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400155 */
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400156 dev = orion_pcie_dev_id(PCIE_BASE);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n");
Thomas Petazzoni4ca2c042013-07-26 10:17:42 -0300160 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
161 ORION_MBUS_PCIE_WA_ATTR,
162 ORION5X_PCIE_WA_PHYS_BASE,
163 ORION5X_PCIE_WA_SIZE);
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400164 pcie_ops.read = pcie_rd_conf_wa;
165 }
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400166
Rob Herring0a4b8c62012-07-06 10:59:30 -0500167 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
168
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400169 /*
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400170 * Request resources.
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400171 */
Rob Herring0a4b8c62012-07-06 10:59:30 -0500172 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400173 if (!res)
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400174 panic("pcie_setup unable to alloc resources");
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400175
176 /*
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400177 * IORESOURCE_MEM
178 */
Rob Herring0a4b8c62012-07-06 10:59:30 -0500179 res->name = "PCIe Memory Space";
180 res->flags = IORESOURCE_MEM;
181 res->start = ORION5X_PCIE_MEM_PHYS_BASE;
182 res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
183 if (request_resource(&iomem_resource, res))
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400184 panic("Request PCIe Memory resource failed\n");
Rob Herring0a4b8c62012-07-06 10:59:30 -0500185 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400186
187 return 1;
188}
189
190/*****************************************************************************
191 * PCI controller
192 ****************************************************************************/
Thomas Petazzoni23326562012-09-11 14:27:17 +0200193#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400194#define PCI_MODE ORION5X_PCI_REG(0xd00)
195#define PCI_CMD ORION5X_PCI_REG(0xc00)
196#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
197#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
198#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400199
200/*
201 * PCI_MODE bits
202 */
203#define PCI_MODE_64BIT (1 << 2)
204#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
205
206/*
207 * PCI_CMD bits
208 */
209#define PCI_CMD_HOST_REORDER (1 << 29)
210
211/*
212 * PCI_P2P_CONF bits
213 */
214#define PCI_P2P_BUS_OFFS 16
215#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
216#define PCI_P2P_DEV_OFFS 24
217#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
218
219/*
220 * PCI_CONF_ADDR bits
221 */
222#define PCI_CONF_REG(reg) ((reg) & 0xfc)
223#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
224#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
225#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
226#define PCI_CONF_ADDR_EN (1 << 31)
227
228/*
229 * Internal configuration space
230 */
231#define PCI_CONF_FUNC_STAT_CMD 0
232#define PCI_CONF_REG_STAT_CMD 4
233#define PCIX_STAT 0x64
234#define PCIX_STAT_BUS_OFFS 8
235#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
236
237/*
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400238 * PCI Address Decode Windows registers
239 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400240#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
Lennert Buytenheke7068ad2008-05-10 16:30:01 +0200241 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
242 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
Andrew Lunn42366662013-10-23 16:12:51 +0200243 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
Lennert Buytenheke7068ad2008-05-10 16:30:01 +0200244#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
245 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
246 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
Andrew Lunn42366662013-10-23 16:12:51 +0200247 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400248#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
249#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400250
251/*
252 * PCI configuration helpers for BAR settings
253 */
254#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
255#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
256#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
257
258/*
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400259 * PCI config cycles are done by programming the PCI_CONF_ADDR register
260 * and then reading the PCI_CONF_DATA register. Need to make sure these
261 * transactions are atomic.
262 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400263static DEFINE_SPINLOCK(orion5x_pci_lock);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400264
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200265static int orion5x_pci_cardbus_mode;
266
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400267static int orion5x_pci_local_bus_nr(void)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400268{
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200269 u32 conf = readl(PCI_P2P_CONF);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400270 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
271}
272
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400273static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400274 u32 where, u32 size, u32 *val)
275{
276 unsigned long flags;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400277 spin_lock_irqsave(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400278
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200279 writel(PCI_CONF_BUS(bus) |
280 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
281 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400282
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200283 *val = readl(PCI_CONF_DATA);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400284
285 if (size == 1)
286 *val = (*val >> (8*(where & 0x3))) & 0xff;
287 else if (size == 2)
288 *val = (*val >> (8*(where & 0x3))) & 0xffff;
289
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400290 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400291
292 return PCIBIOS_SUCCESSFUL;
293}
294
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400295static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400296 u32 where, u32 size, u32 val)
297{
298 unsigned long flags;
299 int ret = PCIBIOS_SUCCESSFUL;
300
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400301 spin_lock_irqsave(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400302
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200303 writel(PCI_CONF_BUS(bus) |
304 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
305 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400306
307 if (size == 4) {
308 __raw_writel(val, PCI_CONF_DATA);
309 } else if (size == 2) {
310 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
311 } else if (size == 1) {
312 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
313 } else {
314 ret = PCIBIOS_BAD_REGISTER_NUMBER;
315 }
316
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400317 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400318
319 return ret;
320}
321
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200322static int orion5x_pci_valid_config(int bus, u32 devfn)
323{
324 if (bus == orion5x_pci_local_bus_nr()) {
325 /*
326 * Don't go out for local device
327 */
328 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
329 return 0;
330
331 /*
332 * When the PCI signals are directly connected to a
333 * Cardbus slot, ignore all but device IDs 0 and 1.
334 */
335 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
336 return 0;
337 }
338
339 return 1;
340}
341
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400342static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400343 int where, int size, u32 *val)
344{
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200345 if (!orion5x_pci_valid_config(bus->number, devfn)) {
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400346 *val = 0xffffffff;
347 return PCIBIOS_DEVICE_NOT_FOUND;
348 }
349
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400350 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400351 PCI_FUNC(devfn), where, size, val);
352}
353
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400354static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400355 int where, int size, u32 val)
356{
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200357 if (!orion5x_pci_valid_config(bus->number, devfn))
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400358 return PCIBIOS_DEVICE_NOT_FOUND;
359
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400360 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400361 PCI_FUNC(devfn), where, size, val);
362}
363
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400364static struct pci_ops pci_ops = {
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400365 .read = orion5x_pci_rd_conf,
366 .write = orion5x_pci_wr_conf,
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400367};
368
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400369static void __init orion5x_pci_set_bus_nr(int nr)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400370{
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200371 u32 p2p = readl(PCI_P2P_CONF);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400372
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200373 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400374 /*
375 * PCI-X mode
376 */
377 u32 pcix_status, bus, dev;
378 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
379 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400380 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400381 pcix_status &= ~PCIX_STAT_BUS_MASK;
382 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400383 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400384 } else {
385 /*
386 * PCI Conventional mode
387 */
388 p2p &= ~PCI_P2P_BUS_MASK;
389 p2p |= (nr << PCI_P2P_BUS_OFFS);
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200390 writel(p2p, PCI_P2P_CONF);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400391 }
392}
393
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400394static void __init orion5x_pci_master_slave_enable(void)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400395{
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -0400396 int bus_nr, func, reg;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400397 u32 val;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400398
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400399 bus_nr = orion5x_pci_local_bus_nr();
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400400 func = PCI_CONF_FUNC_STAT_CMD;
401 reg = PCI_CONF_REG_STAT_CMD;
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400402 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400403 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400404 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400405}
406
Thomas Petazzoni3e762c82013-03-06 17:59:58 +0100407static void __init orion5x_setup_pci_wins(void)
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400408{
Thomas Petazzoni3e762c82013-03-06 17:59:58 +0100409 const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400410 u32 win_enable;
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400411 int bus;
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400412 int i;
413
414 /*
415 * First, disable windows.
416 */
417 win_enable = 0xffffffff;
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200418 writel(win_enable, PCI_BAR_ENABLE);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400419
420 /*
421 * Setup windows for DDR banks.
422 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400423 bus = orion5x_pci_local_bus_nr();
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400424
425 for (i = 0; i < dram->num_cs; i++) {
Thomas Petazzoni3e762c82013-03-06 17:59:58 +0100426 const struct mbus_dram_window *cs = dram->cs + i;
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400427 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
428 u32 reg;
429 u32 val;
430
431 /*
432 * Write DRAM bank base address register.
433 */
434 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400435 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400436 val = (cs->base & 0xfffff000) | (val & 0xfff);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400437 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400438
439 /*
440 * Write DRAM bank size register.
441 */
442 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400443 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200444 writel((cs->size - 1) & 0xfffff000,
445 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
446 writel(cs->base & 0xfffff000,
447 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400448
449 /*
450 * Enable decode window for this chip select.
451 */
452 win_enable &= ~(1 << cs->cs_index);
453 }
454
455 /*
456 * Re-enable decode windows.
457 */
Lennert Buytenhek79e90dd2008-05-28 16:43:48 +0200458 writel(win_enable, PCI_BAR_ENABLE);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400459
460 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200461 * Disable automatic update of address remapping when writing to BARs.
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400462 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400463 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400464}
465
Lennert Buytenheka9984272008-03-27 14:51:41 -0400466static int __init pci_setup(struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400467{
468 struct resource *res;
469
470 /*
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400471 * Point PCI unit MBUS decode windows to DRAM space.
472 */
Thomas Petazzoni3e762c82013-03-06 17:59:58 +0100473 orion5x_setup_pci_wins();
Lennert Buytenhek1f2223b2008-03-27 14:51:39 -0400474
475 /*
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400476 * Master + Slave enable
477 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400478 orion5x_pci_master_slave_enable();
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400479
480 /*
481 * Force ordering
482 */
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400483 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400484
Rob Herring0a4b8c62012-07-06 10:59:30 -0500485 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
486
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400487 /*
488 * Request resources
489 */
Rob Herring0a4b8c62012-07-06 10:59:30 -0500490 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400491 if (!res)
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400492 panic("pci_setup unable to alloc resources");
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400493
494 /*
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400495 * IORESOURCE_MEM
496 */
Rob Herring0a4b8c62012-07-06 10:59:30 -0500497 res->name = "PCI Memory Space";
498 res->flags = IORESOURCE_MEM;
499 res->start = ORION5X_PCI_MEM_PHYS_BASE;
500 res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
501 if (request_resource(&iomem_resource, res))
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400502 panic("Request PCI Memory resource failed\n");
Rob Herring0a4b8c62012-07-06 10:59:30 -0500503 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400504
505 return 1;
506}
507
508
509/*****************************************************************************
Lennert Buytenhek159ffb32008-03-27 14:51:41 -0400510 * General PCIe + PCI
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400511 ****************************************************************************/
Greg Kroah-Hartman351a1022012-12-21 14:02:24 -0800512static void rc_pci_fixup(struct pci_dev *dev)
Lennert Buytenhekd50c60a2008-03-27 14:51:41 -0400513{
514 /*
515 * Prevent enumeration of root complex.
516 */
517 if (dev->bus->parent == NULL && dev->devfn == 0) {
518 int i;
519
520 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
521 dev->resource[i].start = 0;
522 dev->resource[i].end = 0;
523 dev->resource[i].flags = 0;
524 }
525 }
526}
527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
528
Per Andersson7a6bb262008-08-11 12:00:52 +0200529static int orion5x_pci_disabled __initdata;
530
531void __init orion5x_pci_disable(void)
532{
533 orion5x_pci_disabled = 1;
534}
535
Lennert Buytenhekda01bba2008-06-26 17:12:50 +0200536void __init orion5x_pci_set_cardbus_mode(void)
537{
538 orion5x_pci_cardbus_mode = 1;
539}
540
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400541int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400542{
Rob Herringcc22b4c2011-06-28 21:22:40 -0500543 vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
544
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400545 if (nr == 0) {
Lennert Buytenhekabc01972008-03-27 14:51:40 -0400546 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
Bjorn Helgaas9e808eb2015-03-12 15:07:04 -0500547 return pcie_setup(sys);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400548 }
549
Bjorn Helgaas9e808eb2015-03-12 15:07:04 -0500550 if (nr == 1 && !orion5x_pci_disabled) {
551 orion5x_pci_set_bus_nr(sys->busnr);
552 return pci_setup(sys);
553 }
554
555 return 0;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400556}
557
Lennert Buytenhek9dd0b192008-03-27 14:51:41 -0400558struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400559{
Bjorn Helgaas9e808eb2015-03-12 15:07:04 -0500560 if (nr == 0)
561 return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
562 &sys->resources);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400563
Bjorn Helgaas9e808eb2015-03-12 15:07:04 -0500564 if (nr == 1 && !orion5x_pci_disabled)
565 return pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
566 &sys->resources);
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400567
Bjorn Helgaas9e808eb2015-03-12 15:07:04 -0500568 BUG();
569 return NULL;
Tzachi Perelstein038ee082007-10-23 15:14:42 -0400570}
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400571
Ralf Baechled5341942011-06-10 15:30:21 +0100572int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400573{
574 int bus = dev->bus->number;
575
576 /*
577 * PCIe endpoint?
578 */
Per Andersson7a6bb262008-08-11 12:00:52 +0200579 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
Lennert Buytenhek92b913b2008-04-25 16:28:33 -0400580 return IRQ_ORION5X_PCIE0_INT;
581
582 return -1;
583}