blob: e629f8a9fe936be12cb587b921675363ae425cd7 [file] [log] [blame]
Alex Deucher1f7371b2015-12-02 17:46:21 -05001/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/gfp.h>
Jammy Zhouac885b32015-07-21 17:43:02 +080026#include <linux/slab.h>
Alex Deucher1f7371b2015-12-02 17:46:21 -050027#include "amd_shared.h"
28#include "amd_powerplay.h"
Jammy Zhouac885b32015-07-21 17:43:02 +080029#include "pp_instance.h"
Rex Zhu577bbe02015-08-28 12:56:43 +080030#include "power_state.h"
31#include "eventmanager.h"
Rex Zhue273b042015-12-07 18:44:23 +080032#include "pp_debug.h"
Alex Deucher1f7371b2015-12-02 17:46:21 -050033
Rex Zhua969e162015-12-29 13:56:03 +080034#define PP_CHECK(handle) \
35 do { \
36 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
37 return -EINVAL; \
38 } while (0)
39
Rex Zhu7383bcb2016-03-30 11:35:50 +080040#define PP_CHECK_HW(hwmgr) \
41 do { \
42 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
43 return -EINVAL; \
44 } while (0)
45
Alex Deucher1f7371b2015-12-02 17:46:21 -050046static int pp_early_init(void *handle)
47{
48 return 0;
49}
50
51static int pp_sw_init(void *handle)
52{
Jammy Zhou3bace352015-07-21 21:18:15 +080053 struct pp_instance *pp_handle;
54 struct pp_hwmgr *hwmgr;
55 int ret = 0;
56
57 if (handle == NULL)
58 return -EINVAL;
59
60 pp_handle = (struct pp_instance *)handle;
61 hwmgr = pp_handle->hwmgr;
62
Rex Zhu7383bcb2016-03-30 11:35:50 +080063 PP_CHECK_HW(hwmgr);
64
65 if (hwmgr->pptable_func == NULL ||
Jammy Zhou3bace352015-07-21 21:18:15 +080066 hwmgr->pptable_func->pptable_init == NULL ||
67 hwmgr->hwmgr_func->backend_init == NULL)
68 return -EINVAL;
69
70 ret = hwmgr->pptable_func->pptable_init(hwmgr);
Alex Deucher9441f962016-01-20 12:15:09 -050071 if (ret)
Huang Ruib4eeed52016-05-09 17:29:41 +080072 goto err;
Alex Deucher9441f962016-01-20 12:15:09 -050073
Huang Ruib4eeed52016-05-09 17:29:41 +080074 ret = hwmgr->hwmgr_func->backend_init(hwmgr);
75 if (ret)
Monk Liu9d8f0862016-05-30 13:43:45 +080076 goto err1;
Huang Ruib4eeed52016-05-09 17:29:41 +080077
78 pr_info("amdgpu: powerplay initialized\n");
79
80 return 0;
Monk Liu9d8f0862016-05-30 13:43:45 +080081err1:
82 if (hwmgr->pptable_func->pptable_fini)
83 hwmgr->pptable_func->pptable_fini(hwmgr);
Huang Ruib4eeed52016-05-09 17:29:41 +080084err:
85 pr_err("amdgpu: powerplay initialization failed\n");
Jammy Zhou3bace352015-07-21 21:18:15 +080086 return ret;
Alex Deucher1f7371b2015-12-02 17:46:21 -050087}
88
89static int pp_sw_fini(void *handle)
90{
Jammy Zhou3bace352015-07-21 21:18:15 +080091 struct pp_instance *pp_handle;
92 struct pp_hwmgr *hwmgr;
93 int ret = 0;
94
95 if (handle == NULL)
96 return -EINVAL;
97
98 pp_handle = (struct pp_instance *)handle;
99 hwmgr = pp_handle->hwmgr;
100
Rex Zhu7383bcb2016-03-30 11:35:50 +0800101 PP_CHECK_HW(hwmgr);
102
103 if (hwmgr->hwmgr_func->backend_fini != NULL)
Jammy Zhou3bace352015-07-21 21:18:15 +0800104 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
105
Monk Liu9d8f0862016-05-30 13:43:45 +0800106 if (hwmgr->pptable_func->pptable_fini)
107 hwmgr->pptable_func->pptable_fini(hwmgr);
108
Jammy Zhou3bace352015-07-21 21:18:15 +0800109 return ret;
Alex Deucher1f7371b2015-12-02 17:46:21 -0500110}
111
112static int pp_hw_init(void *handle)
113{
Jammy Zhouac885b32015-07-21 17:43:02 +0800114 struct pp_instance *pp_handle;
115 struct pp_smumgr *smumgr;
Rex Zhue92a0372015-09-23 15:14:54 +0800116 struct pp_eventmgr *eventmgr;
Jammy Zhouac885b32015-07-21 17:43:02 +0800117 int ret = 0;
118
119 if (handle == NULL)
120 return -EINVAL;
121
122 pp_handle = (struct pp_instance *)handle;
123 smumgr = pp_handle->smu_mgr;
124
125 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
126 smumgr->smumgr_funcs->smu_init == NULL ||
127 smumgr->smumgr_funcs->start_smu == NULL)
128 return -EINVAL;
129
130 ret = smumgr->smumgr_funcs->smu_init(smumgr);
131 if (ret) {
132 printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
133 return ret;
134 }
135
136 ret = smumgr->smumgr_funcs->start_smu(smumgr);
137 if (ret) {
138 printk(KERN_ERR "[ powerplay ] smc start failed\n");
139 smumgr->smumgr_funcs->smu_fini(smumgr);
140 return ret;
141 }
Jammy Zhou3bace352015-07-21 21:18:15 +0800142
Rex Zhue92a0372015-09-23 15:14:54 +0800143 hw_init_power_state_table(pp_handle->hwmgr);
144 eventmgr = pp_handle->eventmgr;
145
146 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
147 return -EINVAL;
148
149 ret = eventmgr->pp_eventmgr_init(eventmgr);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500150 return 0;
151}
152
153static int pp_hw_fini(void *handle)
154{
Jammy Zhouac885b32015-07-21 17:43:02 +0800155 struct pp_instance *pp_handle;
156 struct pp_smumgr *smumgr;
Rex Zhue92a0372015-09-23 15:14:54 +0800157 struct pp_eventmgr *eventmgr;
Jammy Zhouac885b32015-07-21 17:43:02 +0800158
159 if (handle == NULL)
160 return -EINVAL;
161
162 pp_handle = (struct pp_instance *)handle;
Rex Zhue92a0372015-09-23 15:14:54 +0800163 eventmgr = pp_handle->eventmgr;
164
165 if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL)
166 eventmgr->pp_eventmgr_fini(eventmgr);
167
Jammy Zhouac885b32015-07-21 17:43:02 +0800168 smumgr = pp_handle->smu_mgr;
169
170 if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
171 smumgr->smumgr_funcs->smu_fini != NULL)
172 smumgr->smumgr_funcs->smu_fini(smumgr);
173
Alex Deucher1f7371b2015-12-02 17:46:21 -0500174 return 0;
175}
176
177static bool pp_is_idle(void *handle)
178{
179 return 0;
180}
181
182static int pp_wait_for_idle(void *handle)
183{
184 return 0;
185}
186
187static int pp_sw_reset(void *handle)
188{
189 return 0;
190}
191
Alex Deucher1f7371b2015-12-02 17:46:21 -0500192
193static int pp_set_clockgating_state(void *handle,
194 enum amd_clockgating_state state)
195{
Eric Huang03e39052016-02-09 16:26:00 -0500196 struct pp_hwmgr *hwmgr;
197 uint32_t msg_id, pp_state;
198
199 if (handle == NULL)
200 return -EINVAL;
201
202 hwmgr = ((struct pp_instance *)handle)->hwmgr;
203
Rex Zhu7383bcb2016-03-30 11:35:50 +0800204 PP_CHECK_HW(hwmgr);
Eric Huang03e39052016-02-09 16:26:00 -0500205
Rex Zhu7383bcb2016-03-30 11:35:50 +0800206 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
207 printk(KERN_INFO "%s was not implemented.\n", __func__);
Flora Cui538333f2016-02-15 15:45:59 +0800208 return 0;
Rex Zhu7383bcb2016-03-30 11:35:50 +0800209 }
Flora Cui538333f2016-02-15 15:45:59 +0800210
Eric Huang03e39052016-02-09 16:26:00 -0500211 if (state == AMD_CG_STATE_UNGATE)
212 pp_state = 0;
213 else
214 pp_state = PP_STATE_CG | PP_STATE_LS;
215
216 /* Enable/disable GFX blocks clock gating through SMU */
217 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
218 PP_BLOCK_GFX_CG,
219 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
220 pp_state);
221 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
222 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
223 PP_BLOCK_GFX_3D,
224 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
225 pp_state);
226 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
227 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
228 PP_BLOCK_GFX_RLC,
229 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
230 pp_state);
231 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
232 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
233 PP_BLOCK_GFX_CP,
234 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
235 pp_state);
236 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
237 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
238 PP_BLOCK_GFX_MG,
239 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
240 pp_state);
241 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
242
243 /* Enable/disable System blocks clock gating through SMU */
244 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
245 PP_BLOCK_SYS_BIF,
246 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
247 pp_state);
248 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
249 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
250 PP_BLOCK_SYS_BIF,
251 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
252 pp_state);
253 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
254 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
255 PP_BLOCK_SYS_MC,
256 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
257 pp_state);
258 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
259 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
260 PP_BLOCK_SYS_ROM,
261 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
262 pp_state);
263 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
264 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
265 PP_BLOCK_SYS_DRM,
266 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
267 pp_state);
268 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
269 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
270 PP_BLOCK_SYS_HDP,
271 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
272 pp_state);
273 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
274 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
275 PP_BLOCK_SYS_SDMA,
276 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
277 pp_state);
278 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
279
Alex Deucher1f7371b2015-12-02 17:46:21 -0500280 return 0;
281}
282
283static int pp_set_powergating_state(void *handle,
284 enum amd_powergating_state state)
285{
Eric Huang65f85e72016-02-11 15:54:45 -0500286 struct pp_hwmgr *hwmgr;
287
288 if (handle == NULL)
289 return -EINVAL;
290
291 hwmgr = ((struct pp_instance *)handle)->hwmgr;
292
Rex Zhu7383bcb2016-03-30 11:35:50 +0800293 PP_CHECK_HW(hwmgr);
294
295 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
296 printk(KERN_INFO "%s was not implemented.\n", __func__);
297 return 0;
298 }
Eric Huang65f85e72016-02-11 15:54:45 -0500299
300 /* Enable/disable GFX per cu powergating through SMU */
301 return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
302 state == AMD_PG_STATE_GATE ? true : false);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500303}
304
305static int pp_suspend(void *handle)
306{
Rex Zhu577bbe02015-08-28 12:56:43 +0800307 struct pp_instance *pp_handle;
308 struct pp_eventmgr *eventmgr;
309 struct pem_event_data event_data = { {0} };
310
311 if (handle == NULL)
312 return -EINVAL;
313
314 pp_handle = (struct pp_instance *)handle;
315 eventmgr = pp_handle->eventmgr;
316 pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500317 return 0;
318}
319
320static int pp_resume(void *handle)
321{
Rex Zhu577bbe02015-08-28 12:56:43 +0800322 struct pp_instance *pp_handle;
323 struct pp_eventmgr *eventmgr;
324 struct pem_event_data event_data = { {0} };
Rex Zhue0b71a72015-12-29 10:25:19 +0800325 struct pp_smumgr *smumgr;
326 int ret;
Rex Zhu577bbe02015-08-28 12:56:43 +0800327
328 if (handle == NULL)
329 return -EINVAL;
330
331 pp_handle = (struct pp_instance *)handle;
Rex Zhue0b71a72015-12-29 10:25:19 +0800332 smumgr = pp_handle->smu_mgr;
333
334 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
335 smumgr->smumgr_funcs->start_smu == NULL)
336 return -EINVAL;
337
338 ret = smumgr->smumgr_funcs->start_smu(smumgr);
339 if (ret) {
340 printk(KERN_ERR "[ powerplay ] smc start failed\n");
341 smumgr->smumgr_funcs->smu_fini(smumgr);
342 return ret;
343 }
344
Rex Zhu577bbe02015-08-28 12:56:43 +0800345 eventmgr = pp_handle->eventmgr;
346 pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
Rex Zhue0b71a72015-12-29 10:25:19 +0800347
Alex Deucher1f7371b2015-12-02 17:46:21 -0500348 return 0;
349}
350
351const struct amd_ip_funcs pp_ip_funcs = {
Tom St Denis88a907d2016-05-04 14:28:35 -0400352 .name = "powerplay",
Alex Deucher1f7371b2015-12-02 17:46:21 -0500353 .early_init = pp_early_init,
354 .late_init = NULL,
355 .sw_init = pp_sw_init,
356 .sw_fini = pp_sw_fini,
357 .hw_init = pp_hw_init,
358 .hw_fini = pp_hw_fini,
359 .suspend = pp_suspend,
360 .resume = pp_resume,
361 .is_idle = pp_is_idle,
362 .wait_for_idle = pp_wait_for_idle,
363 .soft_reset = pp_sw_reset,
Alex Deucher1f7371b2015-12-02 17:46:21 -0500364 .set_clockgating_state = pp_set_clockgating_state,
365 .set_powergating_state = pp_set_powergating_state,
366};
367
368static int pp_dpm_load_fw(void *handle)
369{
370 return 0;
371}
372
373static int pp_dpm_fw_loading_complete(void *handle)
374{
375 return 0;
376}
377
378static int pp_dpm_force_performance_level(void *handle,
379 enum amd_dpm_forced_level level)
380{
Rex Zhu577bbe02015-08-28 12:56:43 +0800381 struct pp_instance *pp_handle;
382 struct pp_hwmgr *hwmgr;
383
384 if (handle == NULL)
385 return -EINVAL;
386
387 pp_handle = (struct pp_instance *)handle;
388
389 hwmgr = pp_handle->hwmgr;
390
Rex Zhu7383bcb2016-03-30 11:35:50 +0800391 PP_CHECK_HW(hwmgr);
392
393 if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
394 printk(KERN_INFO "%s was not implemented.\n", __func__);
395 return 0;
396 }
Rex Zhu577bbe02015-08-28 12:56:43 +0800397
398 hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
399
Alex Deucher1f7371b2015-12-02 17:46:21 -0500400 return 0;
401}
Rex Zhu577bbe02015-08-28 12:56:43 +0800402
Alex Deucher1f7371b2015-12-02 17:46:21 -0500403static enum amd_dpm_forced_level pp_dpm_get_performance_level(
404 void *handle)
405{
Rex Zhu577bbe02015-08-28 12:56:43 +0800406 struct pp_hwmgr *hwmgr;
407
408 if (handle == NULL)
409 return -EINVAL;
410
411 hwmgr = ((struct pp_instance *)handle)->hwmgr;
412
413 if (hwmgr == NULL)
414 return -EINVAL;
415
416 return (((struct pp_instance *)handle)->hwmgr->dpm_level);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500417}
Rex Zhu577bbe02015-08-28 12:56:43 +0800418
Alex Deucher1f7371b2015-12-02 17:46:21 -0500419static int pp_dpm_get_sclk(void *handle, bool low)
420{
Rex Zhu577bbe02015-08-28 12:56:43 +0800421 struct pp_hwmgr *hwmgr;
422
423 if (handle == NULL)
424 return -EINVAL;
425
426 hwmgr = ((struct pp_instance *)handle)->hwmgr;
427
Rex Zhu7383bcb2016-03-30 11:35:50 +0800428 PP_CHECK_HW(hwmgr);
429
430 if (hwmgr->hwmgr_func->get_sclk == NULL) {
431 printk(KERN_INFO "%s was not implemented.\n", __func__);
432 return 0;
433 }
Rex Zhu577bbe02015-08-28 12:56:43 +0800434
435 return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500436}
Rex Zhu577bbe02015-08-28 12:56:43 +0800437
Alex Deucher1f7371b2015-12-02 17:46:21 -0500438static int pp_dpm_get_mclk(void *handle, bool low)
439{
Rex Zhu577bbe02015-08-28 12:56:43 +0800440 struct pp_hwmgr *hwmgr;
441
442 if (handle == NULL)
443 return -EINVAL;
444
445 hwmgr = ((struct pp_instance *)handle)->hwmgr;
446
Rex Zhu7383bcb2016-03-30 11:35:50 +0800447 PP_CHECK_HW(hwmgr);
448
449 if (hwmgr->hwmgr_func->get_mclk == NULL) {
450 printk(KERN_INFO "%s was not implemented.\n", __func__);
451 return 0;
452 }
Rex Zhu577bbe02015-08-28 12:56:43 +0800453
454 return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500455}
Rex Zhu577bbe02015-08-28 12:56:43 +0800456
Alex Deucher1f7371b2015-12-02 17:46:21 -0500457static int pp_dpm_powergate_vce(void *handle, bool gate)
458{
Rex Zhu577bbe02015-08-28 12:56:43 +0800459 struct pp_hwmgr *hwmgr;
460
461 if (handle == NULL)
462 return -EINVAL;
463
464 hwmgr = ((struct pp_instance *)handle)->hwmgr;
465
Rex Zhu7383bcb2016-03-30 11:35:50 +0800466 PP_CHECK_HW(hwmgr);
467
468 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
469 printk(KERN_INFO "%s was not implemented.\n", __func__);
470 return 0;
471 }
Rex Zhu577bbe02015-08-28 12:56:43 +0800472
473 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500474}
Rex Zhu577bbe02015-08-28 12:56:43 +0800475
Alex Deucher1f7371b2015-12-02 17:46:21 -0500476static int pp_dpm_powergate_uvd(void *handle, bool gate)
477{
Rex Zhu577bbe02015-08-28 12:56:43 +0800478 struct pp_hwmgr *hwmgr;
479
480 if (handle == NULL)
481 return -EINVAL;
482
483 hwmgr = ((struct pp_instance *)handle)->hwmgr;
484
Rex Zhu7383bcb2016-03-30 11:35:50 +0800485 PP_CHECK_HW(hwmgr);
486
487 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
488 printk(KERN_INFO "%s was not implemented.\n", __func__);
489 return 0;
490 }
Rex Zhu577bbe02015-08-28 12:56:43 +0800491
492 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
493}
494
495static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
496{
497 switch (state) {
498 case POWER_STATE_TYPE_BATTERY:
499 return PP_StateUILabel_Battery;
500 case POWER_STATE_TYPE_BALANCED:
501 return PP_StateUILabel_Balanced;
502 case POWER_STATE_TYPE_PERFORMANCE:
503 return PP_StateUILabel_Performance;
504 default:
505 return PP_StateUILabel_None;
506 }
Alex Deucher1f7371b2015-12-02 17:46:21 -0500507}
508
509int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
510{
Rex Zhu577bbe02015-08-28 12:56:43 +0800511 int ret = 0;
512 struct pp_instance *pp_handle;
513 struct pem_event_data data = { {0} };
514
515 pp_handle = (struct pp_instance *)handle;
516
517 if (pp_handle == NULL)
518 return -EINVAL;
519
520 switch (event_id) {
521 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
522 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
523 break;
524 case AMD_PP_EVENT_ENABLE_USER_STATE:
525 {
526 enum amd_pm_state_type ps;
527
528 if (input == NULL)
529 return -EINVAL;
530 ps = *(unsigned long *)input;
531
532 data.requested_ui_label = power_state_convert(ps);
533 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
Rex Zhudc26a2a2016-02-25 17:16:52 +0800534 break;
Rex Zhu577bbe02015-08-28 12:56:43 +0800535 }
Rex Zhudc26a2a2016-02-25 17:16:52 +0800536 case AMD_PP_EVENT_COMPLETE_INIT:
537 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
538 break;
Rex Zhu577bbe02015-08-28 12:56:43 +0800539 default:
540 break;
541 }
542 return ret;
Alex Deucher1f7371b2015-12-02 17:46:21 -0500543}
Rex Zhu577bbe02015-08-28 12:56:43 +0800544
Alex Deucher1f7371b2015-12-02 17:46:21 -0500545enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
546{
Rex Zhu577bbe02015-08-28 12:56:43 +0800547 struct pp_hwmgr *hwmgr;
548 struct pp_power_state *state;
549
550 if (handle == NULL)
551 return -EINVAL;
552
553 hwmgr = ((struct pp_instance *)handle)->hwmgr;
554
555 if (hwmgr == NULL || hwmgr->current_ps == NULL)
556 return -EINVAL;
557
558 state = hwmgr->current_ps;
559
560 switch (state->classification.ui_label) {
561 case PP_StateUILabel_Battery:
562 return POWER_STATE_TYPE_BATTERY;
563 case PP_StateUILabel_Balanced:
564 return POWER_STATE_TYPE_BALANCED;
565 case PP_StateUILabel_Performance:
566 return POWER_STATE_TYPE_PERFORMANCE;
567 default:
Eric Huangf3898ea2015-12-11 16:24:34 -0500568 if (state->classification.flags & PP_StateClassificationFlag_Boot)
569 return POWER_STATE_TYPE_INTERNAL_BOOT;
570 else
571 return POWER_STATE_TYPE_DEFAULT;
Rex Zhu577bbe02015-08-28 12:56:43 +0800572 }
Alex Deucher1f7371b2015-12-02 17:46:21 -0500573}
Rex Zhu577bbe02015-08-28 12:56:43 +0800574
Alex Deucher1f7371b2015-12-02 17:46:21 -0500575static void
576pp_debugfs_print_current_performance_level(void *handle,
577 struct seq_file *m)
578{
Rex Zhu577bbe02015-08-28 12:56:43 +0800579 struct pp_hwmgr *hwmgr;
580
581 if (handle == NULL)
582 return;
583
584 hwmgr = ((struct pp_instance *)handle)->hwmgr;
585
Rex Zhu7383bcb2016-03-30 11:35:50 +0800586 if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
Rex Zhu577bbe02015-08-28 12:56:43 +0800587 return;
588
Rex Zhu7383bcb2016-03-30 11:35:50 +0800589 if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
590 printk(KERN_INFO "%s was not implemented.\n", __func__);
591 return;
592 }
593
Rex Zhu577bbe02015-08-28 12:56:43 +0800594 hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
Alex Deucher1f7371b2015-12-02 17:46:21 -0500595}
Jammy Zhou3bace352015-07-21 21:18:15 +0800596
Rex Zhucac9a192015-10-16 11:48:21 +0800597static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
598{
599 struct pp_hwmgr *hwmgr;
600
601 if (handle == NULL)
602 return -EINVAL;
603
604 hwmgr = ((struct pp_instance *)handle)->hwmgr;
605
Rex Zhu7383bcb2016-03-30 11:35:50 +0800606 PP_CHECK_HW(hwmgr);
607
608 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
609 printk(KERN_INFO "%s was not implemented.\n", __func__);
610 return 0;
611 }
Rex Zhucac9a192015-10-16 11:48:21 +0800612
613 return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
614}
615
616static int pp_dpm_get_fan_control_mode(void *handle)
617{
618 struct pp_hwmgr *hwmgr;
619
620 if (handle == NULL)
621 return -EINVAL;
622
623 hwmgr = ((struct pp_instance *)handle)->hwmgr;
624
Rex Zhu7383bcb2016-03-30 11:35:50 +0800625 PP_CHECK_HW(hwmgr);
626
627 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
628 printk(KERN_INFO "%s was not implemented.\n", __func__);
629 return 0;
630 }
Rex Zhucac9a192015-10-16 11:48:21 +0800631
632 return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
633}
634
635static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
636{
637 struct pp_hwmgr *hwmgr;
638
639 if (handle == NULL)
640 return -EINVAL;
641
642 hwmgr = ((struct pp_instance *)handle)->hwmgr;
643
Rex Zhu7383bcb2016-03-30 11:35:50 +0800644 PP_CHECK_HW(hwmgr);
645
646 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
647 printk(KERN_INFO "%s was not implemented.\n", __func__);
648 return 0;
649 }
Rex Zhucac9a192015-10-16 11:48:21 +0800650
651 return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
652}
653
654static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
655{
656 struct pp_hwmgr *hwmgr;
657
658 if (handle == NULL)
659 return -EINVAL;
660
661 hwmgr = ((struct pp_instance *)handle)->hwmgr;
662
Rex Zhu7383bcb2016-03-30 11:35:50 +0800663 PP_CHECK_HW(hwmgr);
664
665 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
666 printk(KERN_INFO "%s was not implemented.\n", __func__);
667 return 0;
668 }
Rex Zhucac9a192015-10-16 11:48:21 +0800669
670 return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
671}
672
673static int pp_dpm_get_temperature(void *handle)
674{
675 struct pp_hwmgr *hwmgr;
676
677 if (handle == NULL)
678 return -EINVAL;
679
680 hwmgr = ((struct pp_instance *)handle)->hwmgr;
681
Rex Zhu7383bcb2016-03-30 11:35:50 +0800682 PP_CHECK_HW(hwmgr);
683
684 if (hwmgr->hwmgr_func->get_temperature == NULL) {
685 printk(KERN_INFO "%s was not implemented.\n", __func__);
686 return 0;
687 }
Rex Zhucac9a192015-10-16 11:48:21 +0800688
689 return hwmgr->hwmgr_func->get_temperature(hwmgr);
690}
Rex Zhu577bbe02015-08-28 12:56:43 +0800691
Eric Huangf3898ea2015-12-11 16:24:34 -0500692static int pp_dpm_get_pp_num_states(void *handle,
693 struct pp_states_info *data)
694{
695 struct pp_hwmgr *hwmgr;
696 int i;
697
698 if (!handle)
699 return -EINVAL;
700
701 hwmgr = ((struct pp_instance *)handle)->hwmgr;
702
703 if (hwmgr == NULL || hwmgr->ps == NULL)
704 return -EINVAL;
705
706 data->nums = hwmgr->num_ps;
707
708 for (i = 0; i < hwmgr->num_ps; i++) {
709 struct pp_power_state *state = (struct pp_power_state *)
710 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
711 switch (state->classification.ui_label) {
712 case PP_StateUILabel_Battery:
713 data->states[i] = POWER_STATE_TYPE_BATTERY;
714 break;
715 case PP_StateUILabel_Balanced:
716 data->states[i] = POWER_STATE_TYPE_BALANCED;
717 break;
718 case PP_StateUILabel_Performance:
719 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
720 break;
721 default:
722 if (state->classification.flags & PP_StateClassificationFlag_Boot)
723 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
724 else
725 data->states[i] = POWER_STATE_TYPE_DEFAULT;
726 }
727 }
728
729 return 0;
730}
731
732static int pp_dpm_get_pp_table(void *handle, char **table)
733{
734 struct pp_hwmgr *hwmgr;
735
736 if (!handle)
737 return -EINVAL;
738
739 hwmgr = ((struct pp_instance *)handle)->hwmgr;
740
Rex Zhu7383bcb2016-03-30 11:35:50 +0800741 PP_CHECK_HW(hwmgr);
742
743 if (hwmgr->hwmgr_func->get_pp_table == NULL) {
744 printk(KERN_INFO "%s was not implemented.\n", __func__);
745 return 0;
746 }
Eric Huangf3898ea2015-12-11 16:24:34 -0500747
748 return hwmgr->hwmgr_func->get_pp_table(hwmgr, table);
749}
750
751static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
752{
753 struct pp_hwmgr *hwmgr;
754
755 if (!handle)
756 return -EINVAL;
757
758 hwmgr = ((struct pp_instance *)handle)->hwmgr;
759
Rex Zhu7383bcb2016-03-30 11:35:50 +0800760 PP_CHECK_HW(hwmgr);
761
762 if (hwmgr->hwmgr_func->set_pp_table == NULL) {
763 printk(KERN_INFO "%s was not implemented.\n", __func__);
764 return 0;
765 }
Eric Huangf3898ea2015-12-11 16:24:34 -0500766
767 return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
768}
769
770static int pp_dpm_force_clock_level(void *handle,
Eric Huang56327082016-04-12 14:57:23 -0400771 enum pp_clock_type type, uint32_t mask)
Eric Huangf3898ea2015-12-11 16:24:34 -0500772{
773 struct pp_hwmgr *hwmgr;
774
775 if (!handle)
776 return -EINVAL;
777
778 hwmgr = ((struct pp_instance *)handle)->hwmgr;
779
Rex Zhu7383bcb2016-03-30 11:35:50 +0800780 PP_CHECK_HW(hwmgr);
781
782 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
783 printk(KERN_INFO "%s was not implemented.\n", __func__);
784 return 0;
785 }
Eric Huangf3898ea2015-12-11 16:24:34 -0500786
Eric Huang56327082016-04-12 14:57:23 -0400787 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
Eric Huangf3898ea2015-12-11 16:24:34 -0500788}
789
790static int pp_dpm_print_clock_levels(void *handle,
791 enum pp_clock_type type, char *buf)
792{
793 struct pp_hwmgr *hwmgr;
794
795 if (!handle)
796 return -EINVAL;
797
798 hwmgr = ((struct pp_instance *)handle)->hwmgr;
799
Rex Zhu7383bcb2016-03-30 11:35:50 +0800800 PP_CHECK_HW(hwmgr);
Eric Huangf3898ea2015-12-11 16:24:34 -0500801
Rex Zhu7383bcb2016-03-30 11:35:50 +0800802 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
803 printk(KERN_INFO "%s was not implemented.\n", __func__);
804 return 0;
805 }
Eric Huangf3898ea2015-12-11 16:24:34 -0500806 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
807}
808
Alex Deucher1f7371b2015-12-02 17:46:21 -0500809const struct amd_powerplay_funcs pp_dpm_funcs = {
Rex Zhucac9a192015-10-16 11:48:21 +0800810 .get_temperature = pp_dpm_get_temperature,
Alex Deucher1f7371b2015-12-02 17:46:21 -0500811 .load_firmware = pp_dpm_load_fw,
812 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
813 .force_performance_level = pp_dpm_force_performance_level,
814 .get_performance_level = pp_dpm_get_performance_level,
815 .get_current_power_state = pp_dpm_get_current_power_state,
816 .get_sclk = pp_dpm_get_sclk,
817 .get_mclk = pp_dpm_get_mclk,
818 .powergate_vce = pp_dpm_powergate_vce,
819 .powergate_uvd = pp_dpm_powergate_uvd,
820 .dispatch_tasks = pp_dpm_dispatch_tasks,
821 .print_current_performance_level = pp_debugfs_print_current_performance_level,
Rex Zhucac9a192015-10-16 11:48:21 +0800822 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
823 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
824 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
825 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
Eric Huangf3898ea2015-12-11 16:24:34 -0500826 .get_pp_num_states = pp_dpm_get_pp_num_states,
827 .get_pp_table = pp_dpm_get_pp_table,
828 .set_pp_table = pp_dpm_set_pp_table,
829 .force_clock_level = pp_dpm_force_clock_level,
830 .print_clock_levels = pp_dpm_print_clock_levels,
Alex Deucher1f7371b2015-12-02 17:46:21 -0500831};
832
Jammy Zhouac885b32015-07-21 17:43:02 +0800833static int amd_pp_instance_init(struct amd_pp_init *pp_init,
834 struct amd_powerplay *amd_pp)
835{
836 int ret;
837 struct pp_instance *handle;
838
839 handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
840 if (handle == NULL)
841 return -ENOMEM;
842
Rex Zhua969e162015-12-29 13:56:03 +0800843 handle->pp_valid = PP_VALID;
844
Jammy Zhouac885b32015-07-21 17:43:02 +0800845 ret = smum_init(pp_init, handle);
846 if (ret)
Jammy Zhou3bace352015-07-21 21:18:15 +0800847 goto fail_smum;
848
849 ret = hwmgr_init(pp_init, handle);
850 if (ret)
851 goto fail_hwmgr;
Jammy Zhouac885b32015-07-21 17:43:02 +0800852
Rex Zhue92a0372015-09-23 15:14:54 +0800853 ret = eventmgr_init(handle);
854 if (ret)
855 goto fail_eventmgr;
856
Jammy Zhouac885b32015-07-21 17:43:02 +0800857 amd_pp->pp_handle = handle;
858 return 0;
Jammy Zhou3bace352015-07-21 21:18:15 +0800859
Rex Zhue92a0372015-09-23 15:14:54 +0800860fail_eventmgr:
861 hwmgr_fini(handle->hwmgr);
Jammy Zhou3bace352015-07-21 21:18:15 +0800862fail_hwmgr:
863 smum_fini(handle->smu_mgr);
864fail_smum:
865 kfree(handle);
866 return ret;
Jammy Zhouac885b32015-07-21 17:43:02 +0800867}
868
869static int amd_pp_instance_fini(void *handle)
870{
871 struct pp_instance *instance = (struct pp_instance *)handle;
Rex Zhue92a0372015-09-23 15:14:54 +0800872
Jammy Zhouac885b32015-07-21 17:43:02 +0800873 if (instance == NULL)
874 return -EINVAL;
875
Rex Zhue92a0372015-09-23 15:14:54 +0800876 eventmgr_fini(instance->eventmgr);
877
Jammy Zhou3bace352015-07-21 21:18:15 +0800878 hwmgr_fini(instance->hwmgr);
879
Jammy Zhouac885b32015-07-21 17:43:02 +0800880 smum_fini(instance->smu_mgr);
881
882 kfree(handle);
883 return 0;
884}
885
Alex Deucher1f7371b2015-12-02 17:46:21 -0500886int amd_powerplay_init(struct amd_pp_init *pp_init,
887 struct amd_powerplay *amd_pp)
888{
Jammy Zhouac885b32015-07-21 17:43:02 +0800889 int ret;
890
Alex Deucher1f7371b2015-12-02 17:46:21 -0500891 if (pp_init == NULL || amd_pp == NULL)
892 return -EINVAL;
893
Jammy Zhouac885b32015-07-21 17:43:02 +0800894 ret = amd_pp_instance_init(pp_init, amd_pp);
895
896 if (ret)
897 return ret;
898
Alex Deucher1f7371b2015-12-02 17:46:21 -0500899 amd_pp->ip_funcs = &pp_ip_funcs;
900 amd_pp->pp_funcs = &pp_dpm_funcs;
901
902 return 0;
903}
904
905int amd_powerplay_fini(void *handle)
906{
Jammy Zhouac885b32015-07-21 17:43:02 +0800907 amd_pp_instance_fini(handle);
908
Alex Deucher1f7371b2015-12-02 17:46:21 -0500909 return 0;
910}
Rex Zhu7fb72a12015-11-19 13:35:30 +0800911
912/* export this function to DAL */
913
David Rokhvarg155f1127c2015-12-14 10:51:39 -0500914int amd_powerplay_display_configuration_change(void *handle,
915 const struct amd_pp_display_configuration *display_config)
Rex Zhu7fb72a12015-11-19 13:35:30 +0800916{
917 struct pp_hwmgr *hwmgr;
Rex Zhu7fb72a12015-11-19 13:35:30 +0800918
Rex Zhua969e162015-12-29 13:56:03 +0800919 PP_CHECK((struct pp_instance *)handle);
Rex Zhu7fb72a12015-11-19 13:35:30 +0800920
921 hwmgr = ((struct pp_instance *)handle)->hwmgr;
922
923 phm_store_dal_configuration_data(hwmgr, display_config);
Rex Zhue0b71a72015-12-29 10:25:19 +0800924
Rex Zhu7fb72a12015-11-19 13:35:30 +0800925 return 0;
926}
Vitaly Prosyakc4dd2062015-11-30 16:39:53 -0500927
Vitaly Prosyak1c9a9082015-12-03 10:27:57 -0500928int amd_powerplay_get_display_power_level(void *handle,
Rex Zhu47329132015-12-10 16:49:50 +0800929 struct amd_pp_simple_clock_info *output)
Vitaly Prosyakc4dd2062015-11-30 16:39:53 -0500930{
931 struct pp_hwmgr *hwmgr;
932
Rex Zhua969e162015-12-29 13:56:03 +0800933 PP_CHECK((struct pp_instance *)handle);
934
935 if (output == NULL)
Vitaly Prosyakc4dd2062015-11-30 16:39:53 -0500936 return -EINVAL;
937
938 hwmgr = ((struct pp_instance *)handle)->hwmgr;
939
Vitaly Prosyak1c9a9082015-12-03 10:27:57 -0500940 return phm_get_dal_power_level(hwmgr, output);
Vitaly Prosyakc4dd2062015-11-30 16:39:53 -0500941}
Rex Zhue273b042015-12-07 18:44:23 +0800942
943int amd_powerplay_get_current_clocks(void *handle,
David Rokhvarg155f1127c2015-12-14 10:51:39 -0500944 struct amd_pp_clock_info *clocks)
Rex Zhue273b042015-12-07 18:44:23 +0800945{
946 struct pp_hwmgr *hwmgr;
947 struct amd_pp_simple_clock_info simple_clocks;
948 struct pp_clock_info hw_clocks;
Rex Zhue273b042015-12-07 18:44:23 +0800949
Rex Zhufa9e6992015-12-29 13:56:03 +0800950 PP_CHECK((struct pp_instance *)handle);
951
952 if (clocks == NULL)
Rex Zhue273b042015-12-07 18:44:23 +0800953 return -EINVAL;
954
955 hwmgr = ((struct pp_instance *)handle)->hwmgr;
956
957 phm_get_dal_power_level(hwmgr, &simple_clocks);
958
959 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
960 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
961 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
962 } else {
963 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
964 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
965 }
966
967 clocks->min_engine_clock = hw_clocks.min_eng_clk;
968 clocks->max_engine_clock = hw_clocks.max_eng_clk;
969 clocks->min_memory_clock = hw_clocks.min_mem_clk;
970 clocks->max_memory_clock = hw_clocks.max_mem_clk;
971 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
972 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
973
974 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
975 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
976
977 clocks->max_clocks_state = simple_clocks.level;
978
979 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
980 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
981 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
982 }
983
984 return 0;
985
986}
987
988int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
989{
990 int result = -1;
991
992 struct pp_hwmgr *hwmgr;
993
Rex Zhufa9e6992015-12-29 13:56:03 +0800994 PP_CHECK((struct pp_instance *)handle);
995
996 if (clocks == NULL)
Rex Zhue273b042015-12-07 18:44:23 +0800997 return -EINVAL;
998
999 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1000
1001 result = phm_get_clock_by_type(hwmgr, type, clocks);
1002
1003 return result;
1004}
1005
David Rokhvarg155f1127c2015-12-14 10:51:39 -05001006int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1007 struct amd_pp_simple_clock_info *clocks)
Rex Zhue273b042015-12-07 18:44:23 +08001008{
1009 int result = -1;
Rex Zhue273b042015-12-07 18:44:23 +08001010 struct pp_hwmgr *hwmgr;
1011
Rex Zhufa9e6992015-12-29 13:56:03 +08001012 PP_CHECK((struct pp_instance *)handle);
1013
1014 if (clocks == NULL)
Rex Zhue273b042015-12-07 18:44:23 +08001015 return -EINVAL;
1016
1017 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1018
1019 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1020 result = phm_get_max_high_clocks(hwmgr, clocks);
1021
1022 return result;
1023}
1024