Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 1 | /* |
Grant Likely | c103de2 | 2011-06-04 18:38:28 -0600 | [diff] [blame] | 2 | * U300 GPIO module. |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 3 | * |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 4 | * Copyright (C) 2007-2012 ST-Ericsson AB |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 5 | * License terms: GNU General Public License (GPL) version 2 |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 6 | * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 7 | * Author: Linus Walleij <linus.walleij@linaro.org> |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 9 | */ |
| 10 | #include <linux/module.h> |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 11 | #include <linux/irq.h> |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/io.h> |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 16 | #include <linux/irqdomain.h> |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 17 | #include <linux/clk.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/gpio.h> |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 21 | #include <linux/list.h> |
| 22 | #include <linux/slab.h> |
Linus Walleij | 28a8d14 | 2012-02-09 01:52:22 +0100 | [diff] [blame] | 23 | #include <linux/pinctrl/consumer.h> |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 24 | #include <linux/pinctrl/pinconf-generic.h> |
Linus Walleij | 6517285 | 2012-08-13 10:56:43 +0200 | [diff] [blame] | 25 | #include <linux/platform_data/pinctrl-coh901.h> |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 26 | #include "pinctrl-coh901.h" |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 27 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 28 | #define U300_GPIO_PORT_STRIDE (0x30) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 29 | /* |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 30 | * Control Register 32bit (R/W) |
| 31 | * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores |
| 32 | * gives the number of GPIO pins. |
| 33 | * bit 8-2 (mask 0x000001FC) contains the core version ID. |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 34 | */ |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 35 | #define U300_GPIO_CR (0x00) |
| 36 | #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) |
| 37 | #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) |
| 38 | #define U300_GPIO_PXPDIR (0x04) |
| 39 | #define U300_GPIO_PXPDOR (0x08) |
| 40 | #define U300_GPIO_PXPCR (0x0C) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 41 | #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) |
| 42 | #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) |
| 43 | #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) |
| 44 | #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) |
| 45 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) |
| 46 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) |
| 47 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 48 | #define U300_GPIO_PXPER (0x10) |
| 49 | #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) |
| 50 | #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) |
| 51 | #define U300_GPIO_PXIEV (0x14) |
| 52 | #define U300_GPIO_PXIEN (0x18) |
| 53 | #define U300_GPIO_PXIFR (0x1C) |
| 54 | #define U300_GPIO_PXICR (0x20) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 55 | #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) |
| 56 | #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) |
| 57 | #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) |
| 58 | #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 59 | |
| 60 | /* 8 bits per port, no version has more than 7 ports */ |
| 61 | #define U300_GPIO_PINS_PER_PORT 8 |
| 62 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) |
| 63 | |
| 64 | struct u300_gpio { |
| 65 | struct gpio_chip chip; |
| 66 | struct list_head port_list; |
| 67 | struct clk *clk; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 68 | void __iomem *base; |
| 69 | struct device *dev; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 70 | u32 stride; |
| 71 | /* Register offsets */ |
| 72 | u32 pcr; |
| 73 | u32 dor; |
| 74 | u32 dir; |
| 75 | u32 per; |
| 76 | u32 icr; |
| 77 | u32 ien; |
| 78 | u32 iev; |
| 79 | }; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 80 | |
| 81 | struct u300_gpio_port { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 82 | struct list_head node; |
| 83 | struct u300_gpio *gpio; |
| 84 | char name[8]; |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 85 | struct irq_domain *domain; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 86 | int irq; |
| 87 | int number; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 88 | u8 toggle_edge_mode; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 89 | }; |
| 90 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 91 | /* |
| 92 | * Macro to expand to read a specific register found in the "gpio" |
| 93 | * struct. It requires the struct u300_gpio *gpio variable to exist in |
| 94 | * its context. It calculates the port offset from the given pin |
| 95 | * offset, muliplies by the port stride and adds the register offset |
| 96 | * so it provides a pointer to the desired register. |
| 97 | */ |
| 98 | #define U300_PIN_REG(pin, reg) \ |
| 99 | (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 100 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 101 | /* |
| 102 | * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO |
| 103 | * register. |
| 104 | */ |
| 105 | #define U300_PIN_BIT(pin) \ |
| 106 | (1 << (pin & 0x07)) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 107 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 108 | struct u300_gpio_confdata { |
| 109 | u16 bias_mode; |
| 110 | bool output; |
| 111 | int outval; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 112 | }; |
| 113 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 114 | /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ |
| 115 | #define BS335_GPIO_NUM_PORTS 7 |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 116 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 117 | #define U300_FLOATING_INPUT { \ |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 118 | .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 119 | .output = false, \ |
| 120 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 121 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 122 | #define U300_PULL_UP_INPUT { \ |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 123 | .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 124 | .output = false, \ |
| 125 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 126 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 127 | #define U300_OUTPUT_LOW { \ |
| 128 | .output = true, \ |
| 129 | .outval = 0, \ |
| 130 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 131 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 132 | #define U300_OUTPUT_HIGH { \ |
| 133 | .output = true, \ |
| 134 | .outval = 1, \ |
| 135 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 136 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 137 | /* Initial configuration */ |
Uwe Kleine-König | 122dbe7 | 2012-03-30 22:04:51 +0200 | [diff] [blame] | 138 | static const struct __initconst u300_gpio_confdata |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 139 | bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 140 | /* Port 0, pins 0-7 */ |
| 141 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 142 | U300_FLOATING_INPUT, |
| 143 | U300_OUTPUT_HIGH, |
| 144 | U300_FLOATING_INPUT, |
| 145 | U300_OUTPUT_LOW, |
| 146 | U300_OUTPUT_LOW, |
| 147 | U300_OUTPUT_LOW, |
| 148 | U300_OUTPUT_LOW, |
| 149 | U300_OUTPUT_LOW, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 150 | }, |
| 151 | /* Port 1, pins 0-7 */ |
| 152 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 153 | U300_OUTPUT_LOW, |
| 154 | U300_OUTPUT_LOW, |
| 155 | U300_OUTPUT_LOW, |
| 156 | U300_PULL_UP_INPUT, |
| 157 | U300_FLOATING_INPUT, |
| 158 | U300_OUTPUT_HIGH, |
| 159 | U300_OUTPUT_LOW, |
| 160 | U300_OUTPUT_LOW, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 161 | }, |
| 162 | /* Port 2, pins 0-7 */ |
| 163 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 164 | U300_FLOATING_INPUT, |
| 165 | U300_FLOATING_INPUT, |
| 166 | U300_FLOATING_INPUT, |
| 167 | U300_FLOATING_INPUT, |
| 168 | U300_OUTPUT_LOW, |
| 169 | U300_PULL_UP_INPUT, |
| 170 | U300_OUTPUT_LOW, |
| 171 | U300_PULL_UP_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 172 | }, |
| 173 | /* Port 3, pins 0-7 */ |
| 174 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 175 | U300_PULL_UP_INPUT, |
| 176 | U300_OUTPUT_LOW, |
| 177 | U300_FLOATING_INPUT, |
| 178 | U300_FLOATING_INPUT, |
| 179 | U300_FLOATING_INPUT, |
| 180 | U300_FLOATING_INPUT, |
| 181 | U300_FLOATING_INPUT, |
| 182 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 183 | }, |
| 184 | /* Port 4, pins 0-7 */ |
| 185 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 186 | U300_FLOATING_INPUT, |
| 187 | U300_FLOATING_INPUT, |
| 188 | U300_FLOATING_INPUT, |
| 189 | U300_FLOATING_INPUT, |
| 190 | U300_FLOATING_INPUT, |
| 191 | U300_FLOATING_INPUT, |
| 192 | U300_FLOATING_INPUT, |
| 193 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 194 | }, |
| 195 | /* Port 5, pins 0-7 */ |
| 196 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 197 | U300_FLOATING_INPUT, |
| 198 | U300_FLOATING_INPUT, |
| 199 | U300_FLOATING_INPUT, |
| 200 | U300_FLOATING_INPUT, |
| 201 | U300_FLOATING_INPUT, |
| 202 | U300_FLOATING_INPUT, |
| 203 | U300_FLOATING_INPUT, |
| 204 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 205 | }, |
| 206 | /* Port 6, pind 0-7 */ |
| 207 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 208 | U300_FLOATING_INPUT, |
| 209 | U300_FLOATING_INPUT, |
| 210 | U300_FLOATING_INPUT, |
| 211 | U300_FLOATING_INPUT, |
| 212 | U300_FLOATING_INPUT, |
| 213 | U300_FLOATING_INPUT, |
| 214 | U300_FLOATING_INPUT, |
| 215 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 216 | } |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 217 | }; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 218 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 219 | /** |
| 220 | * to_u300_gpio() - get the pointer to u300_gpio |
| 221 | * @chip: the gpio chip member of the structure u300_gpio |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 222 | */ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 223 | static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 224 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 225 | return container_of(chip, struct u300_gpio, chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 226 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 227 | |
Linus Walleij | b4e3ac7 | 2011-11-16 10:24:39 +0100 | [diff] [blame] | 228 | static int u300_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 229 | { |
| 230 | /* |
| 231 | * Map back to global GPIO space and request muxing, the direction |
| 232 | * parameter does not matter for this controller. |
| 233 | */ |
| 234 | int gpio = chip->base + offset; |
| 235 | |
Linus Walleij | e93bcee | 2012-02-09 07:23:28 +0100 | [diff] [blame] | 236 | return pinctrl_request_gpio(gpio); |
Linus Walleij | b4e3ac7 | 2011-11-16 10:24:39 +0100 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | static void u300_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 240 | { |
| 241 | int gpio = chip->base + offset; |
| 242 | |
Linus Walleij | e93bcee | 2012-02-09 07:23:28 +0100 | [diff] [blame] | 243 | pinctrl_free_gpio(gpio); |
Linus Walleij | b4e3ac7 | 2011-11-16 10:24:39 +0100 | [diff] [blame] | 244 | } |
| 245 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 246 | static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 247 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 248 | struct u300_gpio *gpio = to_u300_gpio(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 249 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 250 | return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 251 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 252 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 253 | static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
Linus Walleij | ee17962 | 2009-09-28 12:36:18 +0100 | [diff] [blame] | 254 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 255 | struct u300_gpio *gpio = to_u300_gpio(chip); |
| 256 | unsigned long flags; |
| 257 | u32 val; |
Linus Walleij | ee17962 | 2009-09-28 12:36:18 +0100 | [diff] [blame] | 258 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 259 | local_irq_save(flags); |
| 260 | |
| 261 | val = readl(U300_PIN_REG(offset, dor)); |
| 262 | if (value) |
| 263 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 264 | else |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 265 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 266 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 267 | local_irq_restore(flags); |
| 268 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 269 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 270 | static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 271 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 272 | struct u300_gpio *gpio = to_u300_gpio(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 273 | unsigned long flags; |
| 274 | u32 val; |
| 275 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 276 | local_irq_save(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 277 | val = readl(U300_PIN_REG(offset, pcr)); |
| 278 | /* Mask out this pin, note 2 bits per setting */ |
| 279 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); |
| 280 | writel(val, U300_PIN_REG(offset, pcr)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 281 | local_irq_restore(flags); |
| 282 | return 0; |
| 283 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 284 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 285 | static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 286 | int value) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 287 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 288 | struct u300_gpio *gpio = to_u300_gpio(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 289 | unsigned long flags; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 290 | u32 oldmode; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 291 | u32 val; |
| 292 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 293 | local_irq_save(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 294 | val = readl(U300_PIN_REG(offset, pcr)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 295 | /* |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 296 | * Drive mode must be set by the special mode set function, set |
| 297 | * push/pull mode by default if no mode has been selected. |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 298 | */ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 299 | oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << |
| 300 | ((offset & 0x07) << 1)); |
| 301 | /* mode = 0 means input, else some mode is already set */ |
| 302 | if (oldmode == 0) { |
| 303 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << |
| 304 | ((offset & 0x07) << 1)); |
| 305 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL |
| 306 | << ((offset & 0x07) << 1)); |
| 307 | writel(val, U300_PIN_REG(offset, pcr)); |
| 308 | } |
| 309 | u300_gpio_set(chip, offset, value); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 310 | local_irq_restore(flags); |
| 311 | return 0; |
| 312 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 313 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 314 | static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 315 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 316 | struct u300_gpio *gpio = to_u300_gpio(chip); |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 317 | int portno = offset >> 3; |
| 318 | struct u300_gpio_port *port = NULL; |
| 319 | struct list_head *p; |
| 320 | int retirq; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 321 | |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 322 | list_for_each(p, &gpio->port_list) { |
| 323 | port = list_entry(p, struct u300_gpio_port, node); |
| 324 | if (port->number == portno) |
| 325 | break; |
| 326 | } |
| 327 | if (port == NULL) { |
| 328 | dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n", |
| 329 | offset); |
| 330 | return -EINVAL; |
| 331 | } |
| 332 | |
| 333 | /* |
| 334 | * The local hwirqs on the port are the lower three bits, there |
| 335 | * are exactly 8 IRQs per port since they are 8-bit |
| 336 | */ |
| 337 | retirq = irq_find_mapping(port->domain, (offset & 0x7)); |
| 338 | |
| 339 | dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n", |
| 340 | offset, retirq, port->number); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 341 | return retirq; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 342 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 343 | |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 344 | /* Returning -EINVAL means "supported but not available" */ |
| 345 | int u300_gpio_config_get(struct gpio_chip *chip, |
| 346 | unsigned offset, |
| 347 | unsigned long *config) |
| 348 | { |
| 349 | struct u300_gpio *gpio = to_u300_gpio(chip); |
| 350 | enum pin_config_param param = (enum pin_config_param) *config; |
| 351 | bool biasmode; |
| 352 | u32 drmode; |
| 353 | |
| 354 | /* One bit per pin, clamp to bool range */ |
| 355 | biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); |
| 356 | |
| 357 | /* Mask out the two bits for this pin and shift to bits 0,1 */ |
| 358 | drmode = readl(U300_PIN_REG(offset, pcr)); |
| 359 | drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); |
| 360 | drmode >>= ((offset & 0x07) << 1); |
| 361 | |
| 362 | switch(param) { |
| 363 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
| 364 | *config = 0; |
| 365 | if (biasmode) |
| 366 | return 0; |
| 367 | else |
| 368 | return -EINVAL; |
| 369 | break; |
| 370 | case PIN_CONFIG_BIAS_PULL_UP: |
| 371 | *config = 0; |
| 372 | if (!biasmode) |
| 373 | return 0; |
| 374 | else |
| 375 | return -EINVAL; |
| 376 | break; |
| 377 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 378 | *config = 0; |
| 379 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) |
| 380 | return 0; |
| 381 | else |
| 382 | return -EINVAL; |
| 383 | break; |
| 384 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 385 | *config = 0; |
| 386 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) |
| 387 | return 0; |
| 388 | else |
| 389 | return -EINVAL; |
| 390 | break; |
| 391 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
| 392 | *config = 0; |
| 393 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) |
| 394 | return 0; |
| 395 | else |
| 396 | return -EINVAL; |
| 397 | break; |
| 398 | default: |
| 399 | break; |
| 400 | } |
| 401 | return -ENOTSUPP; |
| 402 | } |
| 403 | |
| 404 | int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, |
| 405 | enum pin_config_param param) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 406 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 407 | struct u300_gpio *gpio = to_u300_gpio(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 408 | unsigned long flags; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 409 | u32 val; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 410 | |
| 411 | local_irq_save(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 412 | switch (param) { |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 413 | case PIN_CONFIG_BIAS_DISABLE: |
| 414 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 415 | val = readl(U300_PIN_REG(offset, per)); |
| 416 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); |
| 417 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 418 | case PIN_CONFIG_BIAS_PULL_UP: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 419 | val = readl(U300_PIN_REG(offset, per)); |
| 420 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); |
| 421 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 422 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 423 | val = readl(U300_PIN_REG(offset, pcr)); |
| 424 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK |
| 425 | << ((offset & 0x07) << 1)); |
| 426 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL |
| 427 | << ((offset & 0x07) << 1)); |
| 428 | writel(val, U300_PIN_REG(offset, pcr)); |
| 429 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 430 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 431 | val = readl(U300_PIN_REG(offset, pcr)); |
| 432 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK |
| 433 | << ((offset & 0x07) << 1)); |
| 434 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN |
| 435 | << ((offset & 0x07) << 1)); |
| 436 | writel(val, U300_PIN_REG(offset, pcr)); |
| 437 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 438 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 439 | val = readl(U300_PIN_REG(offset, pcr)); |
| 440 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK |
| 441 | << ((offset & 0x07) << 1)); |
| 442 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE |
| 443 | << ((offset & 0x07) << 1)); |
| 444 | writel(val, U300_PIN_REG(offset, pcr)); |
| 445 | break; |
| 446 | default: |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 447 | local_irq_restore(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 448 | dev_err(gpio->dev, "illegal configuration requested\n"); |
| 449 | return -EINVAL; |
| 450 | } |
| 451 | local_irq_restore(flags); |
| 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | static struct gpio_chip u300_gpio_chip = { |
| 456 | .label = "u300-gpio-chip", |
| 457 | .owner = THIS_MODULE, |
Linus Walleij | b4e3ac7 | 2011-11-16 10:24:39 +0100 | [diff] [blame] | 458 | .request = u300_gpio_request, |
| 459 | .free = u300_gpio_free, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 460 | .get = u300_gpio_get, |
| 461 | .set = u300_gpio_set, |
| 462 | .direction_input = u300_gpio_direction_input, |
| 463 | .direction_output = u300_gpio_direction_output, |
| 464 | .to_irq = u300_gpio_to_irq, |
| 465 | }; |
| 466 | |
| 467 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) |
| 468 | { |
| 469 | u32 val; |
| 470 | |
| 471 | val = readl(U300_PIN_REG(offset, icr)); |
| 472 | /* Set mode depending on state */ |
| 473 | if (u300_gpio_get(&gpio->chip, offset)) { |
| 474 | /* High now, let's trigger on falling edge next then */ |
| 475 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 476 | dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", |
| 477 | offset); |
| 478 | } else { |
| 479 | /* Low now, let's trigger on rising edge next then */ |
| 480 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 481 | dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", |
| 482 | offset); |
| 483 | } |
| 484 | } |
| 485 | |
| 486 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
| 487 | { |
| 488 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
| 489 | struct u300_gpio *gpio = port->gpio; |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 490 | int offset = (port->number << 3) + d->hwirq; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 491 | u32 val; |
| 492 | |
| 493 | if ((trigger & IRQF_TRIGGER_RISING) && |
| 494 | (trigger & IRQF_TRIGGER_FALLING)) { |
| 495 | /* |
| 496 | * The GPIO block can only trigger on falling OR rising edges, |
| 497 | * not both. So we need to toggle the mode whenever the pin |
| 498 | * goes from one state to the other with a special state flag |
| 499 | */ |
| 500 | dev_dbg(gpio->dev, |
| 501 | "trigger on both rising and falling edge on pin %d\n", |
| 502 | offset); |
| 503 | port->toggle_edge_mode |= U300_PIN_BIT(offset); |
| 504 | u300_toggle_trigger(gpio, offset); |
| 505 | } else if (trigger & IRQF_TRIGGER_RISING) { |
| 506 | dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", |
| 507 | offset); |
| 508 | val = readl(U300_PIN_REG(offset, icr)); |
| 509 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 510 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); |
| 511 | } else if (trigger & IRQF_TRIGGER_FALLING) { |
| 512 | dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", |
| 513 | offset); |
| 514 | val = readl(U300_PIN_REG(offset, icr)); |
| 515 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 516 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 517 | } |
| 518 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 519 | return 0; |
| 520 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 521 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 522 | static void u300_gpio_irq_enable(struct irq_data *d) |
| 523 | { |
| 524 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
| 525 | struct u300_gpio *gpio = port->gpio; |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 526 | int offset = (port->number << 3) + d->hwirq; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 527 | u32 val; |
| 528 | unsigned long flags; |
| 529 | |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 530 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", |
| 531 | d->hwirq, port->name, offset); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 532 | local_irq_save(flags); |
| 533 | val = readl(U300_PIN_REG(offset, ien)); |
| 534 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); |
| 535 | local_irq_restore(flags); |
| 536 | } |
| 537 | |
| 538 | static void u300_gpio_irq_disable(struct irq_data *d) |
| 539 | { |
| 540 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
| 541 | struct u300_gpio *gpio = port->gpio; |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 542 | int offset = (port->number << 3) + d->hwirq; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 543 | u32 val; |
| 544 | unsigned long flags; |
| 545 | |
| 546 | local_irq_save(flags); |
| 547 | val = readl(U300_PIN_REG(offset, ien)); |
| 548 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); |
| 549 | local_irq_restore(flags); |
| 550 | } |
| 551 | |
| 552 | static struct irq_chip u300_gpio_irqchip = { |
| 553 | .name = "u300-gpio-irqchip", |
| 554 | .irq_enable = u300_gpio_irq_enable, |
| 555 | .irq_disable = u300_gpio_irq_disable, |
| 556 | .irq_set_type = u300_gpio_irq_type, |
| 557 | |
| 558 | }; |
| 559 | |
| 560 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
| 561 | { |
| 562 | struct u300_gpio_port *port = irq_get_handler_data(irq); |
| 563 | struct u300_gpio *gpio = port->gpio; |
| 564 | int pinoffset = port->number << 3; /* get the right stride */ |
| 565 | unsigned long val; |
| 566 | |
| 567 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
| 568 | /* Read event register */ |
| 569 | val = readl(U300_PIN_REG(pinoffset, iev)); |
| 570 | /* Mask relevant bits */ |
| 571 | val &= 0xFFU; /* 8 bits per port */ |
| 572 | /* ACK IRQ (clear event) */ |
| 573 | writel(val, U300_PIN_REG(pinoffset, iev)); |
| 574 | |
| 575 | /* Call IRQ handler */ |
| 576 | if (val != 0) { |
| 577 | int irqoffset; |
| 578 | |
| 579 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 580 | int pin_irq = irq_find_mapping(port->domain, irqoffset); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 581 | int offset = pinoffset + irqoffset; |
| 582 | |
| 583 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", |
| 584 | pin_irq, offset); |
| 585 | generic_handle_irq(pin_irq); |
| 586 | /* |
| 587 | * Triggering IRQ on both rising and falling edge |
| 588 | * needs mockery |
| 589 | */ |
| 590 | if (port->toggle_edge_mode & U300_PIN_BIT(offset)) |
| 591 | u300_toggle_trigger(gpio, offset); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 592 | } |
| 593 | } |
| 594 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 595 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 596 | } |
| 597 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 598 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
| 599 | int offset, |
| 600 | const struct u300_gpio_confdata *conf) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 601 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 602 | /* Set mode: input or output */ |
| 603 | if (conf->output) { |
| 604 | u300_gpio_direction_output(&gpio->chip, offset, conf->outval); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 605 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 606 | /* Deactivate bias mode for output */ |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 607 | u300_gpio_config_set(&gpio->chip, offset, |
| 608 | PIN_CONFIG_BIAS_HIGH_IMPEDANCE); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 609 | |
| 610 | /* Set drive mode for output */ |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 611 | u300_gpio_config_set(&gpio->chip, offset, |
| 612 | PIN_CONFIG_DRIVE_PUSH_PULL); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 613 | |
| 614 | dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", |
| 615 | offset, conf->outval); |
| 616 | } else { |
| 617 | u300_gpio_direction_input(&gpio->chip, offset); |
| 618 | |
| 619 | /* Always set output low on input pins */ |
| 620 | u300_gpio_set(&gpio->chip, offset, 0); |
| 621 | |
| 622 | /* Set bias mode for input */ |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 623 | u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 624 | |
| 625 | dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", |
| 626 | offset, conf->bias_mode); |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, |
| 631 | struct u300_gpio_platform *plat) |
| 632 | { |
| 633 | int i, j; |
| 634 | |
| 635 | /* Write default config and values to all pins */ |
| 636 | for (i = 0; i < plat->ports; i++) { |
| 637 | for (j = 0; j < 8; j++) { |
| 638 | const struct u300_gpio_confdata *conf; |
| 639 | int offset = (i*8) + j; |
| 640 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 641 | conf = &bs335_gpio_config[i][j]; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 642 | u300_gpio_init_pin(gpio, offset, conf); |
| 643 | } |
| 644 | } |
| 645 | } |
| 646 | |
| 647 | static inline void u300_gpio_free_ports(struct u300_gpio *gpio) |
| 648 | { |
| 649 | struct u300_gpio_port *port; |
| 650 | struct list_head *p, *n; |
| 651 | |
| 652 | list_for_each_safe(p, n, &gpio->port_list) { |
| 653 | port = list_entry(p, struct u300_gpio_port, node); |
| 654 | list_del(&port->node); |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 655 | if (port->domain) |
| 656 | irq_domain_remove(port->domain); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 657 | kfree(port); |
| 658 | } |
| 659 | } |
| 660 | |
Linus Walleij | 387923c | 2012-11-20 14:28:07 +0100 | [diff] [blame] | 661 | /* |
| 662 | * Here we map a GPIO in the local gpio_chip pin space to a pin in |
| 663 | * the local pinctrl pin space. The pin controller used is |
| 664 | * pinctrl-u300. |
| 665 | */ |
| 666 | struct coh901_pinpair { |
| 667 | unsigned int offset; |
| 668 | unsigned int pin_base; |
| 669 | }; |
| 670 | |
| 671 | #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } |
| 672 | |
| 673 | static struct coh901_pinpair coh901_pintable[] = { |
| 674 | COH901_PINRANGE(10, 426), |
| 675 | COH901_PINRANGE(11, 180), |
| 676 | COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ |
| 677 | COH901_PINRANGE(13, 179), |
| 678 | COH901_PINRANGE(14, 178), |
| 679 | COH901_PINRANGE(16, 194), |
| 680 | COH901_PINRANGE(17, 193), |
| 681 | COH901_PINRANGE(18, 192), |
| 682 | COH901_PINRANGE(19, 191), |
| 683 | COH901_PINRANGE(20, 186), |
| 684 | COH901_PINRANGE(21, 185), |
| 685 | COH901_PINRANGE(22, 184), |
| 686 | COH901_PINRANGE(23, 183), |
| 687 | COH901_PINRANGE(24, 182), |
| 688 | COH901_PINRANGE(25, 181), |
| 689 | }; |
| 690 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 691 | static int __init u300_gpio_probe(struct platform_device *pdev) |
| 692 | { |
| 693 | struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); |
| 694 | struct u300_gpio *gpio; |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 695 | struct resource *memres; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 696 | int err = 0; |
| 697 | int portno; |
| 698 | u32 val; |
| 699 | u32 ifr; |
| 700 | int i; |
| 701 | |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 702 | gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); |
| 703 | if (gpio == NULL) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 704 | return -ENOMEM; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 705 | |
| 706 | gpio->chip = u300_gpio_chip; |
| 707 | gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 708 | gpio->chip.dev = &pdev->dev; |
| 709 | gpio->chip.base = plat->gpio_base; |
| 710 | gpio->dev = &pdev->dev; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 711 | |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 712 | memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 713 | if (!memres) { |
| 714 | dev_err(gpio->dev, "could not get GPIO memory resource\n"); |
| 715 | return -ENODEV; |
| 716 | } |
| 717 | |
Thierry Reding | 9e0c1fb | 2013-01-21 11:09:14 +0100 | [diff] [blame^] | 718 | gpio->base = devm_ioremap_resource(&pdev->dev, memres); |
| 719 | if (IS_ERR(gpio->base)) |
| 720 | return PTR_ERR(gpio->base); |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 721 | |
| 722 | gpio->clk = devm_clk_get(gpio->dev, NULL); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 723 | if (IS_ERR(gpio->clk)) { |
| 724 | err = PTR_ERR(gpio->clk); |
| 725 | dev_err(gpio->dev, "could not get GPIO clock\n"); |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 726 | return err; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 727 | } |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 728 | |
Linus Walleij | 27e8461 | 2012-06-19 23:36:15 +0200 | [diff] [blame] | 729 | err = clk_prepare_enable(gpio->clk); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 730 | if (err) { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 731 | dev_err(gpio->dev, "could not enable GPIO clock\n"); |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 732 | return err; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 733 | } |
| 734 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 735 | dev_info(gpio->dev, |
| 736 | "initializing GPIO Controller COH 901 571/3\n"); |
| 737 | gpio->stride = U300_GPIO_PORT_STRIDE; |
| 738 | gpio->pcr = U300_GPIO_PXPCR; |
| 739 | gpio->dor = U300_GPIO_PXPDOR; |
| 740 | gpio->dir = U300_GPIO_PXPDIR; |
| 741 | gpio->per = U300_GPIO_PXPER; |
| 742 | gpio->icr = U300_GPIO_PXICR; |
| 743 | gpio->ien = U300_GPIO_PXIEN; |
| 744 | gpio->iev = U300_GPIO_PXIEV; |
| 745 | ifr = U300_GPIO_PXIFR; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 746 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 747 | val = readl(gpio->base + U300_GPIO_CR); |
| 748 | dev_info(gpio->dev, "COH901571/3 block version: %d, " \ |
| 749 | "number of cores: %d totalling %d pins\n", |
| 750 | ((val & 0x000001FC) >> 2), |
| 751 | ((val & 0x0000FE00) >> 9), |
| 752 | ((val & 0x0000FE00) >> 9) * 8); |
| 753 | writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, |
| 754 | gpio->base + U300_GPIO_CR); |
| 755 | u300_gpio_init_coh901571(gpio, plat); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 756 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 757 | /* Add each port with its IRQ separately */ |
| 758 | INIT_LIST_HEAD(&gpio->port_list); |
| 759 | for (portno = 0 ; portno < plat->ports; portno++) { |
| 760 | struct u300_gpio_port *port = |
| 761 | kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); |
| 762 | |
| 763 | if (!port) { |
| 764 | dev_err(gpio->dev, "out of memory\n"); |
| 765 | err = -ENOMEM; |
| 766 | goto err_no_port; |
| 767 | } |
| 768 | |
| 769 | snprintf(port->name, 8, "gpio%d", portno); |
| 770 | port->number = portno; |
| 771 | port->gpio = gpio; |
| 772 | |
| 773 | port->irq = platform_get_irq_byname(pdev, |
| 774 | port->name); |
| 775 | |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 776 | dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 777 | port->name); |
| 778 | |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 779 | port->domain = irq_domain_add_linear(pdev->dev.of_node, |
| 780 | U300_GPIO_PINS_PER_PORT, |
| 781 | &irq_domain_simple_ops, |
| 782 | port); |
Axel Lin | 8035720 | 2012-11-14 00:16:14 +0800 | [diff] [blame] | 783 | if (!port->domain) { |
| 784 | err = -ENOMEM; |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 785 | goto err_no_domain; |
Axel Lin | 8035720 | 2012-11-14 00:16:14 +0800 | [diff] [blame] | 786 | } |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 787 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 788 | irq_set_chained_handler(port->irq, u300_gpio_irq_handler); |
| 789 | irq_set_handler_data(port->irq, port); |
| 790 | |
| 791 | /* For each GPIO pin set the unique IRQ handler */ |
| 792 | for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) { |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 793 | int irqno = irq_create_mapping(port->domain, i); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 794 | |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 795 | dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n", |
| 796 | gpio->chip.base + (port->number << 3) + i, |
| 797 | port->name, irqno); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 798 | irq_set_chip_and_handler(irqno, &u300_gpio_irqchip, |
| 799 | handle_simple_irq); |
| 800 | set_irq_flags(irqno, IRQF_VALID); |
| 801 | irq_set_chip_data(irqno, port); |
| 802 | } |
| 803 | |
| 804 | /* Turns off irq force (test register) for this port */ |
| 805 | writel(0x0, gpio->base + portno * gpio->stride + ifr); |
| 806 | |
| 807 | list_add_tail(&port->node, &gpio->port_list); |
| 808 | } |
| 809 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
| 810 | |
| 811 | err = gpiochip_add(&gpio->chip); |
| 812 | if (err) { |
| 813 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); |
| 814 | goto err_no_chip; |
| 815 | } |
| 816 | |
Linus Walleij | 387923c | 2012-11-20 14:28:07 +0100 | [diff] [blame] | 817 | /* |
| 818 | * Add pinctrl pin ranges, the pin controller must be registered |
| 819 | * at this point |
| 820 | */ |
| 821 | for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { |
| 822 | struct coh901_pinpair *p = &coh901_pintable[i]; |
| 823 | |
| 824 | err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", |
| 825 | p->offset, p->pin_base, 1); |
| 826 | if (err) |
| 827 | goto err_no_range; |
| 828 | } |
| 829 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 830 | platform_set_drvdata(pdev, gpio); |
| 831 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 832 | return 0; |
| 833 | |
Linus Walleij | 387923c | 2012-11-20 14:28:07 +0100 | [diff] [blame] | 834 | err_no_range: |
Linus Walleij | 128a06d | 2012-02-21 14:31:45 +0100 | [diff] [blame] | 835 | err = gpiochip_remove(&gpio->chip); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 836 | err_no_chip: |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 837 | err_no_domain: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 838 | err_no_port: |
| 839 | u300_gpio_free_ports(gpio); |
Linus Walleij | 27e8461 | 2012-06-19 23:36:15 +0200 | [diff] [blame] | 840 | clk_disable_unprepare(gpio->clk); |
Axel Lin | 8035720 | 2012-11-14 00:16:14 +0800 | [diff] [blame] | 841 | dev_err(&pdev->dev, "module ERROR:%d\n", err); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 842 | return err; |
| 843 | } |
| 844 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 845 | static int __exit u300_gpio_remove(struct platform_device *pdev) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 846 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 847 | struct u300_gpio *gpio = platform_get_drvdata(pdev); |
| 848 | int err; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 849 | |
| 850 | /* Turn off the GPIO block */ |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 851 | writel(0x00000000U, gpio->base + U300_GPIO_CR); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 852 | |
| 853 | err = gpiochip_remove(&gpio->chip); |
| 854 | if (err < 0) { |
| 855 | dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); |
| 856 | return err; |
| 857 | } |
| 858 | u300_gpio_free_ports(gpio); |
Linus Walleij | 27e8461 | 2012-06-19 23:36:15 +0200 | [diff] [blame] | 859 | clk_disable_unprepare(gpio->clk); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 860 | platform_set_drvdata(pdev, NULL); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 861 | return 0; |
| 862 | } |
| 863 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 864 | static struct platform_driver u300_gpio_driver = { |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 865 | .driver = { |
| 866 | .name = "u300-gpio", |
| 867 | }, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 868 | .remove = __exit_p(u300_gpio_remove), |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 869 | }; |
| 870 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 871 | static int __init u300_gpio_init(void) |
| 872 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 873 | return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 874 | } |
| 875 | |
| 876 | static void __exit u300_gpio_exit(void) |
| 877 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 878 | platform_driver_unregister(&u300_gpio_driver); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 879 | } |
| 880 | |
| 881 | arch_initcall(u300_gpio_init); |
| 882 | module_exit(u300_gpio_exit); |
| 883 | |
| 884 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 885 | MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 886 | MODULE_LICENSE("GPL"); |