blob: 0ad84b6cd0394be2876610738cce48ba1ac20e8a [file] [log] [blame]
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02001/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
Nicolas Ferre21f81872012-02-11 15:41:40 +010025 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010030 tcb0 = &tcb0;
31 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020032 i2c0 = &i2c0;
33 i2c1 = &i2c1;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020034 };
35 cpus {
36 cpu@0 {
37 compatible = "arm,arm926ejs";
38 };
39 };
40
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020041 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020042 reg = <0x70000000 0x10000000>;
43 };
44
45 ahb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 apb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020058 #interrupt-cells = <3>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020059 compatible = "atmel,at91rm9200-aic";
60 interrupt-controller;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020061 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080062 atmel,external-irqs = <31>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020063 };
64
Jean-Christophe PLAGNIOL-VILLARDa7776ec2012-03-02 20:54:37 +080065 ramc0: ramc@ffffe400 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe400 0x200
68 0xffffe600 0x200>;
69 };
70
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080071 pmc: pmc@fffffc00 {
72 compatible = "atmel,at91rm9200-pmc";
73 reg = <0xfffffc00 0x100>;
74 };
75
Jean-Christophe PLAGNIOL-VILLARDc8082d32012-03-03 03:16:27 +080076 rstc@fffffd00 {
77 compatible = "atmel,at91sam9g45-rstc";
78 reg = <0xfffffd00 0x10>;
79 };
80
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010081 pit: timer@fffffd30 {
82 compatible = "atmel,at91sam9260-pit";
83 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020084 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010085 };
86
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010087
Jean-Christophe PLAGNIOL-VILLARD82015c42012-03-02 21:01:00 +080088 shdwc@fffffd10 {
89 compatible = "atmel,at91sam9rl-shdwc";
90 reg = <0xfffffd10 0x10>;
91 };
92
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010093 tcb0: timer@fff7c000 {
94 compatible = "atmel,at91rm9200-tcb";
95 reg = <0xfff7c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020096 interrupts = <18 4 0>;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +010097 };
98
99 tcb1: timer@fffd4000 {
100 compatible = "atmel,at91rm9200-tcb";
101 reg = <0xfffd4000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200102 interrupts = <18 4 0>;
Nicolas Ferre3a61a5d2012-01-19 10:13:40 +0100103 };
104
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200105 dma: dma-controller@ffffec00 {
106 compatible = "atmel,at91sam9g45-dma";
107 reg = <0xffffec00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200108 interrupts = <21 4 0>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200109 };
110
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800111 pinctrl@fffff200 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
115 ranges = <0xfffff200 0xfffff200 0xa00>;
Nicolas Ferre21f81872012-02-11 15:41:40 +0100116
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800117 atmel,mux-mask = <
118 /* A B */
119 0xffffffff 0xffc003ff /* pioA */
120 0xffffffff 0x800f8f00 /* pioB */
121 0xffffffff 0x00000e00 /* pioC */
122 0xffffffff 0xff0c1381 /* pioD */
123 0xffffffff 0x81ffff81 /* pioE */
124 >;
125
126 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800127 dbgu {
128 pinctrl_dbgu: dbgu-0 {
129 atmel,pins =
130 <1 12 0x1 0x0 /* PB12 periph A */
131 1 13 0x1 0x0>; /* PB13 periph A */
132 };
133 };
134
135 uart0 {
136 pinctrl_uart0: uart0-0 {
137 atmel,pins =
138 <1 19 0x1 0x1 /* PB19 periph A with pullup */
139 1 18 0x1 0x0>; /* PB18 periph A */
140 };
141
142 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
143 atmel,pins =
144 <1 17 0x2 0x0 /* PB17 periph B */
145 1 15 0x2 0x0>; /* PB15 periph B */
146 };
147 };
148
149 uart1 {
150 pinctrl_uart1: uart1-0 {
151 atmel,pins =
152 <1 4 0x1 0x1 /* PB4 periph A with pullup */
153 1 5 0x1 0x0>; /* PB5 periph A */
154 };
155
156 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
157 atmel,pins =
158 <3 16 0x1 0x0 /* PD16 periph A */
159 3 17 0x1 0x0>; /* PD17 periph A */
160 };
161 };
162
163 uart2 {
164 pinctrl_uart2: uart2-0 {
165 atmel,pins =
166 <1 6 0x1 0x1 /* PB6 periph A with pullup */
167 1 7 0x1 0x0>; /* PB7 periph A */
168 };
169
170 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
171 atmel,pins =
172 <2 9 0x2 0x0 /* PC9 periph B */
173 2 11 0x2 0x0>; /* PC11 periph B */
174 };
175 };
176
177 uart3 {
178 pinctrl_uart3: uart3-0 {
179 atmel,pins =
180 <1 8 0x1 0x1 /* PB9 periph A with pullup */
181 1 9 0x1 0x0>; /* PB8 periph A */
182 };
183
184 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
185 atmel,pins =
186 <0 23 0x2 0x0 /* PA23 periph B */
187 0 24 0x2 0x0>; /* PA24 periph B */
188 };
189 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800190
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800191 nand {
192 pinctrl_nand: nand-0 {
193 atmel,pins =
194 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
195 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
196 };
197 };
198
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800199 macb {
200 pinctrl_macb_rmii: macb_rmii-0 {
201 atmel,pins =
202 <0 10 0x1 0x0 /* PA10 periph A */
203 0 11 0x1 0x0 /* PA11 periph A */
204 0 12 0x1 0x0 /* PA12 periph A */
205 0 13 0x1 0x0 /* PA13 periph A */
206 0 14 0x1 0x0 /* PA14 periph A */
207 0 15 0x1 0x0 /* PA15 periph A */
208 0 16 0x1 0x0 /* PA16 periph A */
209 0 17 0x1 0x0 /* PA17 periph A */
210 0 18 0x1 0x0 /* PA18 periph A */
211 0 19 0x1 0x0>; /* PA19 periph A */
212 };
213
214 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
215 atmel,pins =
216 <0 6 0x2 0x0 /* PA6 periph B */
217 0 7 0x2 0x0 /* PA7 periph B */
218 0 8 0x2 0x0 /* PA8 periph B */
219 0 9 0x2 0x0 /* PA9 periph B */
220 0 27 0x2 0x0 /* PA27 periph B */
221 0 28 0x2 0x0 /* PA28 periph B */
222 0 29 0x2 0x0 /* PA29 periph B */
223 0 30 0x2 0x0>; /* PA30 periph B */
224 };
225 };
226
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800227 pioA: gpio@fffff200 {
228 compatible = "atmel,at91rm9200-gpio";
229 reg = <0xfffff200 0x200>;
230 interrupts = <2 4 1>;
231 #gpio-cells = <2>;
232 gpio-controller;
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100236
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800237 pioB: gpio@fffff400 {
238 compatible = "atmel,at91rm9200-gpio";
239 reg = <0xfffff400 0x200>;
240 interrupts = <3 4 1>;
241 #gpio-cells = <2>;
242 gpio-controller;
243 interrupt-controller;
244 #interrupt-cells = <2>;
245 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100246
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800247 pioC: gpio@fffff600 {
248 compatible = "atmel,at91rm9200-gpio";
249 reg = <0xfffff600 0x200>;
250 interrupts = <4 4 1>;
251 #gpio-cells = <2>;
252 gpio-controller;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100256
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800257 pioD: gpio@fffff800 {
258 compatible = "atmel,at91rm9200-gpio";
259 reg = <0xfffff800 0x200>;
260 interrupts = <5 4 1>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
266
267 pioE: gpio@fffffa00 {
268 compatible = "atmel,at91rm9200-gpio";
269 reg = <0xfffffa00 0x200>;
270 interrupts = <5 4 1>;
271 #gpio-cells = <2>;
272 gpio-controller;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
Nicolas Ferre21f81872012-02-11 15:41:40 +0100276 };
277
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200278 dbgu: serial@ffffee00 {
279 compatible = "atmel,at91sam9260-usart";
280 reg = <0xffffee00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200281 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_dbgu>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200284 status = "disabled";
285 };
286
287 usart0: serial@fff8c000 {
288 compatible = "atmel,at91sam9260-usart";
289 reg = <0xfff8c000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200290 interrupts = <7 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200291 atmel,use-dma-rx;
292 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_uart0>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200295 status = "disabled";
296 };
297
298 usart1: serial@fff90000 {
299 compatible = "atmel,at91sam9260-usart";
300 reg = <0xfff90000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200301 interrupts = <8 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200302 atmel,use-dma-rx;
303 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart1>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200306 status = "disabled";
307 };
308
309 usart2: serial@fff94000 {
310 compatible = "atmel,at91sam9260-usart";
311 reg = <0xfff94000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200312 interrupts = <9 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200313 atmel,use-dma-rx;
314 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_uart2>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200317 status = "disabled";
318 };
319
320 usart3: serial@fff98000 {
321 compatible = "atmel,at91sam9260-usart";
322 reg = <0xfff98000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200323 interrupts = <10 4 5>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200324 atmel,use-dma-rx;
325 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_uart3>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200328 status = "disabled";
329 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100330
331 macb0: ethernet@fffbc000 {
332 compatible = "cdns,at32ap7000-macb", "cdns,macb";
333 reg = <0xfffbc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200334 interrupts = <25 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_macb_rmii>;
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +0100337 status = "disabled";
338 };
Maxime Ripard93b298b2012-05-11 15:35:38 +0200339
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200340 i2c0: i2c@fff84000 {
341 compatible = "atmel,at91sam9g10-i2c";
342 reg = <0xfff84000 0x100>;
343 interrupts = <12 4 6>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 status = "disabled";
347 };
348
349 i2c1: i2c@fff88000 {
350 compatible = "atmel,at91sam9g10-i2c";
351 reg = <0xfff88000 0x100>;
352 interrupts = <13 4 6>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 status = "disabled";
356 };
357
Maxime Ripard93b298b2012-05-11 15:35:38 +0200358 adc0: adc@fffb0000 {
359 compatible = "atmel,at91sam9260-adc";
360 reg = <0xfffb0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200361 interrupts = <20 4 0>;
Maxime Ripard93b298b2012-05-11 15:35:38 +0200362 atmel,adc-use-external-triggers;
363 atmel,adc-channels-used = <0xff>;
364 atmel,adc-vref = <3300>;
365 atmel,adc-num-channels = <8>;
366 atmel,adc-startup-time = <40>;
367 atmel,adc-channel-base = <0x30>;
368 atmel,adc-drdy-mask = <0x10000>;
369 atmel,adc-status-register = <0x1c>;
370 atmel,adc-trigger-register = <0x08>;
371
372 trigger@0 {
373 trigger-name = "external-rising";
374 trigger-value = <0x1>;
375 trigger-external;
376 };
377 trigger@1 {
378 trigger-name = "external-falling";
379 trigger-value = <0x2>;
380 trigger-external;
381 };
382
383 trigger@2 {
384 trigger-name = "external-any";
385 trigger-value = <0x3>;
386 trigger-external;
387 };
388
389 trigger@3 {
390 trigger-name = "continuous";
391 trigger-value = <0x6>;
392 };
393 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200394 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800395
396 nand0: nand@40000000 {
397 compatible = "atmel,at91rm9200-nand";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 reg = <0x40000000 0x10000000
401 0xffffe200 0x200
402 >;
403 atmel,nand-addr-offset = <21>;
404 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800407 gpios = <&pioC 8 0
408 &pioC 14 0
409 0
410 >;
411 status = "disabled";
412 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800413
414 usb0: ohci@00700000 {
415 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
416 reg = <0x00700000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200417 interrupts = <22 4 2>;
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800418 status = "disabled";
419 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800420
421 usb1: ehci@00800000 {
422 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
423 reg = <0x00800000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200424 interrupts = <22 4 2>;
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800425 status = "disabled";
426 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200427 };
Jean-Christophe PLAGNIOL-VILLARD8f24bda2012-02-05 18:32:37 +0800428
429 i2c@0 {
430 compatible = "i2c-gpio";
431 gpios = <&pioA 20 0 /* sda */
432 &pioA 21 0 /* scl */
433 >;
434 i2c-gpio,sda-open-drain;
435 i2c-gpio,scl-open-drain;
436 i2c-gpio,delay-us = <5>; /* ~100 kHz */
437 #address-cells = <1>;
438 #size-cells = <0>;
439 status = "disabled";
440 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200441};