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Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010042 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080043 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000044 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000045 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010046 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070047 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010048 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010049 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010050 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070051 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070052 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010053 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000055 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010056 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000057 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010058 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090059 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010063 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000064 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010065 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010066 select HAVE_PERF_REGS
67 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070068 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010069 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010071 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select NO_BOOTMEM
73 select OF
74 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010075 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010076 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000077 select POWER_RESET
78 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010079 select RTC_LIB
80 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070081 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070082 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010083 help
84 ARM 64-bit (AArch64) Linux support.
85
86config 64BIT
87 def_bool y
88
89config ARCH_PHYS_ADDR_T_64BIT
90 def_bool y
91
92config MMU
93 def_bool y
94
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070095config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010096 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010097
98config STACKTRACE_SUPPORT
99 def_bool y
100
101config LOCKDEP_SUPPORT
102 def_bool y
103
104config TRACE_IRQFLAGS_SUPPORT
105 def_bool y
106
Will Deaconc209f792014-03-14 17:47:05 +0000107config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100108 def_bool y
109
110config GENERIC_HWEIGHT
111 def_bool y
112
113config GENERIC_CSUM
114 def_bool y
115
116config GENERIC_CALIBRATE_DELAY
117 def_bool y
118
Catalin Marinas19e76402014-02-27 12:09:22 +0000119config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100120 def_bool y
121
Steve Capper29e56942014-10-09 15:29:25 -0700122config HAVE_GENERIC_RCU_GUP
123 def_bool y
124
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100125config ARCH_DMA_ADDR_T_64BIT
126 def_bool y
127
128config NEED_DMA_MAP_STATE
129 def_bool y
130
131config NEED_SG_DMA_LENGTH
132 def_bool y
133
134config SWIOTLB
135 def_bool y
136
137config IOMMU_HELPER
138 def_bool SWIOTLB
139
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100140config KERNEL_MODE_NEON
141 def_bool y
142
Rob Herring92cc15f2014-04-18 17:19:59 -0500143config FIX_EARLYCON_MEM
144 def_bool y
145
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100146source "init/Kconfig"
147
148source "kernel/Kconfig.freezer"
149
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100150menu "Platform selection"
151
Alim Akhtar6f56eef2014-11-22 22:41:52 +0900152config ARCH_EXYNOS
153 bool
154 help
155 This enables support for Samsung Exynos SoC family
156
157config ARCH_EXYNOS7
158 bool "ARMv8 based Samsung Exynos7"
159 select ARCH_EXYNOS
160 select COMMON_CLK_SAMSUNG
161 select HAVE_S3C2410_WATCHDOG if WATCHDOG
162 select HAVE_S3C_RTC if RTC_CLASS
163 select PINCTRL
164 select PINCTRL_EXYNOS
165
166 help
167 This enables support for Samsung Exynos7 SoC family
168
Olof Johansson5118a6a2015-01-27 16:19:11 -0800169config ARCH_FSL_LS2085A
170 bool "Freescale LS2085A SOC"
171 help
172 This enables support for Freescale LS2085A SOC.
173
Eddie Huang4727a6f2015-12-01 10:14:00 +0100174config ARCH_MEDIATEK
175 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
176 select ARM_GIC
177 help
178 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
179
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700180config ARCH_SEATTLE
181 bool "AMD Seattle SoC Family"
182 help
183 This enables support for AMD Seattle SOC Family
184
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700185config ARCH_TEGRA
186 bool "NVIDIA Tegra SoC Family"
187 select ARCH_HAS_RESET_CONTROLLER
188 select ARCH_REQUIRE_GPIOLIB
189 select CLKDEV_LOOKUP
190 select CLKSRC_MMIO
191 select CLKSRC_OF
192 select GENERIC_CLOCKEVENTS
193 select HAVE_CLK
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700194 select PINCTRL
195 select RESET_CONTROLLER
196 help
197 This enables support for the NVIDIA Tegra SoC family.
198
199config ARCH_TEGRA_132_SOC
200 bool "NVIDIA Tegra132 SoC"
201 depends on ARCH_TEGRA
202 select PINCTRL_TEGRA124
Paul Walmsleyd035fdf2015-01-07 01:17:33 -0700203 select USB_ULPI if USB_PHY
204 select USB_ULPI_VIEWPORT if USB_PHY
205 help
206 Enable support for NVIDIA Tegra132 SoC, based on the Denver
207 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
208 but contains an NVIDIA Denver CPU complex in place of
209 Tegra124's "4+1" Cortex-A15 CPU complex.
210
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530211config ARCH_THUNDER
212 bool "Cavium Inc. Thunder SoC Family"
213 help
214 This enables support for Cavium's Thunder Family of SoCs.
215
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100216config ARCH_VEXPRESS
217 bool "ARMv8 software model (Versatile Express)"
218 select ARCH_REQUIRE_GPIOLIB
219 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000220 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100221 select VEXPRESS_CONFIG
222 help
223 This enables support for the ARMv8 software model (Versatile
224 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100225
Vinayak Kale15942852013-04-24 10:06:57 +0100226config ARCH_XGENE
227 bool "AppliedMicro X-Gene SOC Family"
228 help
229 This enables support for AppliedMicro X-Gene SOC Family
230
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100231endmenu
232
233menu "Bus support"
234
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100235config PCI
236 bool "PCI support"
237 help
238 This feature enables support for PCI bus system. If you say Y
239 here, the kernel will include drivers and infrastructure code
240 to support PCI bus devices.
241
242config PCI_DOMAINS
243 def_bool PCI
244
245config PCI_DOMAINS_GENERIC
246 def_bool PCI
247
248config PCI_SYSCALL
249 def_bool PCI
250
251source "drivers/pci/Kconfig"
252source "drivers/pci/pcie/Kconfig"
253source "drivers/pci/hotplug/Kconfig"
254
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100255endmenu
256
257menu "Kernel Features"
258
Andre Przywarac0a01b82014-11-14 15:54:12 +0000259menu "ARM errata workarounds via the alternatives framework"
260
261config ARM64_ERRATUM_826319
262 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
263 default y
264 help
265 This option adds an alternative code sequence to work around ARM
266 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
267 AXI master interface and an L2 cache.
268
269 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
270 and is unable to accept a certain write via this interface, it will
271 not progress on read data presented on the read data channel and the
272 system can deadlock.
273
274 The workaround promotes data cache clean instructions to
275 data cache clean-and-invalidate.
276 Please note that this does not necessarily enable the workaround,
277 as it depends on the alternative framework, which will only patch
278 the kernel if an affected CPU is detected.
279
280 If unsure, say Y.
281
282config ARM64_ERRATUM_827319
283 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
284 default y
285 help
286 This option adds an alternative code sequence to work around ARM
287 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
288 master interface and an L2 cache.
289
290 Under certain conditions this erratum can cause a clean line eviction
291 to occur at the same time as another transaction to the same address
292 on the AMBA 5 CHI interface, which can cause data corruption if the
293 interconnect reorders the two transactions.
294
295 The workaround promotes data cache clean instructions to
296 data cache clean-and-invalidate.
297 Please note that this does not necessarily enable the workaround,
298 as it depends on the alternative framework, which will only patch
299 the kernel if an affected CPU is detected.
300
301 If unsure, say Y.
302
303config ARM64_ERRATUM_824069
304 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
305 default y
306 help
307 This option adds an alternative code sequence to work around ARM
308 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
309 to a coherent interconnect.
310
311 If a Cortex-A53 processor is executing a store or prefetch for
312 write instruction at the same time as a processor in another
313 cluster is executing a cache maintenance operation to the same
314 address, then this erratum might cause a clean cache line to be
315 incorrectly marked as dirty.
316
317 The workaround promotes data cache clean instructions to
318 data cache clean-and-invalidate.
319 Please note that this option does not necessarily enable the
320 workaround, as it depends on the alternative framework, which will
321 only patch the kernel if an affected CPU is detected.
322
323 If unsure, say Y.
324
325config ARM64_ERRATUM_819472
326 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
327 default y
328 help
329 This option adds an alternative code sequence to work around ARM
330 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
331 present when it is connected to a coherent interconnect.
332
333 If the processor is executing a load and store exclusive sequence at
334 the same time as a processor in another cluster is executing a cache
335 maintenance operation to the same address, then this erratum might
336 cause data corruption.
337
338 The workaround promotes data cache clean instructions to
339 data cache clean-and-invalidate.
340 Please note that this does not necessarily enable the workaround,
341 as it depends on the alternative framework, which will only patch
342 the kernel if an affected CPU is detected.
343
344 If unsure, say Y.
345
346config ARM64_ERRATUM_832075
347 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
348 default y
349 help
350 This option adds an alternative code sequence to work around ARM
351 erratum 832075 on Cortex-A57 parts up to r1p2.
352
353 Affected Cortex-A57 parts might deadlock when exclusive load/store
354 instructions to Write-Back memory are mixed with Device loads.
355
356 The workaround is to promote device loads to use Load-Acquire
357 semantics.
358 Please note that this does not necessarily enable the workaround,
359 as it depends on the alternative framework, which will only patch
360 the kernel if an affected CPU is detected.
361
362 If unsure, say Y.
363
364endmenu
365
366
Jungseok Leee41ceed2014-05-12 10:40:38 +0100367choice
368 prompt "Page size"
369 default ARM64_4K_PAGES
370 help
371 Page size (translation granule) configuration.
372
373config ARM64_4K_PAGES
374 bool "4KB"
375 help
376 This feature enables 4KB pages support.
377
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100378config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100379 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100380 help
381 This feature enables 64KB pages support (4KB by default)
382 allowing only two levels of page tables and faster TLB
383 look-up. AArch32 emulation is not available when this feature
384 is enabled.
385
Jungseok Leee41ceed2014-05-12 10:40:38 +0100386endchoice
387
388choice
389 prompt "Virtual address space size"
390 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
391 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
392 help
393 Allows choosing one of multiple possible virtual address
394 space sizes. The level of translation table is determined by
395 a combination of page size and virtual address space size.
396
397config ARM64_VA_BITS_39
398 bool "39-bit"
399 depends on ARM64_4K_PAGES
400
401config ARM64_VA_BITS_42
402 bool "42-bit"
403 depends on ARM64_64K_PAGES
404
Jungseok Leec79b9542014-05-12 18:40:51 +0900405config ARM64_VA_BITS_48
406 bool "48-bit"
Jungseok Leec79b9542014-05-12 18:40:51 +0900407
Jungseok Leee41ceed2014-05-12 10:40:38 +0100408endchoice
409
410config ARM64_VA_BITS
411 int
412 default 39 if ARM64_VA_BITS_39
413 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900414 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100415
Catalin Marinasabe669d2014-07-15 15:37:21 +0100416config ARM64_PGTABLE_LEVELS
417 int
418 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100419 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100420 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
421 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900422
Will Deacona8720132013-10-11 14:52:19 +0100423config CPU_BIG_ENDIAN
424 bool "Build big-endian kernel"
425 help
426 Say Y if you plan on running a kernel in big-endian mode.
427
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100428config SMP
429 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100430 help
431 This enables support for systems with more than one CPU. If
432 you say N here, the kernel will run on single and
433 multiprocessor machines, but will use only one CPU of a
434 multiprocessor machine. If you say Y here, the kernel will run
435 on many, but not all, single processor machines. On a single
436 processor machine, the kernel will run faster if you say N
437 here.
438
439 If you don't know what to do here, say N.
440
Mark Brownf6e763b2014-03-04 07:51:17 +0000441config SCHED_MC
442 bool "Multi-core scheduler support"
443 depends on SMP
444 help
445 Multi-core scheduler support improves the CPU scheduler's decision
446 making when dealing with multi-core CPU chips at a cost of slightly
447 increased overhead in some places. If unsure say N here.
448
449config SCHED_SMT
450 bool "SMT scheduler support"
451 depends on SMP
452 help
453 Improves the CPU scheduler's decision making when dealing with
454 MultiThreading at a cost of slightly increased overhead in some
455 places. If unsure say N here.
456
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100457config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100458 int "Maximum number of CPUs (2-64)"
459 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100460 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100461 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100462 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100463
Mark Rutland9327e2c2013-10-24 20:30:18 +0100464config HOTPLUG_CPU
465 bool "Support for hot-pluggable CPUs"
466 depends on SMP
467 help
468 Say Y here to experiment with turning CPUs off and on. CPUs
469 can be controlled through /sys/devices/system/cpu.
470
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100471source kernel/Kconfig.preempt
472
473config HZ
474 int
475 default 100
476
477config ARCH_HAS_HOLES_MEMORYMODEL
478 def_bool y if SPARSEMEM
479
480config ARCH_SPARSEMEM_ENABLE
481 def_bool y
482 select SPARSEMEM_VMEMMAP_ENABLE
483
484config ARCH_SPARSEMEM_DEFAULT
485 def_bool ARCH_SPARSEMEM_ENABLE
486
487config ARCH_SELECT_MEMORY_MODEL
488 def_bool ARCH_SPARSEMEM_ENABLE
489
490config HAVE_ARCH_PFN_VALID
491 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
492
493config HW_PERF_EVENTS
494 bool "Enable hardware performance counter support for perf events"
495 depends on PERF_EVENTS
496 default y
497 help
498 Enable hardware performance counter support for perf events. If
499 disabled, perf events will use software events only.
500
Steve Capper084bd292013-04-10 13:48:00 +0100501config SYS_SUPPORTS_HUGETLBFS
502 def_bool y
503
504config ARCH_WANT_GENERAL_HUGETLB
505 def_bool y
506
507config ARCH_WANT_HUGE_PMD_SHARE
508 def_bool y if !ARM64_64K_PAGES
509
Steve Capperaf074842013-04-19 16:23:57 +0100510config HAVE_ARCH_TRANSPARENT_HUGEPAGE
511 def_bool y
512
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100513config ARCH_HAS_CACHE_LINE_SIZE
514 def_bool y
515
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100516source "mm/Kconfig"
517
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000518config SECCOMP
519 bool "Enable seccomp to safely compute untrusted bytecode"
520 ---help---
521 This kernel feature is useful for number crunching applications
522 that may need to compute untrusted bytecode during their
523 execution. By using pipes or other transports made available to
524 the process as file descriptors supporting the read/write
525 syscalls, it's possible to isolate those applications in
526 their own address space using seccomp. Once seccomp is
527 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
528 and the task is only allowed to execute a few safe syscalls
529 defined by each seccomp mode.
530
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000531config XEN_DOM0
532 def_bool y
533 depends on XEN
534
535config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700536 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000537 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000538 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000539 help
540 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
541
Steve Capperd03bb142013-04-25 15:19:21 +0100542config FORCE_MAX_ZONEORDER
543 int
544 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
545 default "11"
546
Will Deacon1b907f42014-11-20 16:51:10 +0000547menuconfig ARMV8_DEPRECATED
548 bool "Emulate deprecated/obsolete ARMv8 instructions"
549 depends on COMPAT
550 help
551 Legacy software support may require certain instructions
552 that have been deprecated or obsoleted in the architecture.
553
554 Enable this config to enable selective emulation of these
555 features.
556
557 If unsure, say Y
558
559if ARMV8_DEPRECATED
560
561config SWP_EMULATION
562 bool "Emulate SWP/SWPB instructions"
563 help
564 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
565 they are always undefined. Say Y here to enable software
566 emulation of these instructions for userspace using LDXR/STXR.
567
568 In some older versions of glibc [<=2.8] SWP is used during futex
569 trylock() operations with the assumption that the code will not
570 be preempted. This invalid assumption may be more likely to fail
571 with SWP emulation enabled, leading to deadlock of the user
572 application.
573
574 NOTE: when accessing uncached shared regions, LDXR/STXR rely
575 on an external transaction monitoring block called a global
576 monitor to maintain update atomicity. If your system does not
577 implement a global monitor, this option can cause programs that
578 perform SWP operations to uncached memory to deadlock.
579
580 If unsure, say Y
581
582config CP15_BARRIER_EMULATION
583 bool "Emulate CP15 Barrier instructions"
584 help
585 The CP15 barrier instructions - CP15ISB, CP15DSB, and
586 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
587 strongly recommended to use the ISB, DSB, and DMB
588 instructions instead.
589
590 Say Y here to enable software emulation of these
591 instructions for AArch32 userspace code. When this option is
592 enabled, CP15 barrier usage is traced which can help
593 identify software that needs updating.
594
595 If unsure, say Y
596
Suzuki K. Poulose2d888f42015-01-21 12:43:11 +0000597config SETEND_EMULATION
598 bool "Emulate SETEND instruction"
599 help
600 The SETEND instruction alters the data-endianness of the
601 AArch32 EL0, and is deprecated in ARMv8.
602
603 Say Y here to enable software emulation of the instruction
604 for AArch32 userspace code.
605
606 Note: All the cpus on the system must have mixed endian support at EL0
607 for this feature to be enabled. If a new CPU - which doesn't support mixed
608 endian - is hotplugged in after this feature has been enabled, there could
609 be unexpected results in the applications.
610
611 If unsure, say Y
Will Deacon1b907f42014-11-20 16:51:10 +0000612endif
613
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100614endmenu
615
616menu "Boot options"
617
618config CMDLINE
619 string "Default kernel command string"
620 default ""
621 help
622 Provide a set of default command-line options at build time by
623 entering them here. As a minimum, you should specify the the
624 root device (e.g. root=/dev/nfs).
625
626config CMDLINE_FORCE
627 bool "Always use the default kernel command string"
628 help
629 Always use the default kernel command string, even if the boot
630 loader passes other arguments to the kernel.
631 This is useful if you cannot or don't want to change the
632 command-line options your boot loader passes to the kernel.
633
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200634config EFI_STUB
635 bool
636
Mark Salterf84d0272014-04-15 21:59:30 -0400637config EFI
638 bool "UEFI runtime support"
639 depends on OF && !CPU_BIG_ENDIAN
640 select LIBFDT
641 select UCS2_STRING
642 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200643 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200644 select EFI_STUB
645 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400646 default y
647 help
648 This option provides support for runtime services provided
649 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400650 clock, and platform reset). A UEFI stub is also provided to
651 allow the kernel to be booted as an EFI application. This
652 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400653
Yi Lid1ae8c02014-10-04 23:46:43 +0800654config DMI
655 bool "Enable support for SMBIOS (DMI) tables"
656 depends on EFI
657 default y
658 help
659 This enables SMBIOS/DMI feature for systems.
660
661 This option is only useful on systems that have UEFI firmware.
662 However, even with this option, the resultant kernel should
663 continue to boot on existing non-UEFI platforms.
664
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100665endmenu
666
667menu "Userspace binary formats"
668
669source "fs/Kconfig.binfmt"
670
671config COMPAT
672 bool "Kernel support for 32-bit EL0"
673 depends on !ARM64_64K_PAGES
674 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700675 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500676 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500677 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100678 help
679 This option enables support for a 32-bit EL0 running under a 64-bit
680 kernel at EL1. AArch32-specific components such as system calls,
681 the user helper functions, VFP support and the ptrace interface are
682 handled appropriately by the kernel.
683
684 If you want to execute 32-bit userspace applications, say Y.
685
686config SYSVIPC_COMPAT
687 def_bool y
688 depends on COMPAT && SYSVIPC
689
690endmenu
691
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000692menu "Power management options"
693
694source "kernel/power/Kconfig"
695
696config ARCH_SUSPEND_POSSIBLE
697 def_bool y
698
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000699endmenu
700
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100701menu "CPU Power Management"
702
703source "drivers/cpuidle/Kconfig"
704
Rob Herring52e7e812014-02-24 11:27:57 +0900705source "drivers/cpufreq/Kconfig"
706
707endmenu
708
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100709source "net/Kconfig"
710
711source "drivers/Kconfig"
712
Mark Salterf84d0272014-04-15 21:59:30 -0400713source "drivers/firmware/Kconfig"
714
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100715source "fs/Kconfig"
716
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100717source "arch/arm64/kvm/Kconfig"
718
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100719source "arch/arm64/Kconfig.debug"
720
721source "security/Kconfig"
722
723source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800724if CRYPTO
725source "arch/arm64/crypto/Kconfig"
726endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100727
728source "lib/Kconfig"