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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000030#include "radeon_asic.h"
Jerome Glissec93bb852009-07-13 21:04:08 +020031#include "atom.h"
Jerome Glisse3bc68532009-10-01 09:39:24 +020032#include "rs690d.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020033
Alex Deucher89e51812012-02-23 17:53:38 -050034int rs690_mc_wait_for_idle(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035{
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
Jerome Glisse3bc68532009-10-01 09:39:24 +020041 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
Jerome Glisse771fe6b2009-06-05 14:42:42 +020043 return 0;
Jerome Glisse3bc68532009-10-01 09:39:24 +020044 udelay(1);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020045 }
46 return -1;
47}
48
Jerome Glisse3bc68532009-10-01 09:39:24 +020049static void rs690_gpu_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050{
Jerome Glisse771fe6b2009-06-05 14:42:42 +020051 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57}
58
Alex Deuchera084e6e2010-03-18 01:04:01 -040059union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62};
63
Jerome Glissec93bb852009-07-13 21:04:08 +020064void rs690_pm_info(struct radeon_device *rdev)
65{
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
Alex Deuchera084e6e2010-03-18 01:04:01 -040067 union igp_info *info;
Jerome Glissec93bb852009-07-13 21:04:08 +020068 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
Alex Deuchera084e6e2010-03-18 01:04:01 -040072 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
Ben Skeggs68adac52010-04-28 11:46:42 +100079 tmp.full = dfixed_const(100);
Alex Deucher265aa6c2011-02-14 16:16:22 -050080 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
Ben Skeggs68adac52010-04-28 11:46:42 +100081 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
Alex Deucher265aa6c2011-02-14 16:16:22 -050082 if (le16_to_cpu(info->info.usK8MemoryClock))
Alex Deucherf8920342010-06-30 12:02:03 -040083 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87 } else
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
Ben Skeggs68adac52010-04-28 11:46:42 +100089 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
Alex Deuchera084e6e2010-03-18 01:04:01 -040091 break;
92 case 2:
Ben Skeggs68adac52010-04-28 11:46:42 +100093 tmp.full = dfixed_const(100);
Alex Deucher265aa6c2011-02-14 16:16:22 -050094 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
Ben Skeggs68adac52010-04-28 11:46:42 +100095 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
Alex Deucher265aa6c2011-02-14 16:16:22 -050096 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
97 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
Alex Deucherf8920342010-06-30 12:02:03 -040098 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100 else
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
Ben Skeggs68adac52010-04-28 11:46:42 +1000102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
Alex Deucher265aa6c2011-02-14 16:16:22 -0500103 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
Ben Skeggs68adac52010-04-28 11:46:42 +1000104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
Alex Deuchera084e6e2010-03-18 01:04:01 -0400106 break;
107 default:
Alex Deuchera084e6e2010-03-18 01:04:01 -0400108 /* We assume the slower possible clock ie worst case */
Alex Deucherf8920342010-06-30 12:02:03 -0400109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
Ben Skeggs68adac52010-04-28 11:46:42 +1000112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
Alex Deuchera084e6e2010-03-18 01:04:01 -0400113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114 break;
115 }
116 } else {
Jerome Glissec93bb852009-07-13 21:04:08 +0200117 /* We assume the slower possible clock ie worst case */
Alex Deucherf8920342010-06-30 12:02:03 -0400118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
Ben Skeggs68adac52010-04-28 11:46:42 +1000121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
Jerome Glissec93bb852009-07-13 21:04:08 +0200122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
Jerome Glissec93bb852009-07-13 21:04:08 +0200123 }
124 /* Compute various bandwidth */
125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129 * = ht_clk * ht_width / 5
130 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
Jerome Glissec93bb852009-07-13 21:04:08 +0200133 rdev->pm.igp_ht_link_width);
Ben Skeggs68adac52010-04-28 11:46:42 +1000134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136 /* HT link is a limiting factor */
137 rdev->pm.max_bandwidth.full = tmp.full;
138 }
139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140 * = (sideport_clk * 14) / 10
141 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200146}
147
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400148static void rs690_mc_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200149{
Jerome Glissed594e462010-02-17 21:54:29 +0000150 u64 base;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400151 uint32_t h_addr, l_addr;
152 unsigned long long k8_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200153
154 rs400_gart_adjust_size(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200155 rdev->mc.vram_is_ddr = true;
Alex Deucher722f2942009-12-03 16:18:19 -0500156 rdev->mc.vram_width = 128;
Dave Airlie7a50f012009-07-21 20:39:30 +1000157 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
158 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
Jordan Crouse01d73a62010-05-27 13:40:24 -0600159 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
160 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
Jerome Glisse51e5fcd2010-02-19 14:33:54 +0000161 rdev->mc.visible_vram_size = rdev->mc.aper_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000162 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
163 base = G_000100_MC_FB_START(base) << 16;
Alex Deucher06b64762010-01-05 11:27:29 -0500164 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
Samuel Lia0a53aa2013-04-08 17:25:47 -0400165
166 /* Use K8 direct mapping for fast fb access. */
167 rdev->fastfb_working = false;
168 h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
169 l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
170 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
171#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
172 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
173#endif
174 {
175 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
176 * memory is present.
177 */
178 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
179 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
180 (unsigned long long)rdev->mc.aper_base, k8_addr);
181 rdev->mc.aper_base = (resource_size_t)k8_addr;
182 rdev->fastfb_working = true;
183 }
184 }
185
Alex Deucher4c70b2e2010-08-02 19:39:15 -0400186 rs690_pm_info(rdev);
Jerome Glissed594e462010-02-17 21:54:29 +0000187 radeon_vram_location(rdev, &rdev->mc, base);
Alex Deucher8d369bb2010-07-15 10:51:10 -0400188 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
Jerome Glissed594e462010-02-17 21:54:29 +0000189 radeon_gtt_location(rdev, &rdev->mc);
Alex Deucherf47299c2010-03-16 20:54:38 -0400190 radeon_update_bandwidth_info(rdev);
Alex Deucher22dd5012009-12-06 19:45:17 -0500191}
192
Jerome Glissec93bb852009-07-13 21:04:08 +0200193void rs690_line_buffer_adjust(struct radeon_device *rdev,
194 struct drm_display_mode *mode1,
195 struct drm_display_mode *mode2)
196{
197 u32 tmp;
198
199 /*
200 * Line Buffer Setup
201 * There is a single line buffer shared by both display controllers.
Jerome Glisse3bc68532009-10-01 09:39:24 +0200202 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
Jerome Glissec93bb852009-07-13 21:04:08 +0200203 * the display controllers. The paritioning can either be done
204 * manually or via one of four preset allocations specified in bits 1:0:
205 * 0 - line buffer is divided in half and shared between crtc
206 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
207 * 2 - D1 gets the whole buffer
208 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
Jerome Glisse3bc68532009-10-01 09:39:24 +0200209 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
Jerome Glissec93bb852009-07-13 21:04:08 +0200210 * allocation mode. In manual allocation mode, D1 always starts at 0,
211 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
212 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200213 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
214 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
Jerome Glissec93bb852009-07-13 21:04:08 +0200215 /* auto */
216 if (mode1 && mode2) {
217 if (mode1->hdisplay > mode2->hdisplay) {
218 if (mode1->hdisplay > 2560)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
Jerome Glissec93bb852009-07-13 21:04:08 +0200220 else
Jerome Glisse3bc68532009-10-01 09:39:24 +0200221 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
Jerome Glissec93bb852009-07-13 21:04:08 +0200222 } else if (mode2->hdisplay > mode1->hdisplay) {
223 if (mode2->hdisplay > 2560)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200224 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
Jerome Glissec93bb852009-07-13 21:04:08 +0200225 else
Jerome Glisse3bc68532009-10-01 09:39:24 +0200226 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
Jerome Glissec93bb852009-07-13 21:04:08 +0200227 } else
Jerome Glisse3bc68532009-10-01 09:39:24 +0200228 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
Jerome Glissec93bb852009-07-13 21:04:08 +0200229 } else if (mode1) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200230 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
Jerome Glissec93bb852009-07-13 21:04:08 +0200231 } else if (mode2) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200232 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
Jerome Glissec93bb852009-07-13 21:04:08 +0200233 }
Jerome Glisse3bc68532009-10-01 09:39:24 +0200234 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200235}
236
237struct rs690_watermark {
238 u32 lb_request_fifo_depth;
239 fixed20_12 num_line_pair;
240 fixed20_12 estimated_width;
241 fixed20_12 worst_case_latency;
242 fixed20_12 consumption_rate;
243 fixed20_12 active_time;
244 fixed20_12 dbpp;
245 fixed20_12 priority_mark_max;
246 fixed20_12 priority_mark;
247 fixed20_12 sclk;
248};
249
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400250static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
Jerome Glissec93bb852009-07-13 21:04:08 +0200251 struct radeon_crtc *crtc,
252 struct rs690_watermark *wm)
253{
254 struct drm_display_mode *mode = &crtc->base.mode;
255 fixed20_12 a, b, c;
256 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
257 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
Jerome Glissec93bb852009-07-13 21:04:08 +0200258
259 if (!crtc->base.enabled) {
260 /* FIXME: wouldn't it better to set priority mark to maximum */
261 wm->lb_request_fifo_depth = 4;
262 return;
263 }
264
Ben Skeggs68adac52010-04-28 11:46:42 +1000265 if (crtc->vsc.full > dfixed_const(2))
266 wm->num_line_pair.full = dfixed_const(2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200267 else
Ben Skeggs68adac52010-04-28 11:46:42 +1000268 wm->num_line_pair.full = dfixed_const(1);
Jerome Glissec93bb852009-07-13 21:04:08 +0200269
Ben Skeggs68adac52010-04-28 11:46:42 +1000270 b.full = dfixed_const(mode->crtc_hdisplay);
271 c.full = dfixed_const(256);
272 a.full = dfixed_div(b, c);
273 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
274 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
275 if (a.full < dfixed_const(4)) {
Jerome Glissec93bb852009-07-13 21:04:08 +0200276 wm->lb_request_fifo_depth = 4;
277 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000278 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
Jerome Glissec93bb852009-07-13 21:04:08 +0200279 }
280
281 /* Determine consumption rate
282 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
283 * vtaps = number of vertical taps,
284 * vsc = vertical scaling ratio, defined as source/destination
285 * hsc = horizontal scaling ration, defined as source/destination
286 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000287 a.full = dfixed_const(mode->clock);
288 b.full = dfixed_const(1000);
289 a.full = dfixed_div(a, b);
290 pclk.full = dfixed_div(b, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200291 if (crtc->rmx_type != RMX_OFF) {
Ben Skeggs68adac52010-04-28 11:46:42 +1000292 b.full = dfixed_const(2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200293 if (crtc->vsc.full > b.full)
294 b.full = crtc->vsc.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000295 b.full = dfixed_mul(b, crtc->hsc);
296 c.full = dfixed_const(2);
297 b.full = dfixed_div(b, c);
298 consumption_time.full = dfixed_div(pclk, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200299 } else {
300 consumption_time.full = pclk.full;
301 }
Ben Skeggs68adac52010-04-28 11:46:42 +1000302 a.full = dfixed_const(1);
303 wm->consumption_rate.full = dfixed_div(a, consumption_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200304
305
306 /* Determine line time
307 * LineTime = total time for one line of displayhtotal
308 * LineTime = total number of horizontal pixels
309 * pclk = pixel clock period(ns)
310 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000311 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
312 line_time.full = dfixed_mul(a, pclk);
Jerome Glissec93bb852009-07-13 21:04:08 +0200313
314 /* Determine active time
315 * ActiveTime = time of active region of display within one line,
316 * hactive = total number of horizontal active pixels
317 * htotal = total number of horizontal pixels
318 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000319 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
320 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
321 wm->active_time.full = dfixed_mul(line_time, b);
322 wm->active_time.full = dfixed_div(wm->active_time, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200323
324 /* Maximun bandwidth is the minimun bandwidth of all component */
325 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
Alex Deucher0888e882010-06-12 11:50:13 -0400326 if (rdev->mc.igp_sideport_enabled) {
Jerome Glissec93bb852009-07-13 21:04:08 +0200327 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
328 rdev->pm.sideport_bandwidth.full)
329 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
Ben Skeggs68adac52010-04-28 11:46:42 +1000330 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
331 read_delay_latency.full = dfixed_div(read_delay_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200332 rdev->pm.igp_sideport_mclk);
333 } else {
334 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
335 rdev->pm.k8_bandwidth.full)
336 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
337 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
338 rdev->pm.ht_bandwidth.full)
339 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
Ben Skeggs68adac52010-04-28 11:46:42 +1000340 read_delay_latency.full = dfixed_const(5000);
Jerome Glissec93bb852009-07-13 21:04:08 +0200341 }
342
343 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000344 a.full = dfixed_const(16);
345 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
346 a.full = dfixed_const(1000);
347 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
Jerome Glissec93bb852009-07-13 21:04:08 +0200348 /* Determine chunk time
349 * ChunkTime = the time it takes the DCP to send one chunk of data
350 * to the LB which consists of pipeline delay and inter chunk gap
351 * sclk = system clock(ns)
352 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000353 a.full = dfixed_const(256 * 13);
354 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
355 a.full = dfixed_const(10);
356 chunk_time.full = dfixed_div(chunk_time, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200357
358 /* Determine the worst case latency
359 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
360 * WorstCaseLatency = worst case time from urgent to when the MC starts
361 * to return data
362 * READ_DELAY_IDLE_MAX = constant of 1us
363 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
364 * which consists of pipeline delay and inter chunk gap
365 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000366 if (dfixed_trunc(wm->num_line_pair) > 1) {
367 a.full = dfixed_const(3);
368 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200369 wm->worst_case_latency.full += read_delay_latency.full;
370 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000371 a.full = dfixed_const(2);
372 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200373 wm->worst_case_latency.full += read_delay_latency.full;
374 }
375
376 /* Determine the tolerable latency
377 * TolerableLatency = Any given request has only 1 line time
378 * for the data to be returned
379 * LBRequestFifoDepth = Number of chunk requests the LB can
380 * put into the request FIFO for a display
381 * LineTime = total time for one line of display
382 * ChunkTime = the time it takes the DCP to send one chunk
383 * of data to the LB which consists of
384 * pipeline delay and inter chunk gap
385 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000386 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
Jerome Glissec93bb852009-07-13 21:04:08 +0200387 tolerable_latency.full = line_time.full;
388 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000389 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200390 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000391 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
Jerome Glissec93bb852009-07-13 21:04:08 +0200392 tolerable_latency.full = line_time.full - tolerable_latency.full;
393 }
394 /* We assume worst case 32bits (4 bytes) */
Ben Skeggs68adac52010-04-28 11:46:42 +1000395 wm->dbpp.full = dfixed_const(4 * 8);
Jerome Glissec93bb852009-07-13 21:04:08 +0200396
397 /* Determine the maximum priority mark
398 * width = viewport width in pixels
399 */
Ben Skeggs68adac52010-04-28 11:46:42 +1000400 a.full = dfixed_const(16);
401 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
402 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
403 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
Jerome Glissec93bb852009-07-13 21:04:08 +0200404
405 /* Determine estimated width */
406 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000407 estimated_width.full = dfixed_div(estimated_width, consumption_time);
408 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
409 wm->priority_mark.full = dfixed_const(10);
Jerome Glissec93bb852009-07-13 21:04:08 +0200410 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000411 a.full = dfixed_const(16);
412 wm->priority_mark.full = dfixed_div(estimated_width, a);
413 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
Jerome Glissec93bb852009-07-13 21:04:08 +0200414 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
415 }
416}
417
418void rs690_bandwidth_update(struct radeon_device *rdev)
419{
420 struct drm_display_mode *mode0 = NULL;
421 struct drm_display_mode *mode1 = NULL;
422 struct rs690_watermark wm0;
423 struct rs690_watermark wm1;
Alex Deuchere06b14e2010-08-02 12:13:46 -0400424 u32 tmp;
425 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
426 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
Jerome Glissec93bb852009-07-13 21:04:08 +0200427 fixed20_12 priority_mark02, priority_mark12, fill_rate;
428 fixed20_12 a, b;
429
Alex Deucherf46c0122010-03-31 00:33:27 -0400430 radeon_update_display_priority(rdev);
431
Jerome Glissec93bb852009-07-13 21:04:08 +0200432 if (rdev->mode_info.crtcs[0]->base.enabled)
433 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
434 if (rdev->mode_info.crtcs[1]->base.enabled)
435 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
436 /*
437 * Set display0/1 priority up in the memory controller for
438 * modes if the user specifies HIGH for displaypriority
439 * option.
440 */
Alex Deucherf46c0122010-03-31 00:33:27 -0400441 if ((rdev->disp_priority == 2) &&
442 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200443 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
444 tmp &= C_000104_MC_DISP0R_INIT_LAT;
445 tmp &= C_000104_MC_DISP1R_INIT_LAT;
Jerome Glissec93bb852009-07-13 21:04:08 +0200446 if (mode0)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200447 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
448 if (mode1)
449 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
450 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200451 }
452 rs690_line_buffer_adjust(rdev, mode0, mode1);
453
454 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
Jerome Glisse3bc68532009-10-01 09:39:24 +0200455 WREG32(R_006C9C_DCP_CONTROL, 0);
Jerome Glissec93bb852009-07-13 21:04:08 +0200456 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
Jerome Glisse3bc68532009-10-01 09:39:24 +0200457 WREG32(R_006C9C_DCP_CONTROL, 2);
Jerome Glissec93bb852009-07-13 21:04:08 +0200458
459 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
460 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
461
462 tmp = (wm0.lb_request_fifo_depth - 1);
463 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
Jerome Glisse3bc68532009-10-01 09:39:24 +0200464 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
Jerome Glissec93bb852009-07-13 21:04:08 +0200465
466 if (mode0 && mode1) {
Ben Skeggs68adac52010-04-28 11:46:42 +1000467 if (dfixed_trunc(wm0.dbpp) > 64)
468 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
Jerome Glissec93bb852009-07-13 21:04:08 +0200469 else
470 a.full = wm0.num_line_pair.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000471 if (dfixed_trunc(wm1.dbpp) > 64)
472 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
Jerome Glissec93bb852009-07-13 21:04:08 +0200473 else
474 b.full = wm1.num_line_pair.full;
475 a.full += b.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000476 fill_rate.full = dfixed_div(wm0.sclk, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200477 if (wm0.consumption_rate.full > fill_rate.full) {
478 b.full = wm0.consumption_rate.full - fill_rate.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000479 b.full = dfixed_mul(b, wm0.active_time);
480 a.full = dfixed_mul(wm0.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200481 wm0.consumption_rate);
482 a.full = a.full + b.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000483 b.full = dfixed_const(16 * 1000);
484 priority_mark02.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200485 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000486 a.full = dfixed_mul(wm0.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200487 wm0.consumption_rate);
Ben Skeggs68adac52010-04-28 11:46:42 +1000488 b.full = dfixed_const(16 * 1000);
489 priority_mark02.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200490 }
491 if (wm1.consumption_rate.full > fill_rate.full) {
492 b.full = wm1.consumption_rate.full - fill_rate.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000493 b.full = dfixed_mul(b, wm1.active_time);
494 a.full = dfixed_mul(wm1.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200495 wm1.consumption_rate);
496 a.full = a.full + b.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000497 b.full = dfixed_const(16 * 1000);
498 priority_mark12.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200499 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000500 a.full = dfixed_mul(wm1.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200501 wm1.consumption_rate);
Ben Skeggs68adac52010-04-28 11:46:42 +1000502 b.full = dfixed_const(16 * 1000);
503 priority_mark12.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200504 }
505 if (wm0.priority_mark.full > priority_mark02.full)
506 priority_mark02.full = wm0.priority_mark.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000507 if (dfixed_trunc(priority_mark02) < 0)
Jerome Glissec93bb852009-07-13 21:04:08 +0200508 priority_mark02.full = 0;
509 if (wm0.priority_mark_max.full > priority_mark02.full)
510 priority_mark02.full = wm0.priority_mark_max.full;
511 if (wm1.priority_mark.full > priority_mark12.full)
512 priority_mark12.full = wm1.priority_mark.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000513 if (dfixed_trunc(priority_mark12) < 0)
Jerome Glissec93bb852009-07-13 21:04:08 +0200514 priority_mark12.full = 0;
515 if (wm1.priority_mark_max.full > priority_mark12.full)
516 priority_mark12.full = wm1.priority_mark_max.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000517 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
518 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
Alex Deucherf46c0122010-03-31 00:33:27 -0400519 if (rdev->disp_priority == 2) {
520 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
521 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
522 }
Jerome Glissec93bb852009-07-13 21:04:08 +0200523 } else if (mode0) {
Ben Skeggs68adac52010-04-28 11:46:42 +1000524 if (dfixed_trunc(wm0.dbpp) > 64)
525 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
Jerome Glissec93bb852009-07-13 21:04:08 +0200526 else
527 a.full = wm0.num_line_pair.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000528 fill_rate.full = dfixed_div(wm0.sclk, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200529 if (wm0.consumption_rate.full > fill_rate.full) {
530 b.full = wm0.consumption_rate.full - fill_rate.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000531 b.full = dfixed_mul(b, wm0.active_time);
532 a.full = dfixed_mul(wm0.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200533 wm0.consumption_rate);
534 a.full = a.full + b.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000535 b.full = dfixed_const(16 * 1000);
536 priority_mark02.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200537 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000538 a.full = dfixed_mul(wm0.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200539 wm0.consumption_rate);
Ben Skeggs68adac52010-04-28 11:46:42 +1000540 b.full = dfixed_const(16 * 1000);
541 priority_mark02.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200542 }
543 if (wm0.priority_mark.full > priority_mark02.full)
544 priority_mark02.full = wm0.priority_mark.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000545 if (dfixed_trunc(priority_mark02) < 0)
Jerome Glissec93bb852009-07-13 21:04:08 +0200546 priority_mark02.full = 0;
547 if (wm0.priority_mark_max.full > priority_mark02.full)
548 priority_mark02.full = wm0.priority_mark_max.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000549 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
Alex Deucherf46c0122010-03-31 00:33:27 -0400550 if (rdev->disp_priority == 2)
551 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
Alex Deuchere06b14e2010-08-02 12:13:46 -0400552 } else if (mode1) {
Ben Skeggs68adac52010-04-28 11:46:42 +1000553 if (dfixed_trunc(wm1.dbpp) > 64)
554 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
Jerome Glissec93bb852009-07-13 21:04:08 +0200555 else
556 a.full = wm1.num_line_pair.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000557 fill_rate.full = dfixed_div(wm1.sclk, a);
Jerome Glissec93bb852009-07-13 21:04:08 +0200558 if (wm1.consumption_rate.full > fill_rate.full) {
559 b.full = wm1.consumption_rate.full - fill_rate.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000560 b.full = dfixed_mul(b, wm1.active_time);
561 a.full = dfixed_mul(wm1.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200562 wm1.consumption_rate);
563 a.full = a.full + b.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000564 b.full = dfixed_const(16 * 1000);
565 priority_mark12.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200566 } else {
Ben Skeggs68adac52010-04-28 11:46:42 +1000567 a.full = dfixed_mul(wm1.worst_case_latency,
Jerome Glissec93bb852009-07-13 21:04:08 +0200568 wm1.consumption_rate);
Ben Skeggs68adac52010-04-28 11:46:42 +1000569 b.full = dfixed_const(16 * 1000);
570 priority_mark12.full = dfixed_div(a, b);
Jerome Glissec93bb852009-07-13 21:04:08 +0200571 }
572 if (wm1.priority_mark.full > priority_mark12.full)
573 priority_mark12.full = wm1.priority_mark.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000574 if (dfixed_trunc(priority_mark12) < 0)
Jerome Glissec93bb852009-07-13 21:04:08 +0200575 priority_mark12.full = 0;
576 if (wm1.priority_mark_max.full > priority_mark12.full)
577 priority_mark12.full = wm1.priority_mark_max.full;
Ben Skeggs68adac52010-04-28 11:46:42 +1000578 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
Alex Deucherf46c0122010-03-31 00:33:27 -0400579 if (rdev->disp_priority == 2)
580 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
Jerome Glissec93bb852009-07-13 21:04:08 +0200581 }
Alex Deuchere06b14e2010-08-02 12:13:46 -0400582
583 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
584 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
585 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
586 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
Jerome Glissec93bb852009-07-13 21:04:08 +0200587}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200588
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200589uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
590{
591 uint32_t r;
592
Jerome Glisse3bc68532009-10-01 09:39:24 +0200593 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
594 r = RREG32(R_00007C_MC_DATA);
595 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200596 return r;
597}
598
599void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
600{
Jerome Glisse3bc68532009-10-01 09:39:24 +0200601 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
602 S_000078_MC_IND_WR_EN(1));
603 WREG32(R_00007C_MC_DATA, v);
604 WREG32(R_000078_MC_INDEX, 0x7F);
605}
606
Lauri Kasanen1109ca02012-08-31 13:43:50 -0400607static void rs690_mc_program(struct radeon_device *rdev)
Jerome Glisse3bc68532009-10-01 09:39:24 +0200608{
609 struct rv515_mc_save save;
610
611 /* Stops all mc clients */
612 rv515_mc_stop(rdev, &save);
613
614 /* Wait for mc idle */
615 if (rs690_mc_wait_for_idle(rdev))
616 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
617 /* Program MC, should be a 32bits limited address space */
618 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
619 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
620 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
621 WREG32(R_000134_HDP_FB_LOCATION,
622 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
623
624 rv515_mc_resume(rdev, &save);
625}
626
627static int rs690_startup(struct radeon_device *rdev)
628{
629 int r;
630
631 rs690_mc_program(rdev);
632 /* Resume clock */
633 rv515_clock_startup(rdev);
634 /* Initialize GPU configuration (# pipes, ...) */
635 rs690_gpu_init(rdev);
636 /* Initialize GART (initialize after TTM so we can allocate
637 * memory through TTM but finalize after TTM) */
638 r = rs400_gart_enable(rdev);
639 if (r)
640 return r;
Alex Deucher724c80e2010-08-27 18:25:25 -0400641
642 /* allocate wb buffer */
643 r = radeon_wb_init(rdev);
644 if (r)
645 return r;
646
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000647 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
648 if (r) {
649 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
650 return r;
651 }
652
Jerome Glisse3bc68532009-10-01 09:39:24 +0200653 /* Enable IRQ */
Jerome Glisseac447df2009-09-30 22:18:43 +0200654 rs600_irq_set(rdev);
Jerome Glissecafe6602010-01-07 12:39:21 +0100655 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200656 /* 1M ring buffer */
657 r = r100_cp_init(rdev, 1024 * 1024);
658 if (r) {
Paul Bolleec4f2ac2011-01-28 23:32:04 +0100659 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200660 return r;
661 }
Rafał Miłeckife50ac72010-06-19 12:24:57 +0200662
Christian König2898c342012-07-05 11:55:34 +0200663 r = radeon_ib_pool_init(rdev);
664 if (r) {
665 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500666 return r;
Christian König2898c342012-07-05 11:55:34 +0200667 }
Jerome Glisseb15ba512011-11-15 11:48:34 -0500668
Alex Deucherd4e30ef2012-06-04 17:18:51 -0400669 r = r600_audio_init(rdev);
670 if (r) {
671 dev_err(rdev->dev, "failed initializing audio\n");
672 return r;
673 }
674
Jerome Glisse3bc68532009-10-01 09:39:24 +0200675 return 0;
676}
677
678int rs690_resume(struct radeon_device *rdev)
679{
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500680 int r;
681
Jerome Glisse3bc68532009-10-01 09:39:24 +0200682 /* Make sur GART are not working */
683 rs400_gart_disable(rdev);
684 /* Resume clock before doing reset */
685 rv515_clock_startup(rdev);
686 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000687 if (radeon_asic_reset(rdev)) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200688 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
689 RREG32(R_000E40_RBBM_STATUS),
690 RREG32(R_0007C0_CP_STAT));
691 }
692 /* post */
693 atom_asic_init(rdev->mode_info.atom_context);
694 /* Resume clock after posting */
695 rv515_clock_startup(rdev);
Dave Airlie550e2d92009-12-09 14:15:38 +1000696 /* Initialize surface registers */
697 radeon_surface_init(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500698
699 rdev->accel_working = true;
Jerome Glisse6b7746e2012-02-20 17:57:20 -0500700 r = rs690_startup(rdev);
701 if (r) {
702 rdev->accel_working = false;
703 }
704 return r;
Jerome Glisse3bc68532009-10-01 09:39:24 +0200705}
706
707int rs690_suspend(struct radeon_device *rdev)
708{
Rafał Miłeckife50ac72010-06-19 12:24:57 +0200709 r600_audio_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200710 r100_cp_disable(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400711 radeon_wb_disable(rdev);
Jerome Glisseac447df2009-09-30 22:18:43 +0200712 rs600_irq_disable(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200713 rs400_gart_disable(rdev);
714 return 0;
715}
716
717void rs690_fini(struct radeon_device *rdev)
718{
Rafał Miłeckife50ac72010-06-19 12:24:57 +0200719 r600_audio_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200720 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400721 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200722 radeon_ib_pool_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200723 radeon_gem_fini(rdev);
724 rs400_gart_fini(rdev);
725 radeon_irq_kms_fini(rdev);
726 radeon_fence_driver_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +0100727 radeon_bo_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200728 radeon_atombios_fini(rdev);
729 kfree(rdev->bios);
730 rdev->bios = NULL;
731}
732
733int rs690_init(struct radeon_device *rdev)
734{
735 int r;
736
Jerome Glisse3bc68532009-10-01 09:39:24 +0200737 /* Disable VGA */
738 rv515_vga_render_disable(rdev);
739 /* Initialize scratch registers */
740 radeon_scratch_init(rdev);
741 /* Initialize surface registers */
742 radeon_surface_init(rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000743 /* restore some register to sane defaults */
744 r100_restore_sanity(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200745 /* TODO: disable VGA need to use VGA request */
746 /* BIOS*/
747 if (!radeon_get_bios(rdev)) {
748 if (ASIC_IS_AVIVO(rdev))
749 return -EINVAL;
750 }
751 if (rdev->is_atom_bios) {
752 r = radeon_atombios_init(rdev);
753 if (r)
754 return r;
755 } else {
756 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
757 return -EINVAL;
758 }
759 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
Jerome Glissea2d07b72010-03-09 14:45:11 +0000760 if (radeon_asic_reset(rdev)) {
Jerome Glisse3bc68532009-10-01 09:39:24 +0200761 dev_warn(rdev->dev,
762 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
763 RREG32(R_000E40_RBBM_STATUS),
764 RREG32(R_0007C0_CP_STAT));
765 }
766 /* check if cards are posted or not */
Dave Airlie72542d72009-12-01 14:06:31 +1000767 if (radeon_boot_test_post_card(rdev) == false)
768 return -EINVAL;
769
Jerome Glisse3bc68532009-10-01 09:39:24 +0200770 /* Initialize clocks */
771 radeon_get_clock_info(rdev->ddev);
Jerome Glissed594e462010-02-17 21:54:29 +0000772 /* initialize memory controller */
773 rs690_mc_init(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200774 rv515_debugfs(rdev);
775 /* Fence driver */
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000776 r = radeon_fence_driver_init(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200777 if (r)
778 return r;
779 r = radeon_irq_kms_init(rdev);
780 if (r)
781 return r;
782 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +0100783 r = radeon_bo_init(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200784 if (r)
785 return r;
786 r = rs400_gart_init(rdev);
787 if (r)
788 return r;
789 rs600_set_safe_registers(rdev);
Jerome Glisseb15ba512011-11-15 11:48:34 -0500790
Jerome Glisse3bc68532009-10-01 09:39:24 +0200791 rdev->accel_working = true;
792 r = rs690_startup(rdev);
793 if (r) {
794 /* Somethings want wront with the accel init stop accel */
795 dev_err(rdev->dev, "Disabling GPU acceleration\n");
Jerome Glisse3bc68532009-10-01 09:39:24 +0200796 r100_cp_fini(rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -0400797 radeon_wb_fini(rdev);
Christian König2898c342012-07-05 11:55:34 +0200798 radeon_ib_pool_fini(rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +0200799 rs400_gart_fini(rdev);
800 radeon_irq_kms_fini(rdev);
801 rdev->accel_working = false;
802 }
803 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200804}