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Alan Tull6a8c3be2015-10-07 16:36:28 +01001#
2# FPGA framework configuration
3#
4
5menu "FPGA Configuration Support"
6
7config FPGA
8 tristate "FPGA Configuration Framework"
9 help
10 Say Y here if you want support for configuring FPGAs from the
11 kernel. The FPGA framework adds a FPGA manager class and FPGA
12 manager drivers.
13
Alan Tullfab62662015-10-07 16:36:29 +010014if FPGA
15
Alan Tull0fa20cd2016-11-01 14:14:29 -050016config FPGA_REGION
17 tristate "FPGA Region"
18 depends on OF && FPGA_BRIDGE
19 help
20 FPGA Regions allow loading FPGA images under control of
21 the Device Tree.
22
Alan Tullfab62662015-10-07 16:36:29 +010023config FPGA_MGR_SOCFPGA
24 tristate "Altera SOCFPGA FPGA Manager"
25 depends on ARCH_SOCFPGA
26 help
27 FPGA manager driver support for Altera SOCFPGA.
28
Alan Tullacbb910a2016-11-01 14:14:32 -050029config FPGA_MGR_SOCFPGA_A10
30 tristate "Altera SoCFPGA Arria10"
31 depends on ARCH_SOCFPGA
32 help
33 FPGA manager driver support for Altera Arria10 SoCFPGA.
34
Moritz Fischer37784702015-10-16 15:42:30 -070035config FPGA_MGR_ZYNQ_FPGA
36 tristate "Xilinx Zynq FPGA"
Jean Delvare54e9b092016-09-08 09:38:05 -050037 depends on ARCH_ZYNQ || COMPILE_TEST
Sudip Mukherjee1c8cb402016-08-03 13:45:46 -070038 depends on HAS_DMA
Moritz Fischer37784702015-10-16 15:42:30 -070039 help
40 FPGA manager driver support for Xilinx Zynq FPGAs.
41
Alan Tull21aeda92016-11-01 14:14:28 -050042config FPGA_BRIDGE
43 tristate "FPGA Bridge Framework"
44 depends on OF
45 help
46 Say Y here if you want to support bridges connected between host
47 processors and FPGAs or between FPGAs.
48
Alan Tulle5f8efa2016-11-01 14:14:30 -050049config SOCFPGA_FPGA_BRIDGE
50 tristate "Altera SoCFPGA FPGA Bridges"
51 depends on ARCH_SOCFPGA && FPGA_BRIDGE
52 help
53 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
54 devices.
55
Alan Tullca24a642016-11-01 14:14:31 -050056config ALTERA_FREEZE_BRIDGE
57 tristate "Altera FPGA Freeze Bridge"
58 depends on ARCH_SOCFPGA && FPGA_BRIDGE
59 help
60 Say Y to enable drivers for Altera FPGA Freeze bridges. A
61 freeze bridge is a bridge that exists in the FPGA fabric to
62 isolate one region of the FPGA from the busses while that
63 region is being reprogrammed.
64
Alan Tullfab62662015-10-07 16:36:29 +010065endif # FPGA
66
Alan Tull6a8c3be2015-10-07 16:36:28 +010067endmenu