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gerrit-public.fairphone.software / kernel / msm-4.19 / a1d53dab4f5b37c800d7a20c56e84a96180a8ea6 / . / arch / arm / boot / dts / armada-xp.dtsi
blob: a09998523d40a459955228cea8a52624e3a2ac5d [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
Thomas Petazzoni10b683c2012-08-02 17:13:47 +0200[diff] [blame]15 * Contains definitions specific to the Armada XP SoC that are not
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]16 * common to all Armada SoCs.
17 */
18
19/include/ "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 mpic: interrupt-controller@d0020000 {
26 reg = <0xd0020a00 0x1d0>,
27 <0xd0021870 0x58>;
28 };
29
30 soc {
31 serial@d0012200 {
32 compatible = "ns16550";
33 reg = <0xd0012200 0x100>;
34 reg-shift = <2>;
35 interrupts = <43>;
36 status = "disabled";
37 };
38 serial@d0012300 {
39 compatible = "ns16550";
40 reg = <0xd0012300 0x100>;
41 reg-shift = <2>;
42 interrupts = <44>;
43 status = "disabled";
44 };
45
46 timer@d0020300 {
47 marvell,timer-25Mhz;
48 };
49
Gregory CLEMENT9d202782012-11-17 15:22:24 +0100[diff] [blame]50 coreclk: mvebu-sar@d0018230 {
51 compatible = "marvell,armada-xp-core-clock";
52 reg = <0xd0018230 0x08>;
53 #clock-cells = <1>;
54 };
55
56 cpuclk: clock-complex@d0018700 {
57 #clock-cells = <1>;
58 compatible = "marvell,armada-xp-cpu-clock";
59 reg = <0xd0018700 0xA0>;
60 clocks = <&coreclk 1>;
61 };
62
63 gateclk: clock-gating-control@d0018220 {
64 compatible = "marvell,armada-xp-gating-clock";
65 reg = <0xd0018220 0x4>;
66 clocks = <&coreclk 0>;
67 #clock-cells = <1>;
68 };
69
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]70 system-controller@d0018200 {
71 compatible = "marvell,armada-370-xp-system-controller";
72 reg = <0xd0018200 0x500>;
73 };
Thomas Petazzonia1d53da2012-11-20 16:03:19 +0100[diff] [blame^]74
75 xor@d0060900 {
76 compatible = "marvell,orion-xor";
77 reg = <0xd0060900 0x100
78 0xd0060b00 0x100>;
79 clocks = <&gateclk 22>;
80 status = "okay";
81
82 xor10 {
83 interrupts = <51>;
84 dmacap,memcpy;
85 dmacap,xor;
86 };
87 xor11 {
88 interrupts = <52>;
89 dmacap,memcpy;
90 dmacap,xor;
91 dmacap,memset;
92 };
93 };
94
95 xor@d00f0900 {
96 compatible = "marvell,orion-xor";
97 reg = <0xd00F0900 0x100
98 0xd00F0B00 0x100>;
99 clocks = <&gateclk 28>;
100 status = "okay";
101
102 xor00 {
103 interrupts = <94>;
104 dmacap,memcpy;
105 dmacap,xor;
106 };
107 xor01 {
108 interrupts = <95>;
109 dmacap,memcpy;
110 dmacap,xor;
111 dmacap,memset;
112 };
113 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]114 };
115};