blob: fae2c9a787441540ad586f438024f44dd8c74c9a [file] [log] [blame]
Sascha Hauer198016e2009-02-06 15:38:22 +01001
2#include <linux/module.h>
Fabio Estevambb07d752012-02-29 10:28:08 -03003#include <linux/io.h>
Shawn Guoa2887542013-08-13 16:59:28 +08004#include <linux/of.h>
5#include <linux/slab.h>
6#include <linux/sys_soc.h>
Shawn Guo50f2de62012-09-14 14:14:45 +08007
8#include "hardware.h"
Fabio Estevame7feaaa2013-03-25 09:20:28 -03009#include "common.h"
Sascha Hauer198016e2009-02-06 15:38:22 +010010
11unsigned int __mxc_cpu_type;
12EXPORT_SYMBOL(__mxc_cpu_type);
13
Shawn Guobfefdff2013-08-13 13:54:02 +080014static unsigned int imx_soc_revision;
15
Sascha Hauer198016e2009-02-06 15:38:22 +010016void mxc_set_cpu_type(unsigned int type)
17{
18 __mxc_cpu_type = type;
19}
20
Shawn Guobfefdff2013-08-13 13:54:02 +080021void imx_set_soc_revision(unsigned int rev)
22{
23 imx_soc_revision = rev;
24}
25
26unsigned int imx_get_soc_revision(void)
27{
28 return imx_soc_revision;
29}
30
Fabio Estevam059e58f2011-08-26 13:35:18 +080031void imx_print_silicon_rev(const char *cpu, int srev)
32{
33 if (srev == IMX_CHIP_REVISION_UNKNOWN)
34 pr_info("CPU identified as %s, unknown revision\n", cpu);
35 else
36 pr_info("CPU identified as %s, silicon rev %d.%d\n",
37 cpu, (srev >> 4) & 0xf, srev & 0xf);
38}
Fabio Estevambb07d752012-02-29 10:28:08 -030039
40void __init imx_set_aips(void __iomem *base)
41{
42 unsigned int reg;
43/*
44 * Set all MPROTx to be non-bufferable, trusted for R/W,
45 * not forced to user-mode.
46 */
47 __raw_writel(0x77777777, base + 0x0);
48 __raw_writel(0x77777777, base + 0x4);
49
50/*
51 * Set all OPACRx to be non-bufferable, to not require
52 * supervisor privilege level for access, allow for
53 * write access and untrusted master access.
54 */
55 __raw_writel(0x0, base + 0x40);
56 __raw_writel(0x0, base + 0x44);
57 __raw_writel(0x0, base + 0x48);
58 __raw_writel(0x0, base + 0x4C);
59 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
60 __raw_writel(reg, base + 0x50);
61}
Shawn Guoa2887542013-08-13 16:59:28 +080062
63struct device * __init imx_soc_device_init(void)
64{
65 struct soc_device_attribute *soc_dev_attr;
66 struct soc_device *soc_dev;
67 struct device_node *root;
68 const char *soc_id;
69 int ret;
70
71 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
72 if (!soc_dev_attr)
73 return NULL;
74
75 soc_dev_attr->family = "Freescale i.MX";
76
77 root = of_find_node_by_path("/");
78 ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
79 of_node_put(root);
80 if (ret)
81 goto free_soc;
82
83 switch (__mxc_cpu_type) {
84 case MXC_CPU_MX1:
85 soc_id = "i.MX1";
86 break;
87 case MXC_CPU_MX21:
88 soc_id = "i.MX21";
89 break;
90 case MXC_CPU_MX25:
91 soc_id = "i.MX25";
92 break;
93 case MXC_CPU_MX27:
94 soc_id = "i.MX27";
95 break;
96 case MXC_CPU_MX31:
97 soc_id = "i.MX31";
98 break;
99 case MXC_CPU_MX35:
100 soc_id = "i.MX35";
101 break;
102 case MXC_CPU_MX51:
103 soc_id = "i.MX51";
104 break;
105 case MXC_CPU_MX53:
106 soc_id = "i.MX53";
107 break;
108 case MXC_CPU_IMX6SL:
109 soc_id = "i.MX6SL";
110 break;
111 case MXC_CPU_IMX6DL:
112 soc_id = "i.MX6DL";
113 break;
114 case MXC_CPU_IMX6Q:
115 soc_id = "i.MX6Q";
116 break;
117 default:
118 soc_id = "Unknown";
119 }
120 soc_dev_attr->soc_id = soc_id;
121
122 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
123 (imx_soc_revision >> 4) & 0xf,
124 imx_soc_revision & 0xf);
125 if (!soc_dev_attr->revision)
126 goto free_soc;
127
128 soc_dev = soc_device_register(soc_dev_attr);
129 if (IS_ERR(soc_dev))
130 goto free_rev;
131
132 return soc_device_to_device(soc_dev);
133
134free_rev:
135 kfree(soc_dev_attr->revision);
136free_soc:
137 kfree(soc_dev_attr);
138 return NULL;
139}