Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file contains work-arounds for many known PCI hardware |
| 3 | * bugs. Devices present only on certain architectures (host |
| 4 | * bridges et cetera) should be handled in arch-specific code. |
| 5 | * |
| 6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
| 7 | * |
| 8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
| 9 | * |
David Brownell | 7586269 | 2005-09-23 17:14:37 -0700 | [diff] [blame] | 10 | * Init/reset quirks for USB host controllers should be in the |
| 11 | * USB quirks file, where their drivers can access reuse it. |
| 12 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * The bridge optimization stuff has been removed. If you really |
| 14 | * have a silly BIOS which is unable to set your host bridge right, |
| 15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). |
| 16 | */ |
| 17 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/types.h> |
| 19 | #include <linux/kernel.h> |
Paul Gortmaker | 363c75d | 2011-05-27 09:37:25 -0400 | [diff] [blame] | 20 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/pci.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/delay.h> |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 24 | #include <linux/acpi.h> |
bjorn.helgaas@hp.com | 9f23ed3 | 2007-12-17 14:09:38 -0700 | [diff] [blame] | 25 | #include <linux/kallsyms.h> |
Andreas Petlund | 75e07fc | 2008-11-20 20:42:25 -0800 | [diff] [blame] | 26 | #include <linux/dmi.h> |
Alexander Duyck | 649426e | 2009-03-05 13:57:28 -0500 | [diff] [blame] | 27 | #include <linux/pci-aspm.h> |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 28 | #include <linux/ioport.h> |
Arjan van de Ven | 3209874 | 2012-01-30 20:52:07 -0800 | [diff] [blame] | 29 | #include <linux/sched.h> |
| 30 | #include <linux/ktime.h> |
Rafael J. Wysocki | 93177a7 | 2010-01-02 22:57:24 +0100 | [diff] [blame] | 31 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
Greg KH | bc56b9e | 2005-04-08 14:53:31 +0900 | [diff] [blame] | 32 | #include "pci.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | |
Yuji Shimada | 32a9a682 | 2009-03-16 17:13:39 +0900 | [diff] [blame] | 34 | /* |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 35 | * Decoding should be disabled for a PCI device during BAR sizing to avoid |
| 36 | * conflict. But doing so may cause problems on host bridge and perhaps other |
| 37 | * key system devices. For devices that need to have mmio decoding always-on, |
| 38 | * we need to set the dev->mmio_always_on bit. |
| 39 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 40 | static void quirk_mmio_always_on(struct pci_dev *dev) |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 41 | { |
Yinghai Lu | 52d21b5 | 2012-02-23 23:46:53 -0800 | [diff] [blame] | 42 | dev->mmio_always_on = 1; |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 43 | } |
Yinghai Lu | 52d21b5 | 2012-02-23 23:46:53 -0800 | [diff] [blame] | 44 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
| 45 | PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); |
Jacob Pan | 253d2e5 | 2010-07-16 10:19:22 -0700 | [diff] [blame] | 46 | |
Doug Thompson | bd8481e | 2006-05-08 17:06:09 -0700 | [diff] [blame] | 47 | /* The Mellanox Tavor device gives false positive parity errors |
| 48 | * Mark this device with a broken_parity_status, to allow |
| 49 | * PCI scanning code to "skip" this now blacklisted device. |
| 50 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 51 | static void quirk_mellanox_tavor(struct pci_dev *dev) |
Doug Thompson | bd8481e | 2006-05-08 17:06:09 -0700 | [diff] [blame] | 52 | { |
| 53 | dev->broken_parity_status = 1; /* This device gives false positives */ |
| 54 | } |
| 55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); |
| 56 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); |
| 57 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | /* Deal with broken BIOS'es that neglect to enable passive release, |
| 59 | which can cause problems in combination with the 82441FX/PPro MTRRs */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 60 | static void quirk_passive_release(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | { |
| 62 | struct pci_dev *d = NULL; |
| 63 | unsigned char dlc; |
| 64 | |
| 65 | /* We have to make sure a particular bit is set in the PIIX3 |
| 66 | ISA bridge, so we have to go out and find it. */ |
| 67 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { |
| 68 | pci_read_config_byte(d, 0x82, &dlc); |
| 69 | if (!(dlc & 1<<1)) { |
Adam Jackson | 999da9f | 2008-12-01 14:30:29 -0800 | [diff] [blame] | 70 | dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | dlc |= 1<<1; |
| 72 | pci_write_config_byte(d, 0x82, dlc); |
| 73 | } |
| 74 | } |
| 75 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 76 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
| 77 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround |
| 80 | but VIA don't answer queries. If you happen to have good contacts at VIA |
| 81 | ask them for me please -- Alan |
| 82 | |
| 83 | This appears to be BIOS not version dependent. So presumably there is a |
| 84 | chipset level fix */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 86 | static void quirk_isa_dma_hangs(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | { |
| 88 | if (!isa_dma_bridge_buggy) { |
| 89 | isa_dma_bridge_buggy=1; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 90 | dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | /* |
| 94 | * Its not totally clear which chipsets are the problematic ones |
| 95 | * We know 82C586 and 82C596 variants are affected. |
| 96 | */ |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 97 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
| 98 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); |
| 99 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); |
| 100 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); |
| 101 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); |
| 102 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); |
| 103 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | /* |
Len Brown | 4731fdc | 2010-09-24 21:02:27 -0400 | [diff] [blame] | 106 | * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear |
| 107 | * for some HT machines to use C4 w/o hanging. |
| 108 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 109 | static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) |
Len Brown | 4731fdc | 2010-09-24 21:02:27 -0400 | [diff] [blame] | 110 | { |
| 111 | u32 pmbase; |
| 112 | u16 pm1a; |
| 113 | |
| 114 | pci_read_config_dword(dev, 0x40, &pmbase); |
| 115 | pmbase = pmbase & 0xff80; |
| 116 | pm1a = inw(pmbase); |
| 117 | |
| 118 | if (pm1a & 0x10) { |
| 119 | dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); |
| 120 | outw(0x10, pmbase); |
| 121 | } |
| 122 | } |
| 123 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); |
| 124 | |
| 125 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | * Chipsets where PCI->PCI transfers vanish or hang |
| 127 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 128 | static void quirk_nopcipci(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | { |
| 130 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 131 | dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | pci_pci_problems |= PCIPCI_FAIL; |
| 133 | } |
| 134 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 135 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
| 136 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 137 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 138 | static void quirk_nopciamd(struct pci_dev *dev) |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 139 | { |
| 140 | u8 rev; |
| 141 | pci_read_config_byte(dev, 0x08, &rev); |
| 142 | if (rev == 0x13) { |
| 143 | /* Erratum 24 */ |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 144 | dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 145 | pci_pci_problems |= PCIAGP_FAIL; |
| 146 | } |
| 147 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 148 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | |
| 150 | /* |
| 151 | * Triton requires workarounds to be used by the drivers |
| 152 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 153 | static void quirk_triton(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | { |
| 155 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 156 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | pci_pci_problems |= PCIPCI_TRITON; |
| 158 | } |
| 159 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 160 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
| 161 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); |
| 162 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); |
| 163 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | |
| 165 | /* |
| 166 | * VIA Apollo KT133 needs PCI latency patch |
| 167 | * Made according to a windows driver based patch by George E. Breese |
| 168 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm |
Justin P. Mattock | 631dd1a | 2010-10-18 11:03:14 +0200 | [diff] [blame] | 169 | * and http://www.georgebreese.com/net/software/#PCI |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for |
| 171 | * the info on which Mr Breese based his work. |
| 172 | * |
| 173 | * Updated based on further information from the site and also on |
| 174 | * information provided by VIA |
| 175 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 176 | static void quirk_vialatency(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | { |
| 178 | struct pci_dev *p; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | u8 busarb; |
| 180 | /* Ok we have a potential problem chipset here. Now see if we have |
| 181 | a buggy southbridge */ |
| 182 | |
| 183 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
| 184 | if (p!=NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
| 186 | /* Check for buggy part revisions */ |
Auke Kok | 2b1afa8 | 2007-10-29 14:55:02 -0700 | [diff] [blame] | 187 | if (p->revision < 0x40 || p->revision > 0x42) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | goto exit; |
| 189 | } else { |
| 190 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); |
| 191 | if (p==NULL) /* No problem parts */ |
| 192 | goto exit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | /* Check for buggy part revisions */ |
Auke Kok | 2b1afa8 | 2007-10-29 14:55:02 -0700 | [diff] [blame] | 194 | if (p->revision < 0x10 || p->revision > 0x12) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | goto exit; |
| 196 | } |
| 197 | |
| 198 | /* |
| 199 | * Ok we have the problem. Now set the PCI master grant to |
| 200 | * occur every master grant. The apparent bug is that under high |
| 201 | * PCI load (quite common in Linux of course) you can get data |
| 202 | * loss when the CPU is held off the bus for 3 bus master requests |
| 203 | * This happens to include the IDE controllers.... |
| 204 | * |
| 205 | * VIA only apply this fix when an SB Live! is present but under |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 206 | * both Linux and Windows this isn't enough, and we have seen |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | * corruption without SB Live! but with things like 3 UDMA IDE |
| 208 | * controllers. So we ignore that bit of the VIA recommendation.. |
| 209 | */ |
| 210 | |
| 211 | pci_read_config_byte(dev, 0x76, &busarb); |
| 212 | /* Set bit 4 and bi 5 of byte 76 to 0x01 |
| 213 | "Master priority rotation on every PCI master grant */ |
| 214 | busarb &= ~(1<<5); |
| 215 | busarb |= (1<<4); |
| 216 | pci_write_config_byte(dev, 0x76, busarb); |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 217 | dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | exit: |
| 219 | pci_dev_put(p); |
| 220 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 221 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
| 222 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); |
| 223 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 224 | /* Must restore this on a resume from RAM */ |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 225 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
| 226 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); |
| 227 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | |
| 229 | /* |
| 230 | * VIA Apollo VP3 needs ETBF on BT848/878 |
| 231 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 232 | static void quirk_viaetbf(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | { |
| 234 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 235 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | pci_pci_problems |= PCIPCI_VIAETBF; |
| 237 | } |
| 238 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 239 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 241 | static void quirk_vsfx(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | { |
| 243 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 244 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | pci_pci_problems |= PCIPCI_VSFX; |
| 246 | } |
| 247 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 248 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 249 | |
| 250 | /* |
| 251 | * Ali Magik requires workarounds to be used by the drivers |
| 252 | * that DMA to AGP space. Latency must be set to 0xA and triton |
| 253 | * workaround applied too |
| 254 | * [Info kindly provided by ALi] |
| 255 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 256 | static void quirk_alimagik(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | { |
| 258 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 259 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
| 261 | } |
| 262 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 263 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
| 264 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | |
| 266 | /* |
| 267 | * Natoma has some interesting boundary conditions with Zoran stuff |
| 268 | * at least |
| 269 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 270 | static void quirk_natoma(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | { |
| 272 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 273 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | pci_pci_problems |= PCIPCI_NATOMA; |
| 275 | } |
| 276 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 277 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
| 278 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); |
| 279 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); |
| 280 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); |
| 281 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); |
| 282 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | |
| 284 | /* |
| 285 | * This chip can cause PCI parity errors if config register 0xA0 is read |
| 286 | * while DMAs are occurring. |
| 287 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 288 | static void quirk_citrine(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | { |
| 290 | dev->cfg_size = 0xA0; |
| 291 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 292 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | |
| 294 | /* |
| 295 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
| 296 | * If it's needed, re-allocate the region. |
| 297 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 298 | static void quirk_s3_64M(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | { |
| 300 | struct resource *r = &dev->resource[0]; |
| 301 | |
| 302 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { |
| 303 | r->start = 0; |
| 304 | r->end = 0x3ffffff; |
| 305 | } |
| 306 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 307 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
| 308 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 309 | |
Andres Salomon | 73d2eaa | 2010-02-05 01:42:43 -0500 | [diff] [blame] | 310 | /* |
| 311 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS |
| 312 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. |
| 313 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k |
| 314 | * (which conflicts w/ BAR1's memory range). |
| 315 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 316 | static void quirk_cs5536_vsa(struct pci_dev *dev) |
Andres Salomon | 73d2eaa | 2010-02-05 01:42:43 -0500 | [diff] [blame] | 317 | { |
| 318 | if (pci_resource_len(dev, 0) != 8) { |
| 319 | struct resource *res = &dev->resource[0]; |
| 320 | res->end = res->start + 8 - 1; |
| 321 | dev_info(&dev->dev, "CS5536 ISA bridge bug detected " |
| 322 | "(incorrect header); workaround applied.\n"); |
| 323 | } |
| 324 | } |
| 325 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); |
| 326 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 327 | static void quirk_io_region(struct pci_dev *dev, int port, |
| 328 | unsigned size, int nr, const char *name) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | { |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 330 | u16 region; |
| 331 | struct pci_bus_region bus_region; |
| 332 | struct resource *res = dev->resource + nr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 334 | pci_read_config_word(dev, port, ®ion); |
| 335 | region &= ~(size - 1); |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 336 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 337 | if (!region) |
| 338 | return; |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 339 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 340 | res->name = pci_name(dev); |
| 341 | res->flags = IORESOURCE_IO; |
| 342 | |
| 343 | /* Convert from PCI bus to resource space */ |
| 344 | bus_region.start = region; |
| 345 | bus_region.end = region + size - 1; |
| 346 | pcibios_bus_to_resource(dev, res, &bus_region); |
| 347 | |
| 348 | if (!pci_claim_resource(dev, nr)) |
| 349 | dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); |
| 350 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | |
| 352 | /* |
| 353 | * ATI Northbridge setups MCE the processor if you even |
| 354 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 |
| 355 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 356 | static void quirk_ati_exploding_mce(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 358 | dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
| 360 | request_region(0x3b0, 0x0C, "RadeonIGP"); |
| 361 | request_region(0x3d3, 0x01, "RadeonIGP"); |
| 362 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 363 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | |
| 365 | /* |
| 366 | * Let's make the southbridge information explicit instead |
| 367 | * of having to worry about people probing the ACPI areas, |
| 368 | * for example.. (Yes, it happens, and if you read the wrong |
| 369 | * ACPI register it will put the machine to sleep with no |
| 370 | * way of waking it up again. Bummer). |
| 371 | * |
| 372 | * ALI M7101: Two IO regions pointed to by words at |
| 373 | * 0xE0 (64 bytes of ACPI registers) |
| 374 | * 0xE2 (32 bytes of SMB registers) |
| 375 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 376 | static void quirk_ali7101_acpi(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | { |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 378 | quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
| 379 | quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 381 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 383 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 384 | { |
| 385 | u32 devres; |
| 386 | u32 mask, size, base; |
| 387 | |
| 388 | pci_read_config_dword(dev, port, &devres); |
| 389 | if ((devres & enable) != enable) |
| 390 | return; |
| 391 | mask = (devres >> 16) & 15; |
| 392 | base = devres & 0xffff; |
| 393 | size = 16; |
| 394 | for (;;) { |
| 395 | unsigned bit = size >> 1; |
| 396 | if ((bit & mask) == bit) |
| 397 | break; |
| 398 | size = bit; |
| 399 | } |
| 400 | /* |
| 401 | * For now we only print it out. Eventually we'll want to |
| 402 | * reserve it (at least if it's in the 0x1000+ range), but |
| 403 | * let's get enough confirmation reports first. |
| 404 | */ |
| 405 | base &= -size; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 406 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
| 410 | { |
| 411 | u32 devres; |
| 412 | u32 mask, size, base; |
| 413 | |
| 414 | pci_read_config_dword(dev, port, &devres); |
| 415 | if ((devres & enable) != enable) |
| 416 | return; |
| 417 | base = devres & 0xffff0000; |
| 418 | mask = (devres & 0x3f) << 16; |
| 419 | size = 128 << 16; |
| 420 | for (;;) { |
| 421 | unsigned bit = size >> 1; |
| 422 | if ((bit & mask) == bit) |
| 423 | break; |
| 424 | size = bit; |
| 425 | } |
| 426 | /* |
| 427 | * For now we only print it out. Eventually we'll want to |
| 428 | * reserve it, but let's get enough confirmation reports first. |
| 429 | */ |
| 430 | base &= -size; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 431 | dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 432 | } |
| 433 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 434 | /* |
| 435 | * PIIX4 ACPI: Two IO regions pointed to by longwords at |
| 436 | * 0x40 (64 bytes of ACPI registers) |
Linus Torvalds | 08db2a7 | 2005-10-30 14:40:07 -0800 | [diff] [blame] | 437 | * 0x90 (16 bytes of SMB registers) |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 438 | * and a few strange programmable PIIX4 device resources. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 440 | static void quirk_piix4_acpi(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 441 | { |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 442 | u32 res_a; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 444 | quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
| 445 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
Linus Torvalds | 6693e74 | 2005-10-25 20:40:09 -0700 | [diff] [blame] | 446 | |
| 447 | /* Device resource A has enables for some of the other ones */ |
| 448 | pci_read_config_dword(dev, 0x5c, &res_a); |
| 449 | |
| 450 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); |
| 451 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); |
| 452 | |
| 453 | /* Device resource D is just bitfields for static resources */ |
| 454 | |
| 455 | /* Device 12 enabled? */ |
| 456 | if (res_a & (1 << 29)) { |
| 457 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); |
| 458 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); |
| 459 | } |
| 460 | /* Device 13 enabled? */ |
| 461 | if (res_a & (1 << 30)) { |
| 462 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); |
| 463 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); |
| 464 | } |
| 465 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); |
| 466 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 468 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
| 469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 471 | #define ICH_PMBASE 0x40 |
| 472 | #define ICH_ACPI_CNTL 0x44 |
| 473 | #define ICH4_ACPI_EN 0x10 |
| 474 | #define ICH6_ACPI_EN 0x80 |
| 475 | #define ICH4_GPIOBASE 0x58 |
| 476 | #define ICH4_GPIO_CNTL 0x5c |
| 477 | #define ICH4_GPIO_EN 0x10 |
| 478 | #define ICH6_GPIOBASE 0x48 |
| 479 | #define ICH6_GPIO_CNTL 0x4c |
| 480 | #define ICH6_GPIO_EN 0x10 |
| 481 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 482 | /* |
| 483 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at |
| 484 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) |
| 485 | * 0x58 (64 bytes of GPIO I/O space) |
| 486 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 487 | static void quirk_ich4_lpc_acpi(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | { |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 489 | u8 enable; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | |
Jiri Slaby | 87e3dc3 | 2011-02-28 10:45:10 +0100 | [diff] [blame] | 491 | /* |
| 492 | * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict |
| 493 | * with low legacy (and fixed) ports. We don't know the decoding |
| 494 | * priority and can't tell whether the legacy device or the one created |
| 495 | * here is really at that address. This happens on boards with broken |
| 496 | * BIOSes. |
| 497 | */ |
| 498 | |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 499 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 500 | if (enable & ICH4_ACPI_EN) |
| 501 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, |
| 502 | "ICH4 ACPI/GPIO/TCO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 504 | pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 505 | if (enable & ICH4_GPIO_EN) |
| 506 | quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, |
| 507 | "ICH4 GPIO"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 509 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
| 510 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); |
| 511 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); |
| 512 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); |
| 513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); |
| 514 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); |
| 515 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); |
| 516 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); |
| 517 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); |
| 518 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 519 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 520 | static void ich6_lpc_acpi_gpio(struct pci_dev *dev) |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 521 | { |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 522 | u8 enable; |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 523 | |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 524 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 525 | if (enable & ICH6_ACPI_EN) |
| 526 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, |
| 527 | "ICH6 ACPI/GPIO/TCO"); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 528 | |
Jiri Slaby | cdb9755 | 2011-02-28 10:45:09 +0100 | [diff] [blame] | 529 | pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 530 | if (enable & ICH6_GPIO_EN) |
| 531 | quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, |
| 532 | "ICH6 GPIO"); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 533 | } |
Linus Torvalds | 894886e | 2008-12-06 10:10:10 -0800 | [diff] [blame] | 534 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 535 | static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) |
Linus Torvalds | 894886e | 2008-12-06 10:10:10 -0800 | [diff] [blame] | 536 | { |
| 537 | u32 val; |
| 538 | u32 size, base; |
| 539 | |
| 540 | pci_read_config_dword(dev, reg, &val); |
| 541 | |
| 542 | /* Enabled? */ |
| 543 | if (!(val & 1)) |
| 544 | return; |
| 545 | base = val & 0xfffc; |
| 546 | if (dynsize) { |
| 547 | /* |
| 548 | * This is not correct. It is 16, 32 or 64 bytes depending on |
| 549 | * register D31:F0:ADh bits 5:4. |
| 550 | * |
| 551 | * But this gets us at least _part_ of it. |
| 552 | */ |
| 553 | size = 16; |
| 554 | } else { |
| 555 | size = 128; |
| 556 | } |
| 557 | base &= ~(size-1); |
| 558 | |
| 559 | /* Just print it out for now. We should reserve it after more debugging */ |
| 560 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); |
| 561 | } |
| 562 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 563 | static void quirk_ich6_lpc(struct pci_dev *dev) |
Linus Torvalds | 894886e | 2008-12-06 10:10:10 -0800 | [diff] [blame] | 564 | { |
| 565 | /* Shared ACPI/GPIO decode with all ICH6+ */ |
| 566 | ich6_lpc_acpi_gpio(dev); |
| 567 | |
| 568 | /* ICH6-specific generic IO decode */ |
| 569 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); |
| 570 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); |
| 571 | } |
| 572 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); |
| 573 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); |
| 574 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 575 | static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) |
Linus Torvalds | 894886e | 2008-12-06 10:10:10 -0800 | [diff] [blame] | 576 | { |
| 577 | u32 val; |
| 578 | u32 mask, base; |
| 579 | |
| 580 | pci_read_config_dword(dev, reg, &val); |
| 581 | |
| 582 | /* Enabled? */ |
| 583 | if (!(val & 1)) |
| 584 | return; |
| 585 | |
| 586 | /* |
| 587 | * IO base in bits 15:2, mask in bits 23:18, both |
| 588 | * are dword-based |
| 589 | */ |
| 590 | base = val & 0xfffc; |
| 591 | mask = (val >> 16) & 0xfc; |
| 592 | mask |= 3; |
| 593 | |
| 594 | /* Just print it out for now. We should reserve it after more debugging */ |
| 595 | dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); |
| 596 | } |
| 597 | |
| 598 | /* ICH7-10 has the same common LPC generic IO decode registers */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 599 | static void quirk_ich7_lpc(struct pci_dev *dev) |
Linus Torvalds | 894886e | 2008-12-06 10:10:10 -0800 | [diff] [blame] | 600 | { |
Jean Delvare | 5d9c0a7 | 2011-04-15 10:03:53 +0200 | [diff] [blame] | 601 | /* We share the common ACPI/GPIO decode with ICH6 */ |
Linus Torvalds | 894886e | 2008-12-06 10:10:10 -0800 | [diff] [blame] | 602 | ich6_lpc_acpi_gpio(dev); |
| 603 | |
| 604 | /* And have 4 ICH7+ generic decodes */ |
| 605 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); |
| 606 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); |
| 607 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); |
| 608 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); |
| 609 | } |
| 610 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); |
| 611 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); |
| 612 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); |
| 613 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); |
| 614 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); |
| 615 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); |
| 616 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); |
| 617 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); |
| 618 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); |
| 619 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); |
| 620 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); |
| 621 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); |
| 622 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); |
R.Marek@sh.cvut.cz | 2cea752 | 2005-09-27 21:54:51 +0000 | [diff] [blame] | 623 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | /* |
| 625 | * VIA ACPI: One IO region pointed to by longword at |
| 626 | * 0x48 or 0x20 (256 bytes of ACPI registers) |
| 627 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 628 | static void quirk_vt82c586_acpi(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | { |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 630 | if (dev->revision & 0x10) |
| 631 | quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, |
| 632 | "vt82c586 ACPI"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 634 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 635 | |
| 636 | /* |
| 637 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at |
| 638 | * 0x48 (256 bytes of ACPI registers) |
| 639 | * 0x70 (128 bytes of hardware monitoring register) |
| 640 | * 0x90 (16 bytes of SMB registers) |
| 641 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 642 | static void quirk_vt82c686_acpi(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 643 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | quirk_vt82c586_acpi(dev); |
| 645 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 646 | quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, |
| 647 | "vt82c686 HW-mon"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 649 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 651 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 652 | |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 653 | /* |
| 654 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at |
| 655 | * 0x88 (128 bytes of power management registers) |
| 656 | * 0xd0 (16 bytes of SMB registers) |
| 657 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 658 | static void quirk_vt8235_acpi(struct pci_dev *dev) |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 659 | { |
Yinghai Lu | 65195c7 | 2013-04-12 12:44:15 +0000 | [diff] [blame] | 660 | quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
| 661 | quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); |
Ivan Kokshaysky | 6d85f29 | 2005-08-08 12:55:54 +0400 | [diff] [blame] | 662 | } |
| 663 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); |
| 664 | |
Gabe Black | 1f56f4a | 2009-10-06 09:19:45 -0500 | [diff] [blame] | 665 | /* |
| 666 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: |
| 667 | * Disable fast back-to-back on the secondary bus segment |
| 668 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 669 | static void quirk_xio2000a(struct pci_dev *dev) |
Gabe Black | 1f56f4a | 2009-10-06 09:19:45 -0500 | [diff] [blame] | 670 | { |
| 671 | struct pci_dev *pdev; |
| 672 | u16 command; |
| 673 | |
| 674 | dev_warn(&dev->dev, "TI XIO2000a quirk detected; " |
| 675 | "secondary bus fast back-to-back transfers disabled\n"); |
| 676 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { |
| 677 | pci_read_config_word(pdev, PCI_COMMAND, &command); |
| 678 | if (command & PCI_COMMAND_FAST_BACK) |
| 679 | pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); |
| 680 | } |
| 681 | } |
| 682 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, |
| 683 | quirk_xio2000a); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | |
| 685 | #ifdef CONFIG_X86_IO_APIC |
| 686 | |
| 687 | #include <asm/io_apic.h> |
| 688 | |
| 689 | /* |
| 690 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip |
| 691 | * devices to the external APIC. |
| 692 | * |
| 693 | * TODO: When we have device-specific interrupt routers, |
| 694 | * this code will go away from quirks. |
| 695 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 696 | static void quirk_via_ioapic(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | { |
| 698 | u8 tmp; |
| 699 | |
| 700 | if (nr_ioapics < 1) |
| 701 | tmp = 0; /* nothing routed to external APIC */ |
| 702 | else |
| 703 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ |
| 704 | |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 705 | dev_info(&dev->dev, "%sbling VIA external APIC routing\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | tmp == 0 ? "Disa" : "Ena"); |
| 707 | |
| 708 | /* Offset 0x58: External APIC IRQ output control */ |
| 709 | pci_write_config_byte (dev, 0x58, tmp); |
| 710 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 711 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 712 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | |
| 714 | /* |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 715 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. |
| 716 | * This leads to doubled level interrupt rates. |
| 717 | * Set this bit to get rid of cycle wastage. |
| 718 | * Otherwise uncritical. |
| 719 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 720 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 721 | { |
| 722 | u8 misc_control2; |
| 723 | #define BYPASS_APIC_DEASSERT 8 |
| 724 | |
| 725 | pci_read_config_byte(dev, 0x5B, &misc_control2); |
| 726 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 727 | dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 728 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
| 729 | } |
| 730 | } |
| 731 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 732 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
Karsten Wiese | a174091 | 2005-09-03 15:56:33 -0700 | [diff] [blame] | 733 | |
| 734 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | * The AMD io apic can hang the box when an apic irq is masked. |
| 736 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
| 737 | * is currently marked NoFix |
| 738 | * |
| 739 | * We have multiple reports of hangs with this chipset that went away with |
Alan Cox | 236561e | 2006-09-30 23:27:03 -0700 | [diff] [blame] | 740 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 741 | * of course. However the advice is demonstrably good even if so.. |
| 742 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 743 | static void quirk_amd_ioapic(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | { |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 745 | if (dev->revision >= 0x02) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 746 | dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
| 747 | dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 748 | } |
| 749 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 750 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 752 | static void quirk_ioapic_rmw(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 753 | { |
| 754 | if (dev->devfn == 0 && dev->bus->number == 0) |
| 755 | sis_apic_bug = 1; |
| 756 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 757 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | #endif /* CONFIG_X86_IO_APIC */ |
| 759 | |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 760 | /* |
| 761 | * Some settings of MMRBC can lead to data corruption so block changes. |
| 762 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide |
| 763 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 764 | static void quirk_amd_8131_mmrbc(struct pci_dev *dev) |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 765 | { |
Auke Kok | aa288d4 | 2007-08-27 16:17:47 -0700 | [diff] [blame] | 766 | if (dev->subordinate && dev->revision <= 0x12) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 767 | dev_info(&dev->dev, "AMD8131 rev %x detected; " |
| 768 | "disabling PCI-X MMRBC\n", dev->revision); |
Peter Oruba | d556ad4 | 2007-05-15 13:59:13 +0200 | [diff] [blame] | 769 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
| 770 | } |
| 771 | } |
| 772 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | |
| 774 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | * FIXME: it is questionable that quirk_via_acpi |
| 776 | * is needed. It shows up as an ISA bridge, and does not |
| 777 | * support the PCI_INTERRUPT_LINE register at all. Therefore |
| 778 | * it seems like setting the pci_dev's 'irq' to the |
| 779 | * value of the ACPI SCI interrupt is only done for convenience. |
| 780 | * -jgarzik |
| 781 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 782 | static void quirk_via_acpi(struct pci_dev *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | { |
| 784 | /* |
| 785 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 |
| 786 | */ |
| 787 | u8 irq; |
| 788 | pci_read_config_byte(d, 0x42, &irq); |
| 789 | irq &= 0xf; |
| 790 | if (irq && (irq != 2)) |
| 791 | d->irq = irq; |
| 792 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 793 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
| 794 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 796 | |
| 797 | /* |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 798 | * VIA bridges which have VLink |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 799 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 800 | |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 801 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
| 802 | |
| 803 | static void quirk_via_bridge(struct pci_dev *dev) |
| 804 | { |
| 805 | /* See what bridge we have and find the device ranges */ |
| 806 | switch (dev->device) { |
| 807 | case PCI_DEVICE_ID_VIA_82C686: |
Jean Delvare | cb7468e | 2007-01-31 23:48:12 -0800 | [diff] [blame] | 808 | /* The VT82C686 is special, it attaches to PCI and can have |
| 809 | any device number. All its subdevices are functions of |
| 810 | that single device. */ |
| 811 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); |
| 812 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 813 | break; |
| 814 | case PCI_DEVICE_ID_VIA_8237: |
| 815 | case PCI_DEVICE_ID_VIA_8237A: |
| 816 | via_vlink_dev_lo = 15; |
| 817 | break; |
| 818 | case PCI_DEVICE_ID_VIA_8235: |
| 819 | via_vlink_dev_lo = 16; |
| 820 | break; |
| 821 | case PCI_DEVICE_ID_VIA_8231: |
| 822 | case PCI_DEVICE_ID_VIA_8233_0: |
| 823 | case PCI_DEVICE_ID_VIA_8233A: |
| 824 | case PCI_DEVICE_ID_VIA_8233C_0: |
| 825 | via_vlink_dev_lo = 17; |
| 826 | break; |
| 827 | } |
| 828 | } |
| 829 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); |
| 830 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); |
| 831 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); |
| 832 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); |
| 833 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); |
| 834 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); |
| 835 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); |
| 836 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 837 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 838 | /** |
| 839 | * quirk_via_vlink - VIA VLink IRQ number update |
| 840 | * @dev: PCI device |
| 841 | * |
| 842 | * If the device we are dealing with is on a PIC IRQ we need to |
| 843 | * ensure that the IRQ line register which usually is not relevant |
| 844 | * for PCI cards, is actually written so that interrupts get sent |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 845 | * to the right place. |
| 846 | * We only do this on systems where a VIA south bridge was detected, |
| 847 | * and only for VIA devices on the motherboard (see quirk_via_bridge |
| 848 | * above). |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 849 | */ |
| 850 | |
| 851 | static void quirk_via_vlink(struct pci_dev *dev) |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 852 | { |
| 853 | u8 irq, new_irq; |
| 854 | |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 855 | /* Check if we have VLink at all */ |
| 856 | if (via_vlink_dev_lo == -1) |
Daniel Drake | 09d6029 | 2006-09-25 16:52:19 -0700 | [diff] [blame] | 857 | return; |
| 858 | |
| 859 | new_irq = dev->irq; |
| 860 | |
| 861 | /* Don't quirk interrupts outside the legacy IRQ range */ |
| 862 | if (!new_irq || new_irq > 15) |
| 863 | return; |
| 864 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 865 | /* Internal device ? */ |
Jean Delvare | c06bb5d | 2007-01-30 14:36:09 -0800 | [diff] [blame] | 866 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
| 867 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 868 | return; |
| 869 | |
| 870 | /* This is an internal VLink device on a PIC interrupt. The BIOS |
| 871 | ought to have set this but may not have, so we redo it */ |
| 872 | |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 873 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
| 874 | if (new_irq != irq) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 875 | dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", |
| 876 | irq, new_irq); |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 877 | udelay(15); /* unknown if delay really needed */ |
| 878 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); |
| 879 | } |
| 880 | } |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 881 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
Len Brown | 25be5e6 | 2005-05-27 04:21:50 -0400 | [diff] [blame] | 882 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 883 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | * VIA VT82C598 has its device ID settable and many BIOSes |
| 885 | * set it to the ID of VT82C597 for backward compatibility. |
| 886 | * We need to switch it off to be able to recognize the real |
| 887 | * type of the chip. |
| 888 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 889 | static void quirk_vt82c598_id(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 890 | { |
| 891 | pci_write_config_byte(dev, 0xfc, 0); |
| 892 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); |
| 893 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 894 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | |
| 896 | /* |
| 897 | * CardBus controllers have a legacy base address that enables them |
| 898 | * to respond as i82365 pcmcia controllers. We don't want them to |
| 899 | * do this even if the Linux CardBus driver is not loaded, because |
| 900 | * the Linux i82365 driver does not (and should not) handle CardBus. |
| 901 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 902 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
| 905 | } |
Yinghai Lu | ae9de56 | 2012-02-23 23:46:54 -0800 | [diff] [blame] | 906 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
| 907 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); |
| 908 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
| 909 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | |
| 911 | /* |
| 912 | * Following the PCI ordering rules is optional on the AMD762. I'm not |
| 913 | * sure what the designers were smoking but let's not inhale... |
| 914 | * |
| 915 | * To be fair to AMD, it follows the spec by default, its BIOS people |
| 916 | * who turn it off! |
| 917 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 918 | static void quirk_amd_ordering(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 919 | { |
| 920 | u32 pcic; |
| 921 | pci_read_config_dword(dev, 0x4C, &pcic); |
| 922 | if ((pcic&6)!=6) { |
| 923 | pcic |= 6; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 924 | dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | pci_write_config_dword(dev, 0x4C, pcic); |
| 926 | pci_read_config_dword(dev, 0x84, &pcic); |
| 927 | pcic |= (1<<23); /* Required in this mode */ |
| 928 | pci_write_config_dword(dev, 0x84, pcic); |
| 929 | } |
| 930 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 931 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 932 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 933 | |
| 934 | /* |
| 935 | * DreamWorks provided workaround for Dunord I-3000 problem |
| 936 | * |
| 937 | * This card decodes and responds to addresses not apparently |
| 938 | * assigned to it. We force a larger allocation to ensure that |
| 939 | * nothing gets put too close to it. |
| 940 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 941 | static void quirk_dunord(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 942 | { |
| 943 | struct resource *r = &dev->resource [1]; |
| 944 | r->start = 0; |
| 945 | r->end = 0xffffff; |
| 946 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 947 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | |
| 949 | /* |
| 950 | * i82380FB mobile docking controller: its PCI-to-PCI bridge |
| 951 | * is subtractive decoding (transparent), and does indicate this |
| 952 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 |
| 953 | * instead of 0x01. |
| 954 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 955 | static void quirk_transparent_bridge(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 956 | { |
| 957 | dev->transparent = 1; |
| 958 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 959 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
| 960 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | |
| 962 | /* |
| 963 | * Common misconfiguration of the MediaGX/Geode PCI master that will |
| 964 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 |
Justin P. Mattock | 631dd1a | 2010-10-18 11:03:14 +0200 | [diff] [blame] | 965 | * datasheets found at http://www.national.com/analog for info on what |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 966 | * these bits do. <christer@weinigel.se> |
| 967 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 968 | static void quirk_mediagx_master(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 969 | { |
| 970 | u8 reg; |
| 971 | pci_read_config_byte(dev, 0x41, ®); |
| 972 | if (reg & 2) { |
| 973 | reg &= ~2; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 974 | dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | pci_write_config_byte(dev, 0x41, reg); |
| 976 | } |
| 977 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 978 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
| 979 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | |
| 981 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | * Ensure C0 rev restreaming is off. This is normally done by |
| 983 | * the BIOS but in the odd case it is not the results are corruption |
| 984 | * hence the presence of a Linux check |
| 985 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 986 | static void quirk_disable_pxb(struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 987 | { |
| 988 | u16 config; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 990 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | return; |
| 992 | pci_read_config_word(pdev, 0x40, &config); |
| 993 | if (config & (1<<6)) { |
| 994 | config &= ~(1<<6); |
| 995 | pci_write_config_word(pdev, 0x40, config); |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 996 | dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 997 | } |
| 998 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 999 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1000 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1001 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 1002 | static void quirk_amd_ide_mode(struct pci_dev *pdev) |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 1003 | { |
Shane Huang | 5deab53 | 2009-10-13 11:14:00 +0800 | [diff] [blame] | 1004 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
Crane Cai | 05a7d22 | 2008-02-02 13:56:56 +0800 | [diff] [blame] | 1005 | u8 tmp; |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 1006 | |
Crane Cai | 05a7d22 | 2008-02-02 13:56:56 +0800 | [diff] [blame] | 1007 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
| 1008 | if (tmp == 0x01) { |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 1009 | pci_read_config_byte(pdev, 0x40, &tmp); |
| 1010 | pci_write_config_byte(pdev, 0x40, tmp|1); |
| 1011 | pci_write_config_byte(pdev, 0x9, 1); |
| 1012 | pci_write_config_byte(pdev, 0xa, 6); |
| 1013 | pci_write_config_byte(pdev, 0x40, tmp); |
| 1014 | |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1015 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
Crane Cai | 05a7d22 | 2008-02-02 13:56:56 +0800 | [diff] [blame] | 1016 | dev_info(&pdev->dev, "set SATA to AHCI mode\n"); |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 1017 | } |
| 1018 | } |
Crane Cai | 05a7d22 | 2008-02-02 13:56:56 +0800 | [diff] [blame] | 1019 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1020 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
Crane Cai | 05a7d22 | 2008-02-02 13:56:56 +0800 | [diff] [blame] | 1021 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1022 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
Shane Huang | 5deab53 | 2009-10-13 11:14:00 +0800 | [diff] [blame] | 1023 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
| 1024 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
Shane Huang | fafe5c3d8 | 2013-06-03 18:24:10 +0800 | [diff] [blame] | 1025 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
| 1026 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
Conke Hu | ab17443 | 2006-12-19 13:11:37 -0800 | [diff] [blame] | 1027 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | /* |
| 1029 | * Serverworks CSB5 IDE does not fully support native mode |
| 1030 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1031 | static void quirk_svwks_csb5ide(struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1032 | { |
| 1033 | u8 prog; |
| 1034 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 1035 | if (prog & 5) { |
| 1036 | prog &= ~5; |
| 1037 | pdev->class &= ~5; |
| 1038 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 1039 | /* PCI layer will sort out resources */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1040 | } |
| 1041 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1042 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1043 | |
| 1044 | /* |
| 1045 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same |
| 1046 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1047 | static void quirk_ide_samemode(struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1048 | { |
| 1049 | u8 prog; |
| 1050 | |
| 1051 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); |
| 1052 | |
| 1053 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1054 | dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1055 | prog &= ~5; |
| 1056 | pdev->class &= ~5; |
| 1057 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | } |
| 1059 | } |
Alan Cox | 368c73d | 2006-10-04 00:41:26 +0100 | [diff] [blame] | 1060 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1061 | |
Alan Cox | 979b179 | 2008-07-24 17:18:38 +0100 | [diff] [blame] | 1062 | /* |
| 1063 | * Some ATA devices break if put into D3 |
| 1064 | */ |
| 1065 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1066 | static void quirk_no_ata_d3(struct pci_dev *pdev) |
Alan Cox | 979b179 | 2008-07-24 17:18:38 +0100 | [diff] [blame] | 1067 | { |
Yinghai Lu | faa738b | 2012-02-23 23:46:55 -0800 | [diff] [blame] | 1068 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; |
Alan Cox | 979b179 | 2008-07-24 17:18:38 +0100 | [diff] [blame] | 1069 | } |
Yinghai Lu | faa738b | 2012-02-23 23:46:55 -0800 | [diff] [blame] | 1070 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ |
| 1071 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, |
| 1072 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
| 1073 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
| 1074 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
Alan Cox | 7a661c6 | 2009-06-24 16:02:27 +0100 | [diff] [blame] | 1075 | /* ALi loses some register settings that we cannot then restore */ |
Yinghai Lu | faa738b | 2012-02-23 23:46:55 -0800 | [diff] [blame] | 1076 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, |
| 1077 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
Alan Cox | 7a661c6 | 2009-06-24 16:02:27 +0100 | [diff] [blame] | 1078 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures |
| 1079 | occur when mode detecting */ |
Yinghai Lu | faa738b | 2012-02-23 23:46:55 -0800 | [diff] [blame] | 1080 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, |
| 1081 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
Alan Cox | 979b179 | 2008-07-24 17:18:38 +0100 | [diff] [blame] | 1082 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | /* This was originally an Alpha specific thing, but it really fits here. |
| 1084 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
| 1085 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1086 | static void quirk_eisa_bridge(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1087 | { |
| 1088 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; |
| 1089 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1090 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | |
Johannes Goecke | 7daa0c4 | 2006-04-20 02:43:17 -0700 | [diff] [blame] | 1092 | |
| 1093 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1094 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge |
| 1095 | * is not activated. The myth is that Asus said that they do not want the |
| 1096 | * users to be irritated by just another PCI Device in the Win98 device |
| 1097 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
| 1098 | * package 2.7.0 for details) |
| 1099 | * |
| 1100 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
| 1101 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1102 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
| 1103 | * is either the Host bridge (preferred) or on-board VGA controller. |
Jean Delvare | 9208ee8 | 2007-03-24 16:56:44 +0100 | [diff] [blame] | 1104 | * |
| 1105 | * Note that we used to unhide the SMBus that way on Toshiba laptops |
| 1106 | * (Satellite A40 and Tecra M2) but then found that the thermal management |
| 1107 | * was done by SMM code, which could cause unsynchronized concurrent |
| 1108 | * accesses to the SMBus registers, with potentially bad effects. Thus you |
| 1109 | * should be very careful when adding new entries: if SMM is accessing the |
| 1110 | * Intel SMBus, this is a very good reason to leave it hidden. |
Jean Delvare | a99acc8 | 2008-03-28 14:16:04 -0700 | [diff] [blame] | 1111 | * |
| 1112 | * Likewise, many recent laptops use ACPI for thermal management. If the |
| 1113 | * ACPI DSDT code accesses the SMBus, then Linux should not access it |
| 1114 | * natively, and keeping the SMBus hidden is the right thing to do. If you |
| 1115 | * are about to add an entry in the table below, please first disassemble |
| 1116 | * the DSDT and double-check that there is no code accessing the SMBus. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1117 | */ |
Vivek Goyal | 9d24a81 | 2007-01-11 01:52:44 +0100 | [diff] [blame] | 1118 | static int asus_hides_smbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1120 | static void asus_hides_smbus_hostbridge(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | { |
| 1122 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 1123 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) |
| 1124 | switch(dev->subsystem_device) { |
Jean Delvare | a00db37 | 2005-06-29 17:04:06 +0200 | [diff] [blame] | 1125 | case 0x8025: /* P4B-LX */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1126 | case 0x8070: /* P4B */ |
| 1127 | case 0x8088: /* P4B533 */ |
| 1128 | case 0x1626: /* L3C notebook */ |
| 1129 | asus_hides_smbus = 1; |
| 1130 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1131 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1132 | switch(dev->subsystem_device) { |
| 1133 | case 0x80b1: /* P4GE-V */ |
| 1134 | case 0x80b2: /* P4PE */ |
| 1135 | case 0x8093: /* P4B533-V */ |
| 1136 | asus_hides_smbus = 1; |
| 1137 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1138 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1139 | switch(dev->subsystem_device) { |
| 1140 | case 0x8030: /* P4T533 */ |
| 1141 | asus_hides_smbus = 1; |
| 1142 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1143 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1144 | switch (dev->subsystem_device) { |
| 1145 | case 0x8070: /* P4G8X Deluxe */ |
| 1146 | asus_hides_smbus = 1; |
| 1147 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1148 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
Jean Delvare | 321311a | 2006-07-31 08:53:15 +0200 | [diff] [blame] | 1149 | switch (dev->subsystem_device) { |
| 1150 | case 0x80c9: /* PU-DLS */ |
| 1151 | asus_hides_smbus = 1; |
| 1152 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1153 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1154 | switch (dev->subsystem_device) { |
| 1155 | case 0x1751: /* M2N notebook */ |
| 1156 | case 0x1821: /* M5N notebook */ |
Mats Erik Andersson | 4096ed0 | 2009-05-12 12:05:23 +0200 | [diff] [blame] | 1157 | case 0x1897: /* A6L notebook */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1158 | asus_hides_smbus = 1; |
| 1159 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1160 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1161 | switch (dev->subsystem_device) { |
| 1162 | case 0x184b: /* W1N notebook */ |
| 1163 | case 0x186a: /* M6Ne notebook */ |
| 1164 | asus_hides_smbus = 1; |
| 1165 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1166 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
Jean Delvare | 2e45785 | 2007-01-05 09:17:56 +0100 | [diff] [blame] | 1167 | switch (dev->subsystem_device) { |
| 1168 | case 0x80f2: /* P4P800-X */ |
| 1169 | asus_hides_smbus = 1; |
| 1170 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1171 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1172 | switch (dev->subsystem_device) { |
| 1173 | case 0x1882: /* M6V notebook */ |
Jean Delvare | 2d1e1c7 | 2006-04-01 16:46:35 +0200 | [diff] [blame] | 1174 | case 0x1977: /* A6VA notebook */ |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1175 | asus_hides_smbus = 1; |
| 1176 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1177 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
| 1178 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1179 | switch(dev->subsystem_device) { |
| 1180 | case 0x088C: /* HP Compaq nc8000 */ |
| 1181 | case 0x0890: /* HP Compaq nc6000 */ |
| 1182 | asus_hides_smbus = 1; |
| 1183 | } |
Jean Delvare | 2f2d39d | 2007-01-05 11:23:15 +0100 | [diff] [blame] | 1184 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1185 | switch (dev->subsystem_device) { |
| 1186 | case 0x12bc: /* HP D330L */ |
Jean Delvare | e3b1bd5 | 2005-09-21 22:26:31 +0200 | [diff] [blame] | 1187 | case 0x12bd: /* HP D530 */ |
Michal Miroslaw | 74c5742 | 2009-05-12 13:49:25 -0700 | [diff] [blame] | 1188 | case 0x006a: /* HP Compaq nx9500 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1189 | asus_hides_smbus = 1; |
| 1190 | } |
Jean Delvare | 677cc64 | 2007-11-21 18:29:06 +0100 | [diff] [blame] | 1191 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
| 1192 | switch (dev->subsystem_device) { |
| 1193 | case 0x12bf: /* HP xw4100 */ |
| 1194 | asus_hides_smbus = 1; |
| 1195 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1196 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
| 1197 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1198 | switch(dev->subsystem_device) { |
| 1199 | case 0xC00C: /* Samsung P35 notebook */ |
| 1200 | asus_hides_smbus = 1; |
| 1201 | } |
Rumen Ivanov Zarev | c87f883 | 2005-09-06 13:39:32 -0700 | [diff] [blame] | 1202 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
| 1203 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
| 1204 | switch(dev->subsystem_device) { |
| 1205 | case 0x0058: /* Compaq Evo N620c */ |
| 1206 | asus_hides_smbus = 1; |
| 1207 | } |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1208 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
| 1209 | switch(dev->subsystem_device) { |
| 1210 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ |
| 1211 | /* Motherboard doesn't have Host bridge |
| 1212 | * subvendor/subdevice IDs, therefore checking |
| 1213 | * its on-board VGA controller */ |
| 1214 | asus_hides_smbus = 1; |
| 1215 | } |
David O'Shea | 8293b0f | 2009-03-02 09:51:13 +0100 | [diff] [blame] | 1216 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
Jean Delvare | 10260d9 | 2008-06-04 13:53:31 +0200 | [diff] [blame] | 1217 | switch(dev->subsystem_device) { |
| 1218 | case 0x00b8: /* Compaq Evo D510 CMT */ |
| 1219 | case 0x00b9: /* Compaq Evo D510 SFF */ |
Jean Delvare | 6b5096e | 2009-07-28 11:49:19 +0200 | [diff] [blame] | 1220 | case 0x00ba: /* Compaq Evo D510 USDT */ |
David O'Shea | 8293b0f | 2009-03-02 09:51:13 +0100 | [diff] [blame] | 1221 | /* Motherboard doesn't have Host bridge |
| 1222 | * subvendor/subdevice IDs and on-board VGA |
| 1223 | * controller is disabled if an AGP card is |
| 1224 | * inserted, therefore checking USB UHCI |
| 1225 | * Controller #1 */ |
Jean Delvare | 10260d9 | 2008-06-04 13:53:31 +0200 | [diff] [blame] | 1226 | asus_hides_smbus = 1; |
| 1227 | } |
Krzysztof Helt | 27e4685 | 2008-06-08 13:47:02 +0200 | [diff] [blame] | 1228 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
| 1229 | switch (dev->subsystem_device) { |
| 1230 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ |
| 1231 | /* Motherboard doesn't have host bridge |
| 1232 | * subvendor/subdevice IDs, therefore checking |
| 1233 | * its on-board VGA controller */ |
| 1234 | asus_hides_smbus = 1; |
| 1235 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1236 | } |
| 1237 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1238 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
| 1239 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); |
| 1240 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); |
| 1241 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); |
Jean Delvare | 677cc64 | 2007-11-21 18:29:06 +0100 | [diff] [blame] | 1242 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1243 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
| 1244 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); |
| 1245 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); |
| 1246 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); |
| 1247 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1248 | |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1249 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); |
David O'Shea | 8293b0f | 2009-03-02 09:51:13 +0100 | [diff] [blame] | 1250 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
Krzysztof Helt | 27e4685 | 2008-06-08 13:47:02 +0200 | [diff] [blame] | 1251 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
gw.kernel@tnode.com | d7698ed | 2007-08-23 21:22:04 +0200 | [diff] [blame] | 1252 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1253 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1254 | { |
| 1255 | u16 val; |
| 1256 | |
| 1257 | if (likely(!asus_hides_smbus)) |
| 1258 | return; |
| 1259 | |
| 1260 | pci_read_config_word(dev, 0xF2, &val); |
| 1261 | if (val & 0x8) { |
| 1262 | pci_write_config_word(dev, 0xF2, val & (~0x8)); |
| 1263 | pci_read_config_word(dev, 0xF2, &val); |
| 1264 | if (val & 0x8) |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1265 | dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | else |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1267 | dev_info(&dev->dev, "Enabled i801 SMBus device\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | } |
| 1269 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1270 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
| 1271 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); |
| 1272 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); |
| 1273 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); |
| 1274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); |
| 1275 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); |
| 1276 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1277 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
| 1278 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); |
| 1279 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); |
| 1280 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); |
| 1281 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); |
| 1282 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); |
| 1283 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1284 | |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1285 | /* It appears we just have one such device. If not, we have a warning */ |
| 1286 | static void __iomem *asus_rcba_base; |
| 1287 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1288 | { |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1289 | u32 rcba; |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1290 | |
| 1291 | if (likely(!asus_hides_smbus)) |
| 1292 | return; |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1293 | WARN_ON(asus_rcba_base); |
| 1294 | |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1295 | pci_read_config_dword(dev, 0xF0, &rcba); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1296 | /* use bits 31:14, 16 kB aligned */ |
| 1297 | asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); |
| 1298 | if (asus_rcba_base == NULL) |
| 1299 | return; |
| 1300 | } |
| 1301 | |
| 1302 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) |
| 1303 | { |
| 1304 | u32 val; |
| 1305 | |
| 1306 | if (likely(!asus_hides_smbus || !asus_rcba_base)) |
| 1307 | return; |
| 1308 | /* read the Function Disable register, dword mode only */ |
| 1309 | val = readl(asus_rcba_base + 0x3418); |
| 1310 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ |
| 1311 | } |
| 1312 | |
| 1313 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) |
| 1314 | { |
| 1315 | if (likely(!asus_hides_smbus || !asus_rcba_base)) |
| 1316 | return; |
| 1317 | iounmap(asus_rcba_base); |
| 1318 | asus_rcba_base = NULL; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1319 | dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); |
R.Marek@sh.cvut.cz | acc0663 | 2005-09-29 08:35:41 +0000 | [diff] [blame] | 1320 | } |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1321 | |
| 1322 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) |
| 1323 | { |
| 1324 | asus_hides_smbus_lpc_ich6_suspend(dev); |
| 1325 | asus_hides_smbus_lpc_ich6_resume_early(dev); |
| 1326 | asus_hides_smbus_lpc_ich6_resume(dev); |
| 1327 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1328 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1329 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
| 1330 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); |
| 1331 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); |
Carl-Daniel Hailfinger | ce007ea | 2006-05-15 09:44:33 -0700 | [diff] [blame] | 1332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | /* |
| 1334 | * SiS 96x south bridge: BIOS typically hides SMBus device... |
| 1335 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1336 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1337 | { |
| 1338 | u8 val = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1339 | pci_read_config_byte(dev, 0x77, &val); |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1340 | if (val & 0x10) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1341 | dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1342 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
| 1343 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1345 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
| 1346 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); |
| 1347 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); |
| 1348 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1349 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
| 1350 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); |
| 1351 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); |
| 1352 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1353 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | /* |
| 1355 | * ... This is further complicated by the fact that some SiS96x south |
| 1356 | * bridges pretend to be 85C503/5513 instead. In that case see if we |
| 1357 | * spotted a compatible north bridge to make sure. |
| 1358 | * (pci_find_device doesn't work yet) |
| 1359 | * |
| 1360 | * We can also enable the sis96x bit in the discovery register.. |
| 1361 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1362 | #define SIS_DETECT_REGISTER 0x40 |
| 1363 | |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1364 | static void quirk_sis_503(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1365 | { |
| 1366 | u8 reg; |
| 1367 | u16 devid; |
| 1368 | |
| 1369 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); |
| 1370 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); |
| 1371 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); |
| 1372 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { |
| 1373 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); |
| 1374 | return; |
| 1375 | } |
| 1376 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1377 | /* |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1378 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
| 1379 | * hand in case it has already been processed. |
| 1380 | * (depends on link order, which is apparently not guaranteed) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1381 | */ |
| 1382 | dev->device = devid; |
Mark M. Hoffman | 2f5c33b | 2007-01-08 22:11:29 -0500 | [diff] [blame] | 1383 | quirk_sis_96x_smbus(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1384 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1385 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1386 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1389 | /* |
| 1390 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller |
| 1391 | * and MC97 modem controller are disabled when a second PCI soundcard is |
| 1392 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. |
| 1393 | * -- bjd |
| 1394 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1395 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1396 | { |
| 1397 | u8 val; |
| 1398 | int asus_hides_ac97 = 0; |
| 1399 | |
| 1400 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
| 1401 | if (dev->device == PCI_DEVICE_ID_VIA_8237) |
| 1402 | asus_hides_ac97 = 1; |
| 1403 | } |
| 1404 | |
| 1405 | if (!asus_hides_ac97) |
| 1406 | return; |
| 1407 | |
| 1408 | pci_read_config_byte(dev, 0x50, &val); |
| 1409 | if (val & 0xc0) { |
| 1410 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); |
| 1411 | pci_read_config_byte(dev, 0x50, &val); |
| 1412 | if (val & 0xc0) |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1413 | dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1414 | else |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1415 | dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); |
Bauke Jan Douma | e5548e9 | 2006-02-28 21:44:36 +0100 | [diff] [blame] | 1416 | } |
| 1417 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1418 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1419 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1420 | |
Tejun Heo | 7796705 | 2006-08-19 03:54:39 +0900 | [diff] [blame] | 1421 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1422 | |
| 1423 | /* |
| 1424 | * If we are using libata we can drive this chip properly but must |
| 1425 | * do this early on to make the additional device appear during |
| 1426 | * the PCI scanning. |
| 1427 | */ |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1428 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1429 | { |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 1430 | u32 conf1, conf5, class; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1431 | u8 hdr; |
| 1432 | |
| 1433 | /* Only poke fn 0 */ |
| 1434 | if (PCI_FUNC(pdev->devfn)) |
| 1435 | return; |
| 1436 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1437 | pci_read_config_dword(pdev, 0x40, &conf1); |
| 1438 | pci_read_config_dword(pdev, 0x80, &conf5); |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1439 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1440 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
| 1441 | conf5 &= ~(1 << 24); /* Clear bit 24 */ |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1442 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1443 | switch (pdev->device) { |
Tejun Heo | 4daedcf | 2010-06-03 11:57:04 +0200 | [diff] [blame] | 1444 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
| 1445 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ |
Tejun Heo | 5b6ae5b | 2010-07-30 11:42:42 +0200 | [diff] [blame] | 1446 | case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1447 | /* The controller should be in single function ahci mode */ |
| 1448 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ |
| 1449 | break; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1450 | |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1451 | case PCI_DEVICE_ID_JMICRON_JMB365: |
| 1452 | case PCI_DEVICE_ID_JMICRON_JMB366: |
| 1453 | /* Redirect IDE second PATA port to the right spot */ |
| 1454 | conf5 |= (1 << 24); |
| 1455 | /* Fall through */ |
| 1456 | case PCI_DEVICE_ID_JMICRON_JMB361: |
| 1457 | case PCI_DEVICE_ID_JMICRON_JMB363: |
Tejun Heo | 5b6ae5b | 2010-07-30 11:42:42 +0200 | [diff] [blame] | 1458 | case PCI_DEVICE_ID_JMICRON_JMB369: |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1459 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
| 1460 | /* Set the class codes correctly and then direct IDE 0 */ |
Tejun Heo | 3a9e3a5 | 2007-10-23 15:27:31 +0900 | [diff] [blame] | 1461 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1462 | break; |
| 1463 | |
| 1464 | case PCI_DEVICE_ID_JMICRON_JMB368: |
| 1465 | /* The controller should be in single function IDE mode */ |
| 1466 | conf1 |= 0x00C00000; /* Set 22, 23 */ |
| 1467 | break; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1468 | } |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1469 | |
| 1470 | pci_write_config_dword(pdev, 0x40, conf1); |
| 1471 | pci_write_config_dword(pdev, 0x80, conf5); |
| 1472 | |
| 1473 | /* Update pdev accordingly */ |
| 1474 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); |
| 1475 | pdev->hdr_type = hdr & 0x7f; |
| 1476 | pdev->multifunction = !!(hdr & 0x80); |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 1477 | |
| 1478 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); |
| 1479 | pdev->class = class >> 8; |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1480 | } |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1481 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
| 1482 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
Tejun Heo | 4daedcf | 2010-06-03 11:57:04 +0200 | [diff] [blame] | 1483 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1484 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
Tejun Heo | 5b6ae5b | 2010-07-30 11:42:42 +0200 | [diff] [blame] | 1485 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
Tejun Heo | 5ee2ae7 | 2007-02-26 20:16:13 +0900 | [diff] [blame] | 1486 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
| 1487 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); |
| 1488 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
Tejun Heo | 5b6ae5b | 2010-07-30 11:42:42 +0200 | [diff] [blame] | 1489 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1490 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
| 1491 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
Tejun Heo | 4daedcf | 2010-06-03 11:57:04 +0200 | [diff] [blame] | 1492 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1493 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
Tejun Heo | 5b6ae5b | 2010-07-30 11:42:42 +0200 | [diff] [blame] | 1494 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1495 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
| 1496 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); |
| 1497 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
Tejun Heo | 5b6ae5b | 2010-07-30 11:42:42 +0200 | [diff] [blame] | 1498 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
Alan Cox | 15e0c69 | 2006-07-12 15:05:41 +0100 | [diff] [blame] | 1499 | |
| 1500 | #endif |
| 1501 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1502 | #ifdef CONFIG_X86_IO_APIC |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1503 | static void quirk_alder_ioapic(struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1504 | { |
| 1505 | int i; |
| 1506 | |
| 1507 | if ((pdev->class >> 8) != 0xff00) |
| 1508 | return; |
| 1509 | |
| 1510 | /* the first BAR is the location of the IO APIC...we must |
| 1511 | * not touch this (and it's already covered by the fixmap), so |
| 1512 | * forcibly insert it into the resource tree */ |
| 1513 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
| 1514 | insert_resource(&iomem_resource, &pdev->resource[0]); |
| 1515 | |
| 1516 | /* The next five BARs all seem to be rubbish, so just clean |
| 1517 | * them out */ |
| 1518 | for (i=1; i < 6; i++) { |
| 1519 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
| 1520 | } |
| 1521 | |
| 1522 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1523 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1524 | #endif |
| 1525 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1526 | static void quirk_pcie_mch(struct pci_dev *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1527 | { |
Eric W. Biederman | 0ba379e | 2009-09-06 21:48:35 -0700 | [diff] [blame] | 1528 | pci_msi_off(pdev); |
| 1529 | pdev->no_msi = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1530 | } |
Andrew Morton | 652c538 | 2007-11-21 15:07:13 -0800 | [diff] [blame] | 1531 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
| 1532 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); |
| 1533 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1534 | |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1535 | |
| 1536 | /* |
| 1537 | * It's possible for the MSI to get corrupted if shpc and acpi |
| 1538 | * are used together on certain PXH-based systems. |
| 1539 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1540 | static void quirk_pcie_pxh(struct pci_dev *dev) |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1541 | { |
Eric W. Biederman | f5f2b13 | 2007-03-05 00:30:07 -0800 | [diff] [blame] | 1542 | pci_msi_off(dev); |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1543 | dev->no_msi = 1; |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1544 | dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1545 | } |
| 1546 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); |
| 1547 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); |
| 1548 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); |
| 1549 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); |
| 1550 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); |
| 1551 | |
Kristen Carlson Accardi | ffadcc2 | 2006-07-12 08:59:00 -0700 | [diff] [blame] | 1552 | /* |
| 1553 | * Some Intel PCI Express chipsets have trouble with downstream |
| 1554 | * device power management. |
| 1555 | */ |
| 1556 | static void quirk_intel_pcie_pm(struct pci_dev * dev) |
| 1557 | { |
| 1558 | pci_pm_d3_delay = 120; |
| 1559 | dev->no_d1d2 = 1; |
| 1560 | } |
| 1561 | |
| 1562 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
| 1563 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); |
| 1564 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); |
| 1565 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); |
| 1566 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); |
| 1567 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); |
| 1568 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); |
| 1569 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); |
| 1570 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); |
| 1571 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); |
| 1572 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); |
| 1573 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); |
| 1574 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); |
| 1575 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); |
| 1576 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); |
| 1577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); |
| 1578 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); |
| 1579 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); |
| 1580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); |
| 1581 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); |
| 1582 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); |
Kristen Accardi | 4602b88 | 2005-08-16 15:15:58 -0700 | [diff] [blame] | 1583 | |
Stefan Assmann | 426b3b8 | 2008-06-11 16:35:16 +0200 | [diff] [blame] | 1584 | #ifdef CONFIG_X86_IO_APIC |
| 1585 | /* |
Stefan Assmann | e1d3a90 | 2008-06-11 16:35:17 +0200 | [diff] [blame] | 1586 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, |
| 1587 | * remap the original interrupt in the linux kernel to the boot interrupt, so |
| 1588 | * that a PCI device's interrupt handler is installed on the boot interrupt |
| 1589 | * line instead. |
| 1590 | */ |
| 1591 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) |
| 1592 | { |
Stefan Assmann | 41b9eb2 | 2008-07-15 13:48:55 +0200 | [diff] [blame] | 1593 | if (noioapicquirk || noioapicreroute) |
Stefan Assmann | e1d3a90 | 2008-06-11 16:35:17 +0200 | [diff] [blame] | 1594 | return; |
| 1595 | |
| 1596 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; |
Bjorn Helgaas | fdcdaf6 | 2009-09-14 14:36:41 -0600 | [diff] [blame] | 1597 | dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", |
| 1598 | dev->vendor, dev->device); |
Stefan Assmann | e1d3a90 | 2008-06-11 16:35:17 +0200 | [diff] [blame] | 1599 | } |
Olaf Dabrunz | 88d1dce | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1600 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
| 1601 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); |
| 1602 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); |
| 1603 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); |
| 1604 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); |
| 1605 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); |
| 1606 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); |
| 1607 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); |
| 1608 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
| 1609 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); |
| 1610 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); |
| 1611 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); |
| 1612 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); |
| 1613 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); |
| 1614 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); |
| 1615 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); |
Stefan Assmann | e1d3a90 | 2008-06-11 16:35:17 +0200 | [diff] [blame] | 1616 | |
| 1617 | /* |
Stefan Assmann | 426b3b8 | 2008-06-11 16:35:16 +0200 | [diff] [blame] | 1618 | * On some chipsets we can disable the generation of legacy INTx boot |
| 1619 | * interrupts. |
| 1620 | */ |
| 1621 | |
| 1622 | /* |
| 1623 | * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no |
| 1624 | * 300641-004US, section 5.7.3. |
| 1625 | */ |
| 1626 | #define INTEL_6300_IOAPIC_ABAR 0x40 |
| 1627 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) |
| 1628 | |
| 1629 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) |
| 1630 | { |
| 1631 | u16 pci_config_word; |
| 1632 | |
| 1633 | if (noioapicquirk) |
| 1634 | return; |
| 1635 | |
| 1636 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); |
| 1637 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; |
| 1638 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); |
| 1639 | |
Bjorn Helgaas | fdcdaf6 | 2009-09-14 14:36:41 -0600 | [diff] [blame] | 1640 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
| 1641 | dev->vendor, dev->device); |
Stefan Assmann | 426b3b8 | 2008-06-11 16:35:16 +0200 | [diff] [blame] | 1642 | } |
Olaf Dabrunz | 88d1dce | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1643 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
| 1644 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
Olaf Dabrunz | 7725118 | 2008-07-08 15:59:47 +0200 | [diff] [blame] | 1645 | |
| 1646 | /* |
| 1647 | * disable boot interrupts on HT-1000 |
| 1648 | */ |
| 1649 | #define BC_HT1000_FEATURE_REG 0x64 |
| 1650 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) |
| 1651 | #define BC_HT1000_MAP_IDX 0xC00 |
| 1652 | #define BC_HT1000_MAP_DATA 0xC01 |
| 1653 | |
| 1654 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) |
| 1655 | { |
| 1656 | u32 pci_config_dword; |
| 1657 | u8 irq; |
| 1658 | |
| 1659 | if (noioapicquirk) |
| 1660 | return; |
| 1661 | |
| 1662 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); |
| 1663 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | |
| 1664 | BC_HT1000_PIC_REGS_ENABLE); |
| 1665 | |
| 1666 | for (irq = 0x10; irq < 0x10 + 32; irq++) { |
| 1667 | outb(irq, BC_HT1000_MAP_IDX); |
| 1668 | outb(0x00, BC_HT1000_MAP_DATA); |
| 1669 | } |
| 1670 | |
| 1671 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); |
| 1672 | |
Bjorn Helgaas | fdcdaf6 | 2009-09-14 14:36:41 -0600 | [diff] [blame] | 1673 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
| 1674 | dev->vendor, dev->device); |
Olaf Dabrunz | 7725118 | 2008-07-08 15:59:47 +0200 | [diff] [blame] | 1675 | } |
Olaf Dabrunz | 88d1dce | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1676 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
| 1677 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1678 | |
| 1679 | /* |
| 1680 | * disable boot interrupts on AMD and ATI chipsets |
| 1681 | */ |
| 1682 | /* |
| 1683 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 |
| 1684 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode |
| 1685 | * (due to an erratum). |
| 1686 | */ |
| 1687 | #define AMD_813X_MISC 0x40 |
| 1688 | #define AMD_813X_NOIOAMODE (1<<0) |
Stefan Assmann | 4fd8bdc | 2009-10-27 08:57:42 +0100 | [diff] [blame] | 1689 | #define AMD_813X_REV_B1 0x12 |
Stefan Assmann | bbe1944 | 2009-02-26 10:46:48 -0800 | [diff] [blame] | 1690 | #define AMD_813X_REV_B2 0x13 |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1691 | |
| 1692 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) |
| 1693 | { |
| 1694 | u32 pci_config_dword; |
| 1695 | |
| 1696 | if (noioapicquirk) |
| 1697 | return; |
Stefan Assmann | 4fd8bdc | 2009-10-27 08:57:42 +0100 | [diff] [blame] | 1698 | if ((dev->revision == AMD_813X_REV_B1) || |
| 1699 | (dev->revision == AMD_813X_REV_B2)) |
Stefan Assmann | bbe1944 | 2009-02-26 10:46:48 -0800 | [diff] [blame] | 1700 | return; |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1701 | |
| 1702 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); |
| 1703 | pci_config_dword &= ~AMD_813X_NOIOAMODE; |
| 1704 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); |
| 1705 | |
Bjorn Helgaas | fdcdaf6 | 2009-09-14 14:36:41 -0600 | [diff] [blame] | 1706 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
| 1707 | dev->vendor, dev->device); |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1708 | } |
Stefan Assmann | 4fd8bdc | 2009-10-27 08:57:42 +0100 | [diff] [blame] | 1709 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
| 1710 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
| 1711 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
| 1712 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1713 | |
| 1714 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 |
| 1715 | |
| 1716 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) |
| 1717 | { |
| 1718 | u16 pci_config_word; |
| 1719 | |
| 1720 | if (noioapicquirk) |
| 1721 | return; |
| 1722 | |
| 1723 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); |
| 1724 | if (!pci_config_word) { |
Bjorn Helgaas | fdcdaf6 | 2009-09-14 14:36:41 -0600 | [diff] [blame] | 1725 | dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " |
| 1726 | "already disabled\n", dev->vendor, dev->device); |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1727 | return; |
| 1728 | } |
| 1729 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); |
Bjorn Helgaas | fdcdaf6 | 2009-09-14 14:36:41 -0600 | [diff] [blame] | 1730 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
| 1731 | dev->vendor, dev->device); |
Olaf Dabrunz | 542622d | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1732 | } |
Olaf Dabrunz | 88d1dce | 2008-07-08 15:59:48 +0200 | [diff] [blame] | 1733 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
| 1734 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
Stefan Assmann | 426b3b8 | 2008-06-11 16:35:16 +0200 | [diff] [blame] | 1735 | #endif /* CONFIG_X86_IO_APIC */ |
| 1736 | |
Sergei Shtylyov | 33dced2 | 2007-02-07 18:18:45 +0100 | [diff] [blame] | 1737 | /* |
| 1738 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size |
| 1739 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. |
| 1740 | * Re-allocate the region if needed... |
| 1741 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1742 | static void quirk_tc86c001_ide(struct pci_dev *dev) |
Sergei Shtylyov | 33dced2 | 2007-02-07 18:18:45 +0100 | [diff] [blame] | 1743 | { |
| 1744 | struct resource *r = &dev->resource[0]; |
| 1745 | |
| 1746 | if (r->start & 0x8) { |
| 1747 | r->start = 0; |
| 1748 | r->end = 0xf; |
| 1749 | } |
| 1750 | } |
| 1751 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, |
| 1752 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, |
| 1753 | quirk_tc86c001_ide); |
| 1754 | |
Ian Abbott | 21c5fd9 | 2012-10-30 17:25:53 +0000 | [diff] [blame] | 1755 | /* |
| 1756 | * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the |
| 1757 | * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) |
| 1758 | * being read correctly if bit 7 of the base address is set. |
| 1759 | * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). |
| 1760 | * Re-allocate the regions to a 256-byte boundary if necessary. |
| 1761 | */ |
Linus Torvalds | 193c0d6 | 2012-12-13 12:14:47 -0800 | [diff] [blame] | 1762 | static void quirk_plx_pci9050(struct pci_dev *dev) |
Ian Abbott | 21c5fd9 | 2012-10-30 17:25:53 +0000 | [diff] [blame] | 1763 | { |
| 1764 | unsigned int bar; |
| 1765 | |
| 1766 | /* Fixed in revision 2 (PCI 9052). */ |
| 1767 | if (dev->revision >= 2) |
| 1768 | return; |
| 1769 | for (bar = 0; bar <= 1; bar++) |
| 1770 | if (pci_resource_len(dev, bar) == 0x80 && |
| 1771 | (pci_resource_start(dev, bar) & 0x80)) { |
| 1772 | struct resource *r = &dev->resource[bar]; |
| 1773 | dev_info(&dev->dev, |
| 1774 | "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", |
| 1775 | bar); |
| 1776 | r->start = 0; |
| 1777 | r->end = 0xff; |
| 1778 | } |
| 1779 | } |
| 1780 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
| 1781 | quirk_plx_pci9050); |
Ian Abbott | 2794bb2 | 2012-10-29 14:40:18 +0000 | [diff] [blame] | 1782 | /* |
| 1783 | * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) |
| 1784 | * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, |
| 1785 | * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, |
| 1786 | * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. |
| 1787 | * |
| 1788 | * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" |
| 1789 | * driver. |
| 1790 | */ |
| 1791 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); |
| 1792 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); |
Ian Abbott | 21c5fd9 | 2012-10-30 17:25:53 +0000 | [diff] [blame] | 1793 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1794 | static void quirk_netmos(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1795 | { |
| 1796 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; |
| 1797 | unsigned int num_serial = dev->subsystem_device & 0xf; |
| 1798 | |
| 1799 | /* |
| 1800 | * These Netmos parts are multiport serial devices with optional |
| 1801 | * parallel ports. Even when parallel ports are present, they |
| 1802 | * are identified as class SERIAL, which means the serial driver |
| 1803 | * will claim them. To prevent this, mark them as class OTHER. |
| 1804 | * These combo devices should be claimed by parport_serial. |
| 1805 | * |
| 1806 | * The subdevice ID is of the form 0x00PS, where <P> is the number |
| 1807 | * of parallel ports and <S> is the number of serial ports. |
| 1808 | */ |
| 1809 | switch (dev->device) { |
Jiri Slaby | 4c9c168 | 2008-12-08 16:19:14 +0100 | [diff] [blame] | 1810 | case PCI_DEVICE_ID_NETMOS_9835: |
| 1811 | /* Well, this rule doesn't hold for the following 9835 device */ |
| 1812 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && |
| 1813 | dev->subsystem_device == 0x0299) |
| 1814 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1815 | case PCI_DEVICE_ID_NETMOS_9735: |
| 1816 | case PCI_DEVICE_ID_NETMOS_9745: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1817 | case PCI_DEVICE_ID_NETMOS_9845: |
| 1818 | case PCI_DEVICE_ID_NETMOS_9855: |
Yinghai Lu | 08803ef | 2012-02-23 23:46:56 -0800 | [diff] [blame] | 1819 | if (num_parallel) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1820 | dev_info(&dev->dev, "Netmos %04x (%u parallel, " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1821 | "%u serial); changing class SERIAL to OTHER " |
| 1822 | "(use parport_serial)\n", |
| 1823 | dev->device, num_parallel, num_serial); |
| 1824 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | |
| 1825 | (dev->class & 0xff); |
| 1826 | } |
| 1827 | } |
| 1828 | } |
Yinghai Lu | 08803ef | 2012-02-23 23:46:56 -0800 | [diff] [blame] | 1829 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, |
| 1830 | PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1831 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1832 | static void quirk_e100_interrupt(struct pci_dev *dev) |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1833 | { |
Ivan Kokshaysky | e64aecc | 2007-12-18 00:39:27 +0300 | [diff] [blame] | 1834 | u16 command, pmcsr; |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1835 | u8 __iomem *csr; |
| 1836 | u8 cmd_hi; |
| 1837 | |
| 1838 | switch (dev->device) { |
| 1839 | /* PCI IDs taken from drivers/net/e100.c */ |
| 1840 | case 0x1029: |
| 1841 | case 0x1030 ... 0x1034: |
| 1842 | case 0x1038 ... 0x103E: |
| 1843 | case 0x1050 ... 0x1057: |
| 1844 | case 0x1059: |
| 1845 | case 0x1064 ... 0x106B: |
| 1846 | case 0x1091 ... 0x1095: |
| 1847 | case 0x1209: |
| 1848 | case 0x1229: |
| 1849 | case 0x2449: |
| 1850 | case 0x2459: |
| 1851 | case 0x245D: |
| 1852 | case 0x27DC: |
| 1853 | break; |
| 1854 | default: |
| 1855 | return; |
| 1856 | } |
| 1857 | |
| 1858 | /* |
| 1859 | * Some firmware hands off the e100 with interrupts enabled, |
| 1860 | * which can cause a flood of interrupts if packets are |
| 1861 | * received before the driver attaches to the device. So |
| 1862 | * disable all e100 interrupts here. The driver will |
| 1863 | * re-enable them when it's ready. |
| 1864 | */ |
| 1865 | pci_read_config_word(dev, PCI_COMMAND, &command); |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1866 | |
Benjamin Herrenschmidt | 1bef7dc | 2007-09-29 09:06:21 +1000 | [diff] [blame] | 1867 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1868 | return; |
| 1869 | |
Ivan Kokshaysky | e64aecc | 2007-12-18 00:39:27 +0300 | [diff] [blame] | 1870 | /* |
| 1871 | * Check that the device is in the D0 power state. If it's not, |
| 1872 | * there is no point to look any further. |
| 1873 | */ |
Yijing Wang | 728cdb7 | 2013-06-18 16:22:14 +0800 | [diff] [blame] | 1874 | if (dev->pm_cap) { |
| 1875 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
Ivan Kokshaysky | e64aecc | 2007-12-18 00:39:27 +0300 | [diff] [blame] | 1876 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) |
| 1877 | return; |
| 1878 | } |
| 1879 | |
Benjamin Herrenschmidt | 1bef7dc | 2007-09-29 09:06:21 +1000 | [diff] [blame] | 1880 | /* Convert from PCI bus to resource space. */ |
| 1881 | csr = ioremap(pci_resource_start(dev, 0), 8); |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1882 | if (!csr) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1883 | dev_warn(&dev->dev, "Can't map e100 registers\n"); |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1884 | return; |
| 1885 | } |
| 1886 | |
| 1887 | cmd_hi = readb(csr + 3); |
| 1888 | if (cmd_hi == 0) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1889 | dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " |
| 1890 | "disabling\n"); |
Bjorn Helgaas | 16a7474 | 2006-04-05 08:47:00 -0400 | [diff] [blame] | 1891 | writeb(1, csr + 3); |
| 1892 | } |
| 1893 | |
| 1894 | iounmap(csr); |
| 1895 | } |
Yinghai Lu | 4c5b28e | 2012-02-23 23:46:57 -0800 | [diff] [blame] | 1896 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
| 1897 | PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); |
Ivan Kokshaysky | a5312e2 | 2005-11-01 01:43:56 +0300 | [diff] [blame] | 1898 | |
Alexander Duyck | 649426e | 2009-03-05 13:57:28 -0500 | [diff] [blame] | 1899 | /* |
| 1900 | * The 82575 and 82598 may experience data corruption issues when transitioning |
| 1901 | * out of L0S. To prevent this we need to disable L0S on the pci-e link |
| 1902 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1903 | static void quirk_disable_aspm_l0s(struct pci_dev *dev) |
Alexander Duyck | 649426e | 2009-03-05 13:57:28 -0500 | [diff] [blame] | 1904 | { |
| 1905 | dev_info(&dev->dev, "Disabling L0s\n"); |
| 1906 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); |
| 1907 | } |
| 1908 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); |
| 1909 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); |
| 1910 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); |
| 1911 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); |
| 1912 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); |
| 1913 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); |
| 1914 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); |
| 1915 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); |
| 1916 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); |
| 1917 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); |
| 1918 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); |
| 1919 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); |
| 1920 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); |
| 1921 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); |
| 1922 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1923 | static void fixup_rev1_53c810(struct pci_dev *dev) |
Ivan Kokshaysky | a5312e2 | 2005-11-01 01:43:56 +0300 | [diff] [blame] | 1924 | { |
| 1925 | /* rev 1 ncr53c810 chips don't set the class at all which means |
| 1926 | * they don't get their resources remapped. Fix that here. |
| 1927 | */ |
| 1928 | |
| 1929 | if (dev->class == PCI_CLASS_NOT_DEFINED) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1930 | dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); |
Ivan Kokshaysky | a5312e2 | 2005-11-01 01:43:56 +0300 | [diff] [blame] | 1931 | dev->class = PCI_CLASS_STORAGE_SCSI; |
| 1932 | } |
| 1933 | } |
| 1934 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); |
| 1935 | |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1936 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1937 | static void quirk_p64h2_1k_io(struct pci_dev *dev) |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1938 | { |
| 1939 | u16 en1k; |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1940 | |
| 1941 | pci_read_config_word(dev, 0x40, &en1k); |
| 1942 | |
| 1943 | if (en1k & 0x200) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1944 | dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); |
Bjorn Helgaas | 2b28ae1 | 2012-07-09 13:38:57 -0600 | [diff] [blame] | 1945 | dev->io_window_1k = 1; |
Daniel Yeisley | 9d26512 | 2005-12-05 07:06:43 -0500 | [diff] [blame] | 1946 | } |
| 1947 | } |
| 1948 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
| 1949 | |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1950 | /* Under some circumstances, AER is not linked with extended capabilities. |
| 1951 | * Force it to be linked by setting the corresponding control bit in the |
| 1952 | * config space. |
| 1953 | */ |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1954 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1955 | { |
| 1956 | uint8_t b; |
| 1957 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { |
| 1958 | if (!(b & 0x20)) { |
| 1959 | pci_write_config_byte(dev, 0xf41, b | 0x20); |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 1960 | dev_info(&dev->dev, |
| 1961 | "Linking AER extended capability\n"); |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1962 | } |
| 1963 | } |
| 1964 | } |
| 1965 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 1966 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
Rafael J. Wysocki | e1a2a51 | 2008-05-15 21:51:31 +0200 | [diff] [blame] | 1967 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
Alan Cox | 1597cac | 2006-12-04 15:14:45 -0800 | [diff] [blame] | 1968 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
Brice Goglin | cf34a8e | 2006-06-13 14:35:42 -0400 | [diff] [blame] | 1969 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 1970 | static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 1971 | { |
| 1972 | /* |
| 1973 | * Disable PCI Bus Parking and PCI Master read caching on CX700 |
| 1974 | * which causes unspecified timing errors with a VT6212L on the PCI |
Tim Yamin | ca84639 | 2010-03-19 14:22:58 -0700 | [diff] [blame] | 1975 | * bus leading to USB2.0 packet loss. |
| 1976 | * |
| 1977 | * This quirk is only enabled if a second (on the external PCI bus) |
| 1978 | * VT6212L is found -- the CX700 core itself also contains a USB |
| 1979 | * host controller with the same PCI ID as the VT6212L. |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 1980 | */ |
| 1981 | |
Tim Yamin | ca84639 | 2010-03-19 14:22:58 -0700 | [diff] [blame] | 1982 | /* Count VT6212L instances */ |
| 1983 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, |
| 1984 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 1985 | uint8_t b; |
Tim Yamin | ca84639 | 2010-03-19 14:22:58 -0700 | [diff] [blame] | 1986 | |
| 1987 | /* p should contain the first (internal) VT6212L -- see if we have |
| 1988 | an external one by searching again */ |
| 1989 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); |
| 1990 | if (!p) |
| 1991 | return; |
| 1992 | pci_dev_put(p); |
| 1993 | |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 1994 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { |
| 1995 | if (b & 0x40) { |
| 1996 | /* Turn off PCI Bus Parking */ |
| 1997 | pci_write_config_byte(dev, 0x76, b ^ 0x40); |
| 1998 | |
Tim Yamin | bc04327 | 2008-03-30 20:58:59 +0100 | [diff] [blame] | 1999 | dev_info(&dev->dev, |
| 2000 | "Disabling VIA CX700 PCI parking\n"); |
| 2001 | } |
| 2002 | } |
| 2003 | |
| 2004 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { |
| 2005 | if (b != 0) { |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 2006 | /* Turn off PCI Master read caching */ |
| 2007 | pci_write_config_byte(dev, 0x72, 0x0); |
Tim Yamin | bc04327 | 2008-03-30 20:58:59 +0100 | [diff] [blame] | 2008 | |
| 2009 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 2010 | pci_write_config_byte(dev, 0x75, 0x1); |
Tim Yamin | bc04327 | 2008-03-30 20:58:59 +0100 | [diff] [blame] | 2011 | |
| 2012 | /* Disable "Read FIFO Timer" */ |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 2013 | pci_write_config_byte(dev, 0x77, 0x0); |
| 2014 | |
Bjorn Helgaas | d6505a5 | 2008-02-29 16:12:18 -0700 | [diff] [blame] | 2015 | dev_info(&dev->dev, |
Tim Yamin | bc04327 | 2008-03-30 20:58:59 +0100 | [diff] [blame] | 2016 | "Disabling VIA CX700 PCI caching\n"); |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 2017 | } |
| 2018 | } |
| 2019 | } |
Tim Yamin | ca84639 | 2010-03-19 14:22:58 -0700 | [diff] [blame] | 2020 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
Tim Yamin | 53a9bf4 | 2007-11-01 23:14:54 +0000 | [diff] [blame] | 2021 | |
Benjamin Li | 99cb233d | 2008-07-02 10:59:04 -0700 | [diff] [blame] | 2022 | /* |
| 2023 | * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the |
| 2024 | * VPD end tag will hang the device. This problem was initially |
| 2025 | * observed when a vpd entry was created in sysfs |
| 2026 | * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry |
| 2027 | * will dump 32k of data. Reading a full 32k will cause an access |
| 2028 | * beyond the VPD end tag causing the device to hang. Once the device |
| 2029 | * is hung, the bnx2 driver will not be able to reset the device. |
| 2030 | * We believe that it is legal to read beyond the end tag and |
| 2031 | * therefore the solution is to limit the read/write length. |
| 2032 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2033 | static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) |
Benjamin Li | 99cb233d | 2008-07-02 10:59:04 -0700 | [diff] [blame] | 2034 | { |
Eric Dumazet | 9d82d8e | 2008-07-31 20:27:31 +0200 | [diff] [blame] | 2035 | /* |
Dean Hildebrand | 35405f2 | 2008-08-07 17:31:45 -0700 | [diff] [blame] | 2036 | * Only disable the VPD capability for 5706, 5706S, 5708, |
| 2037 | * 5708S and 5709 rev. A |
Eric Dumazet | 9d82d8e | 2008-07-31 20:27:31 +0200 | [diff] [blame] | 2038 | */ |
Benjamin Li | 99cb233d | 2008-07-02 10:59:04 -0700 | [diff] [blame] | 2039 | if ((dev->device == PCI_DEVICE_ID_NX2_5706) || |
Dean Hildebrand | 35405f2 | 2008-08-07 17:31:45 -0700 | [diff] [blame] | 2040 | (dev->device == PCI_DEVICE_ID_NX2_5706S) || |
Benjamin Li | 99cb233d | 2008-07-02 10:59:04 -0700 | [diff] [blame] | 2041 | (dev->device == PCI_DEVICE_ID_NX2_5708) || |
Eric Dumazet | 9d82d8e | 2008-07-31 20:27:31 +0200 | [diff] [blame] | 2042 | (dev->device == PCI_DEVICE_ID_NX2_5708S) || |
Benjamin Li | 99cb233d | 2008-07-02 10:59:04 -0700 | [diff] [blame] | 2043 | ((dev->device == PCI_DEVICE_ID_NX2_5709) && |
| 2044 | (dev->revision & 0xf0) == 0x0)) { |
| 2045 | if (dev->vpd) |
| 2046 | dev->vpd->len = 0x80; |
| 2047 | } |
| 2048 | } |
| 2049 | |
Yu Zhao | bffadff | 2008-10-28 14:44:11 +0800 | [diff] [blame] | 2050 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2051 | PCI_DEVICE_ID_NX2_5706, |
| 2052 | quirk_brcm_570x_limit_vpd); |
| 2053 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2054 | PCI_DEVICE_ID_NX2_5706S, |
| 2055 | quirk_brcm_570x_limit_vpd); |
| 2056 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2057 | PCI_DEVICE_ID_NX2_5708, |
| 2058 | quirk_brcm_570x_limit_vpd); |
| 2059 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2060 | PCI_DEVICE_ID_NX2_5708S, |
| 2061 | quirk_brcm_570x_limit_vpd); |
| 2062 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2063 | PCI_DEVICE_ID_NX2_5709, |
| 2064 | quirk_brcm_570x_limit_vpd); |
| 2065 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2066 | PCI_DEVICE_ID_NX2_5709S, |
| 2067 | quirk_brcm_570x_limit_vpd); |
Benjamin Li | 99cb233d | 2008-07-02 10:59:04 -0700 | [diff] [blame] | 2068 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2069 | static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) |
Matt Carlson | 0b47150 | 2012-02-27 09:44:48 +0000 | [diff] [blame] | 2070 | { |
| 2071 | u32 rev; |
| 2072 | |
| 2073 | pci_read_config_dword(dev, 0xf4, &rev); |
| 2074 | |
| 2075 | /* Only CAP the MRRS if the device is a 5719 A0 */ |
| 2076 | if (rev == 0x05719000) { |
| 2077 | int readrq = pcie_get_readrq(dev); |
| 2078 | if (readrq > 2048) |
| 2079 | pcie_set_readrq(dev, 2048); |
| 2080 | } |
| 2081 | } |
| 2082 | |
| 2083 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, |
| 2084 | PCI_DEVICE_ID_TIGON3_5719, |
| 2085 | quirk_brcm_5719_limit_mrrs); |
| 2086 | |
Michal Miroslaw | 26c56dc | 2009-05-12 13:49:26 -0700 | [diff] [blame] | 2087 | /* Originally in EDAC sources for i82875P: |
| 2088 | * Intel tells BIOS developers to hide device 6 which |
| 2089 | * configures the overflow device access containing |
| 2090 | * the DRBs - this is where we expose device 6. |
| 2091 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm |
| 2092 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2093 | static void quirk_unhide_mch_dev6(struct pci_dev *dev) |
Michal Miroslaw | 26c56dc | 2009-05-12 13:49:26 -0700 | [diff] [blame] | 2094 | { |
| 2095 | u8 reg; |
| 2096 | |
| 2097 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { |
| 2098 | dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); |
| 2099 | pci_write_config_byte(dev, 0xF4, reg | 0x02); |
| 2100 | } |
| 2101 | } |
| 2102 | |
| 2103 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, |
| 2104 | quirk_unhide_mch_dev6); |
| 2105 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, |
| 2106 | quirk_unhide_mch_dev6); |
| 2107 | |
Chris Metcalf | 1296226 | 2012-04-07 17:10:17 -0400 | [diff] [blame] | 2108 | #ifdef CONFIG_TILEPRO |
Chris Metcalf | f02cbbe | 2010-11-02 12:05:10 -0400 | [diff] [blame] | 2109 | /* |
Chris Metcalf | 1296226 | 2012-04-07 17:10:17 -0400 | [diff] [blame] | 2110 | * The Tilera TILEmpower tilepro platform needs to set the link speed |
Chris Metcalf | f02cbbe | 2010-11-02 12:05:10 -0400 | [diff] [blame] | 2111 | * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed |
| 2112 | * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe |
| 2113 | * capability register of the PEX8624 PCIe switch. The switch |
| 2114 | * supports link speed auto negotiation, but falsely sets |
| 2115 | * the link speed to 5GT/s. |
| 2116 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2117 | static void quirk_tile_plx_gen1(struct pci_dev *dev) |
Chris Metcalf | f02cbbe | 2010-11-02 12:05:10 -0400 | [diff] [blame] | 2118 | { |
| 2119 | if (tile_plx_gen1) { |
| 2120 | pci_write_config_dword(dev, 0x98, 0x1); |
| 2121 | mdelay(50); |
| 2122 | } |
| 2123 | } |
| 2124 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); |
Chris Metcalf | 1296226 | 2012-04-07 17:10:17 -0400 | [diff] [blame] | 2125 | #endif /* CONFIG_TILEPRO */ |
Michal Miroslaw | 26c56dc | 2009-05-12 13:49:26 -0700 | [diff] [blame] | 2126 | |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2127 | #ifdef CONFIG_PCI_MSI |
Tejun Heo | ebdf7d3 | 2007-05-31 00:40:48 -0700 | [diff] [blame] | 2128 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
| 2129 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually |
| 2130 | * some other busses controlled by the chipset even if Linux is not |
| 2131 | * aware of it. Instead of setting the flag on all busses in the |
| 2132 | * machine, simply disable MSI globally. |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2133 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2134 | static void quirk_disable_all_msi(struct pci_dev *dev) |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2135 | { |
Michael Ellerman | 88187df | 2007-01-25 19:34:07 +1100 | [diff] [blame] | 2136 | pci_no_msi(); |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 2137 | dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2138 | } |
Tejun Heo | ebdf7d3 | 2007-05-31 00:40:48 -0700 | [diff] [blame] | 2139 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
| 2140 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); |
| 2141 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); |
Tejun Heo | 66d715c | 2008-07-04 09:59:32 -0700 | [diff] [blame] | 2142 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
Jay Cliburn | 184b812 | 2007-05-26 17:01:04 -0500 | [diff] [blame] | 2143 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
Thomas Renninger | 162dedd | 2009-04-03 06:34:00 -0700 | [diff] [blame] | 2144 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
Tejun Heo | 549e156 | 2010-05-23 10:22:55 +0200 | [diff] [blame] | 2145 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2146 | |
| 2147 | /* Disable MSI on chipsets that are known to not support it */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2148 | static void quirk_disable_msi(struct pci_dev *dev) |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2149 | { |
| 2150 | if (dev->subordinate) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 2151 | dev_warn(&dev->dev, "MSI quirk detected; " |
| 2152 | "subordinate MSI disabled\n"); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2153 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 2154 | } |
| 2155 | } |
| 2156 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); |
Matthew Wilcox | 134b345 | 2010-03-24 07:11:01 -0600 | [diff] [blame] | 2157 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
Alex Deucher | 9313ff4 | 2010-05-18 10:42:53 -0400 | [diff] [blame] | 2158 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2159 | |
Clemens Ladisch | aff6136 | 2010-05-26 12:21:10 +0200 | [diff] [blame] | 2160 | /* |
| 2161 | * The APC bridge device in AMD 780 family northbridges has some random |
| 2162 | * OEM subsystem ID in its vendor ID register (erratum 18), so instead |
| 2163 | * we use the possible vendor/device IDs of the host bridge for the |
| 2164 | * declared quirk, and search for the APC bridge by slot number. |
| 2165 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2166 | static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) |
Clemens Ladisch | aff6136 | 2010-05-26 12:21:10 +0200 | [diff] [blame] | 2167 | { |
| 2168 | struct pci_dev *apc_bridge; |
| 2169 | |
| 2170 | apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); |
| 2171 | if (apc_bridge) { |
| 2172 | if (apc_bridge->device == 0x9602) |
| 2173 | quirk_disable_msi(apc_bridge); |
| 2174 | pci_dev_put(apc_bridge); |
| 2175 | } |
| 2176 | } |
| 2177 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); |
| 2178 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); |
| 2179 | |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2180 | /* Go through the list of Hypertransport capabilities and |
| 2181 | * return 1 if a HT MSI capability is found and enabled */ |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2182 | static int msi_ht_cap_enabled(struct pci_dev *dev) |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2183 | { |
Michael Ellerman | 7a38050 | 2006-11-22 18:26:21 +1100 | [diff] [blame] | 2184 | int pos, ttl = 48; |
| 2185 | |
| 2186 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
| 2187 | while (pos && ttl--) { |
| 2188 | u8 flags; |
| 2189 | |
| 2190 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2191 | &flags) == 0) |
| 2192 | { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 2193 | dev_info(&dev->dev, "Found %s HT MSI Mapping\n", |
Michael Ellerman | 7a38050 | 2006-11-22 18:26:21 +1100 | [diff] [blame] | 2194 | flags & HT_MSI_FLAGS_ENABLE ? |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 2195 | "enabled" : "disabled"); |
Michael Ellerman | 7a38050 | 2006-11-22 18:26:21 +1100 | [diff] [blame] | 2196 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2197 | } |
Michael Ellerman | 7a38050 | 2006-11-22 18:26:21 +1100 | [diff] [blame] | 2198 | |
| 2199 | pos = pci_find_next_ht_capability(dev, pos, |
| 2200 | HT_CAPTYPE_MSI_MAPPING); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2201 | } |
| 2202 | return 0; |
| 2203 | } |
| 2204 | |
| 2205 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2206 | static void quirk_msi_ht_cap(struct pci_dev *dev) |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2207 | { |
| 2208 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 2209 | dev_warn(&dev->dev, "MSI quirk detected; " |
| 2210 | "subordinate MSI disabled\n"); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2211 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 2212 | } |
| 2213 | } |
| 2214 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, |
| 2215 | quirk_msi_ht_cap); |
Sebastien Dugue | 6bae1d9 | 2007-12-13 16:09:25 -0800 | [diff] [blame] | 2216 | |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2217 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
| 2218 | * MSI are supported if the MSI capability set in any of these mappings. |
| 2219 | */ |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2220 | static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2221 | { |
| 2222 | struct pci_dev *pdev; |
| 2223 | |
| 2224 | if (!dev->subordinate) |
| 2225 | return; |
| 2226 | |
| 2227 | /* check HT MSI cap on this chipset and the root one. |
| 2228 | * a single one having MSI is enough to be sure that MSI are supported. |
| 2229 | */ |
Alan Cox | 11f242f | 2006-10-10 14:39:00 -0700 | [diff] [blame] | 2230 | pdev = pci_get_slot(dev->bus, 0); |
Jesper Juhl | 9ac0ce8 | 2006-12-04 15:14:48 -0800 | [diff] [blame] | 2231 | if (!pdev) |
| 2232 | return; |
David Rientjes | 0c875c2 | 2006-12-03 11:55:34 -0800 | [diff] [blame] | 2233 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
bjorn.helgaas@hp.com | f0fda80 | 2007-12-17 14:09:39 -0700 | [diff] [blame] | 2234 | dev_warn(&dev->dev, "MSI quirk detected; " |
| 2235 | "subordinate MSI disabled\n"); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2236 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
| 2237 | } |
Alan Cox | 11f242f | 2006-10-10 14:39:00 -0700 | [diff] [blame] | 2238 | pci_dev_put(pdev); |
Brice Goglin | 6397c75 | 2006-08-31 01:55:32 -0400 | [diff] [blame] | 2239 | } |
| 2240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
| 2241 | quirk_nvidia_ck804_msi_ht_cap); |
David Miller | ba698ad | 2007-10-25 01:16:30 -0700 | [diff] [blame] | 2242 | |
Bjorn Helgaas | 415b6d0 | 2008-02-29 16:04:39 -0700 | [diff] [blame] | 2243 | /* Force enable MSI mapping capability on HT bridges */ |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2244 | static void ht_enable_msi_mapping(struct pci_dev *dev) |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2245 | { |
| 2246 | int pos, ttl = 48; |
| 2247 | |
| 2248 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
| 2249 | while (pos && ttl--) { |
| 2250 | u8 flags; |
| 2251 | |
| 2252 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2253 | &flags) == 0) { |
| 2254 | dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); |
| 2255 | |
| 2256 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2257 | flags | HT_MSI_FLAGS_ENABLE); |
| 2258 | } |
| 2259 | pos = pci_find_next_ht_capability(dev, pos, |
| 2260 | HT_CAPTYPE_MSI_MAPPING); |
| 2261 | } |
| 2262 | } |
Bjorn Helgaas | 415b6d0 | 2008-02-29 16:04:39 -0700 | [diff] [blame] | 2263 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
| 2264 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, |
| 2265 | ht_enable_msi_mapping); |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2266 | |
Yinghai Lu | e0ae4f5 | 2009-02-17 20:40:09 -0800 | [diff] [blame] | 2267 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
| 2268 | ht_enable_msi_mapping); |
| 2269 | |
Ben Hutchings | e4146bb | 2010-05-16 02:28:49 +0100 | [diff] [blame] | 2270 | /* The P5N32-SLI motherboards from Asus have a problem with msi |
Andreas Petlund | 75e07fc | 2008-11-20 20:42:25 -0800 | [diff] [blame] | 2271 | * for the MCP55 NIC. It is not yet determined whether the msi problem |
| 2272 | * also affects other devices. As for now, turn off msi for this device. |
| 2273 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2274 | static void nvenet_msi_disable(struct pci_dev *dev) |
Andreas Petlund | 75e07fc | 2008-11-20 20:42:25 -0800 | [diff] [blame] | 2275 | { |
Jean Delvare | 9251bac | 2011-05-15 18:13:46 +0200 | [diff] [blame] | 2276 | const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); |
| 2277 | |
| 2278 | if (board_name && |
| 2279 | (strstr(board_name, "P5N32-SLI PREMIUM") || |
| 2280 | strstr(board_name, "P5N32-E SLI"))) { |
Andreas Petlund | 75e07fc | 2008-11-20 20:42:25 -0800 | [diff] [blame] | 2281 | dev_info(&dev->dev, |
Ben Hutchings | e4146bb | 2010-05-16 02:28:49 +0100 | [diff] [blame] | 2282 | "Disabling msi for MCP55 NIC on P5N32-SLI\n"); |
Andreas Petlund | 75e07fc | 2008-11-20 20:42:25 -0800 | [diff] [blame] | 2283 | dev->no_msi = 1; |
| 2284 | } |
| 2285 | } |
| 2286 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
| 2287 | PCI_DEVICE_ID_NVIDIA_NVENET_15, |
| 2288 | nvenet_msi_disable); |
| 2289 | |
Neil Horman | 66db60e | 2010-09-21 13:54:39 -0400 | [diff] [blame] | 2290 | /* |
| 2291 | * Some versions of the MCP55 bridge from nvidia have a legacy irq routing |
| 2292 | * config register. This register controls the routing of legacy interrupts |
| 2293 | * from devices that route through the MCP55. If this register is misprogramed |
| 2294 | * interrupts are only sent to the bsp, unlike conventional systems where the |
| 2295 | * irq is broadxast to all online cpus. Not having this register set |
| 2296 | * properly prevents kdump from booting up properly, so lets make sure that |
| 2297 | * we have it set correctly. |
| 2298 | * Note this is an undocumented register. |
| 2299 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2300 | static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) |
Neil Horman | 66db60e | 2010-09-21 13:54:39 -0400 | [diff] [blame] | 2301 | { |
| 2302 | u32 cfg; |
| 2303 | |
Neil Horman | 49c2fa08 | 2010-12-08 09:47:48 -0500 | [diff] [blame] | 2304 | if (!pci_find_capability(dev, PCI_CAP_ID_HT)) |
| 2305 | return; |
| 2306 | |
Neil Horman | 66db60e | 2010-09-21 13:54:39 -0400 | [diff] [blame] | 2307 | pci_read_config_dword(dev, 0x74, &cfg); |
| 2308 | |
| 2309 | if (cfg & ((1 << 2) | (1 << 15))) { |
| 2310 | printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); |
| 2311 | cfg &= ~((1 << 2) | (1 << 15)); |
| 2312 | pci_write_config_dword(dev, 0x74, cfg); |
| 2313 | } |
| 2314 | } |
| 2315 | |
| 2316 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
| 2317 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, |
| 2318 | nvbridge_check_legacy_irq_routing); |
| 2319 | |
| 2320 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
| 2321 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, |
| 2322 | nvbridge_check_legacy_irq_routing); |
| 2323 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2324 | static int ht_check_msi_mapping(struct pci_dev *dev) |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2325 | { |
| 2326 | int pos, ttl = 48; |
| 2327 | int found = 0; |
| 2328 | |
| 2329 | /* check if there is HT MSI cap or enabled on this device */ |
| 2330 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
| 2331 | while (pos && ttl--) { |
| 2332 | u8 flags; |
| 2333 | |
| 2334 | if (found < 1) |
| 2335 | found = 1; |
| 2336 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2337 | &flags) == 0) { |
| 2338 | if (flags & HT_MSI_FLAGS_ENABLE) { |
| 2339 | if (found < 2) { |
| 2340 | found = 2; |
| 2341 | break; |
| 2342 | } |
| 2343 | } |
| 2344 | } |
| 2345 | pos = pci_find_next_ht_capability(dev, pos, |
| 2346 | HT_CAPTYPE_MSI_MAPPING); |
| 2347 | } |
| 2348 | |
| 2349 | return found; |
| 2350 | } |
| 2351 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2352 | static int host_bridge_with_leaf(struct pci_dev *host_bridge) |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2353 | { |
| 2354 | struct pci_dev *dev; |
| 2355 | int pos; |
| 2356 | int i, dev_no; |
| 2357 | int found = 0; |
| 2358 | |
| 2359 | dev_no = host_bridge->devfn >> 3; |
| 2360 | for (i = dev_no + 1; i < 0x20; i++) { |
| 2361 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); |
| 2362 | if (!dev) |
| 2363 | continue; |
| 2364 | |
| 2365 | /* found next host bridge ?*/ |
| 2366 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); |
| 2367 | if (pos != 0) { |
| 2368 | pci_dev_put(dev); |
| 2369 | break; |
| 2370 | } |
| 2371 | |
| 2372 | if (ht_check_msi_mapping(dev)) { |
| 2373 | found = 1; |
| 2374 | pci_dev_put(dev); |
| 2375 | break; |
| 2376 | } |
| 2377 | pci_dev_put(dev); |
| 2378 | } |
| 2379 | |
| 2380 | return found; |
| 2381 | } |
| 2382 | |
Yinghai Lu | eeafda7 | 2009-03-29 12:30:05 -0700 | [diff] [blame] | 2383 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
| 2384 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ |
| 2385 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2386 | static int is_end_of_ht_chain(struct pci_dev *dev) |
Yinghai Lu | eeafda7 | 2009-03-29 12:30:05 -0700 | [diff] [blame] | 2387 | { |
| 2388 | int pos, ctrl_off; |
| 2389 | int end = 0; |
| 2390 | u16 flags, ctrl; |
| 2391 | |
| 2392 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); |
| 2393 | |
| 2394 | if (!pos) |
| 2395 | goto out; |
| 2396 | |
| 2397 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); |
| 2398 | |
| 2399 | ctrl_off = ((flags >> 10) & 1) ? |
| 2400 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; |
| 2401 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); |
| 2402 | |
| 2403 | if (ctrl & (1 << 6)) |
| 2404 | end = 1; |
| 2405 | |
| 2406 | out: |
| 2407 | return end; |
| 2408 | } |
| 2409 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2410 | static void nv_ht_enable_msi_mapping(struct pci_dev *dev) |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2411 | { |
| 2412 | struct pci_dev *host_bridge; |
| 2413 | int pos; |
| 2414 | int i, dev_no; |
| 2415 | int found = 0; |
| 2416 | |
| 2417 | dev_no = dev->devfn >> 3; |
| 2418 | for (i = dev_no; i >= 0; i--) { |
| 2419 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); |
| 2420 | if (!host_bridge) |
| 2421 | continue; |
| 2422 | |
| 2423 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); |
| 2424 | if (pos != 0) { |
| 2425 | found = 1; |
| 2426 | break; |
| 2427 | } |
| 2428 | pci_dev_put(host_bridge); |
| 2429 | } |
| 2430 | |
| 2431 | if (!found) |
| 2432 | return; |
| 2433 | |
Yinghai Lu | eeafda7 | 2009-03-29 12:30:05 -0700 | [diff] [blame] | 2434 | /* don't enable end_device/host_bridge with leaf directly here */ |
| 2435 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && |
| 2436 | host_bridge_with_leaf(host_bridge)) |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2437 | goto out; |
| 2438 | |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2439 | /* root did that ! */ |
| 2440 | if (msi_ht_cap_enabled(host_bridge)) |
| 2441 | goto out; |
| 2442 | |
| 2443 | ht_enable_msi_mapping(dev); |
| 2444 | |
| 2445 | out: |
| 2446 | pci_dev_put(host_bridge); |
| 2447 | } |
| 2448 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2449 | static void ht_disable_msi_mapping(struct pci_dev *dev) |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2450 | { |
| 2451 | int pos, ttl = 48; |
| 2452 | |
| 2453 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
| 2454 | while (pos && ttl--) { |
| 2455 | u8 flags; |
| 2456 | |
| 2457 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2458 | &flags) == 0) { |
Prakash Punnoor | 6a958d5 | 2009-03-06 10:10:35 +0100 | [diff] [blame] | 2459 | dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2460 | |
| 2461 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2462 | flags & ~HT_MSI_FLAGS_ENABLE); |
| 2463 | } |
| 2464 | pos = pci_find_next_ht_capability(dev, pos, |
| 2465 | HT_CAPTYPE_MSI_MAPPING); |
| 2466 | } |
| 2467 | } |
| 2468 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2469 | static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2470 | { |
| 2471 | struct pci_dev *host_bridge; |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2472 | int pos; |
| 2473 | int found; |
| 2474 | |
Rafael J. Wysocki | 3d2a531 | 2010-07-23 22:19:55 +0200 | [diff] [blame] | 2475 | if (!pci_msi_enabled()) |
| 2476 | return; |
| 2477 | |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2478 | /* check if there is HT MSI cap or enabled on this device */ |
| 2479 | found = ht_check_msi_mapping(dev); |
| 2480 | |
| 2481 | /* no HT MSI CAP */ |
| 2482 | if (found == 0) |
| 2483 | return; |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2484 | |
| 2485 | /* |
| 2486 | * HT MSI mapping should be disabled on devices that are below |
| 2487 | * a non-Hypertransport host bridge. Locate the host bridge... |
| 2488 | */ |
| 2489 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); |
| 2490 | if (host_bridge == NULL) { |
| 2491 | dev_warn(&dev->dev, |
| 2492 | "nv_msi_ht_cap_quirk didn't locate host bridge\n"); |
| 2493 | return; |
| 2494 | } |
| 2495 | |
| 2496 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); |
| 2497 | if (pos != 0) { |
| 2498 | /* Host bridge is to HT */ |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2499 | if (found == 1) { |
| 2500 | /* it is not enabled, try to enable it */ |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2501 | if (all) |
| 2502 | ht_enable_msi_mapping(dev); |
| 2503 | else |
| 2504 | nv_ht_enable_msi_mapping(dev); |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2505 | } |
Myron Stowe | dff3aef | 2012-07-09 15:36:08 -0600 | [diff] [blame] | 2506 | goto out; |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2507 | } |
| 2508 | |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2509 | /* HT MSI is not enabled */ |
| 2510 | if (found == 1) |
Myron Stowe | dff3aef | 2012-07-09 15:36:08 -0600 | [diff] [blame] | 2511 | goto out; |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2512 | |
Yinghai Lu | 1dec6b0 | 2009-02-23 11:51:59 -0800 | [diff] [blame] | 2513 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
| 2514 | ht_disable_msi_mapping(dev); |
Myron Stowe | dff3aef | 2012-07-09 15:36:08 -0600 | [diff] [blame] | 2515 | |
| 2516 | out: |
| 2517 | pci_dev_put(host_bridge); |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2518 | } |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2519 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2520 | static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2521 | { |
| 2522 | return __nv_msi_ht_cap_quirk(dev, 1); |
| 2523 | } |
| 2524 | |
Myron Stowe | 25e742b | 2012-07-09 15:36:14 -0600 | [diff] [blame] | 2525 | static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2526 | { |
| 2527 | return __nv_msi_ht_cap_quirk(dev, 0); |
| 2528 | } |
| 2529 | |
| 2530 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
Tejun Heo | 6dab62e | 2009-07-21 16:08:43 -0700 | [diff] [blame] | 2531 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
Yinghai Lu | de74530 | 2009-03-20 19:29:41 -0700 | [diff] [blame] | 2532 | |
| 2533 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
Tejun Heo | 6dab62e | 2009-07-21 16:08:43 -0700 | [diff] [blame] | 2534 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
Peer Chen | 9dc625e | 2008-02-04 23:50:13 -0800 | [diff] [blame] | 2535 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2536 | static void quirk_msi_intx_disable_bug(struct pci_dev *dev) |
David Miller | ba698ad | 2007-10-25 01:16:30 -0700 | [diff] [blame] | 2537 | { |
| 2538 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
| 2539 | } |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2540 | static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
Shane Huang | 4600c9d | 2008-01-25 15:46:24 +0900 | [diff] [blame] | 2541 | { |
| 2542 | struct pci_dev *p; |
| 2543 | |
| 2544 | /* SB700 MSI issue will be fixed at HW level from revision A21, |
| 2545 | * we need check PCI REVISION ID of SMBus controller to get SB700 |
| 2546 | * revision. |
| 2547 | */ |
| 2548 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
| 2549 | NULL); |
| 2550 | if (!p) |
| 2551 | return; |
| 2552 | |
| 2553 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) |
| 2554 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
| 2555 | pci_dev_put(p); |
| 2556 | } |
Xiong Huang | 7058881 | 2013-03-07 08:55:16 +0000 | [diff] [blame] | 2557 | static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) |
| 2558 | { |
| 2559 | /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ |
| 2560 | if (dev->revision < 0x18) { |
| 2561 | dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); |
| 2562 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
| 2563 | } |
| 2564 | } |
David Miller | ba698ad | 2007-10-25 01:16:30 -0700 | [diff] [blame] | 2565 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2566 | PCI_DEVICE_ID_TIGON3_5780, |
| 2567 | quirk_msi_intx_disable_bug); |
| 2568 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2569 | PCI_DEVICE_ID_TIGON3_5780S, |
| 2570 | quirk_msi_intx_disable_bug); |
| 2571 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2572 | PCI_DEVICE_ID_TIGON3_5714, |
| 2573 | quirk_msi_intx_disable_bug); |
| 2574 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2575 | PCI_DEVICE_ID_TIGON3_5714S, |
| 2576 | quirk_msi_intx_disable_bug); |
| 2577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2578 | PCI_DEVICE_ID_TIGON3_5715, |
| 2579 | quirk_msi_intx_disable_bug); |
| 2580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
| 2581 | PCI_DEVICE_ID_TIGON3_5715S, |
| 2582 | quirk_msi_intx_disable_bug); |
| 2583 | |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 2584 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
Shane Huang | 4600c9d | 2008-01-25 15:46:24 +0900 | [diff] [blame] | 2585 | quirk_msi_intx_disable_ati_bug); |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 2586 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
Shane Huang | 4600c9d | 2008-01-25 15:46:24 +0900 | [diff] [blame] | 2587 | quirk_msi_intx_disable_ati_bug); |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 2588 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
Shane Huang | 4600c9d | 2008-01-25 15:46:24 +0900 | [diff] [blame] | 2589 | quirk_msi_intx_disable_ati_bug); |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 2590 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
Shane Huang | 4600c9d | 2008-01-25 15:46:24 +0900 | [diff] [blame] | 2591 | quirk_msi_intx_disable_ati_bug); |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 2592 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
Shane Huang | 4600c9d | 2008-01-25 15:46:24 +0900 | [diff] [blame] | 2593 | quirk_msi_intx_disable_ati_bug); |
David Miller | bc38b41 | 2007-10-25 01:16:52 -0700 | [diff] [blame] | 2594 | |
| 2595 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, |
| 2596 | quirk_msi_intx_disable_bug); |
| 2597 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, |
| 2598 | quirk_msi_intx_disable_bug); |
| 2599 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, |
| 2600 | quirk_msi_intx_disable_bug); |
| 2601 | |
Huang, Xiong | 7cb6a29 | 2012-04-30 15:38:49 +0000 | [diff] [blame] | 2602 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, |
| 2603 | quirk_msi_intx_disable_bug); |
| 2604 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, |
| 2605 | quirk_msi_intx_disable_bug); |
| 2606 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, |
| 2607 | quirk_msi_intx_disable_bug); |
| 2608 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, |
| 2609 | quirk_msi_intx_disable_bug); |
| 2610 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, |
| 2611 | quirk_msi_intx_disable_bug); |
| 2612 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, |
| 2613 | quirk_msi_intx_disable_bug); |
Xiong Huang | 7058881 | 2013-03-07 08:55:16 +0000 | [diff] [blame] | 2614 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, |
| 2615 | quirk_msi_intx_disable_qca_bug); |
| 2616 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, |
| 2617 | quirk_msi_intx_disable_qca_bug); |
| 2618 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, |
| 2619 | quirk_msi_intx_disable_qca_bug); |
| 2620 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, |
| 2621 | quirk_msi_intx_disable_qca_bug); |
| 2622 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, |
| 2623 | quirk_msi_intx_disable_qca_bug); |
Brice Goglin | 3f79e10 | 2006-08-31 01:54:56 -0400 | [diff] [blame] | 2624 | #endif /* CONFIG_PCI_MSI */ |
Thomas Petazzoni | 3d13731 | 2008-08-19 10:28:24 +0200 | [diff] [blame] | 2625 | |
Felix Radensky | 3322340 | 2010-03-28 16:02:02 +0300 | [diff] [blame] | 2626 | /* Allow manual resource allocation for PCI hotplug bridges |
| 2627 | * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For |
| 2628 | * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), |
| 2629 | * kernel fails to allocate resources when hotplug device is |
| 2630 | * inserted and PCI bus is rescanned. |
| 2631 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2632 | static void quirk_hotplug_bridge(struct pci_dev *dev) |
Felix Radensky | 3322340 | 2010-03-28 16:02:02 +0300 | [diff] [blame] | 2633 | { |
| 2634 | dev->is_hotplug_bridge = 1; |
| 2635 | } |
| 2636 | |
| 2637 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); |
| 2638 | |
Maxim Levitsky | 03cd8f7 | 2010-03-05 13:43:20 -0800 | [diff] [blame] | 2639 | /* |
| 2640 | * This is a quirk for the Ricoh MMC controller found as a part of |
| 2641 | * some mulifunction chips. |
| 2642 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 2643 | * This is very similar and based on the ricoh_mmc driver written by |
Maxim Levitsky | 03cd8f7 | 2010-03-05 13:43:20 -0800 | [diff] [blame] | 2644 | * Philip Langdale. Thank you for these magic sequences. |
| 2645 | * |
| 2646 | * These chips implement the four main memory card controllers (SD, MMC, MS, xD) |
| 2647 | * and one or both of cardbus or firewire. |
| 2648 | * |
| 2649 | * It happens that they implement SD and MMC |
| 2650 | * support as separate controllers (and PCI functions). The linux SDHCI |
| 2651 | * driver supports MMC cards but the chip detects MMC cards in hardware |
| 2652 | * and directs them to the MMC controller - so the SDHCI driver never sees |
| 2653 | * them. |
| 2654 | * |
| 2655 | * To get around this, we must disable the useless MMC controller. |
| 2656 | * At that point, the SDHCI controller will start seeing them |
| 2657 | * It seems to be the case that the relevant PCI registers to deactivate the |
| 2658 | * MMC controller live on PCI function 0, which might be the cardbus controller |
| 2659 | * or the firewire controller, depending on the particular chip in question |
| 2660 | * |
| 2661 | * This has to be done early, because as soon as we disable the MMC controller |
| 2662 | * other pci functions shift up one level, e.g. function #2 becomes function |
| 2663 | * #1, and this will confuse the pci core. |
| 2664 | */ |
| 2665 | |
| 2666 | #ifdef CONFIG_MMC_RICOH_MMC |
| 2667 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) |
| 2668 | { |
| 2669 | /* disable via cardbus interface */ |
| 2670 | u8 write_enable; |
| 2671 | u8 write_target; |
| 2672 | u8 disable; |
| 2673 | |
| 2674 | /* disable must be done via function #0 */ |
| 2675 | if (PCI_FUNC(dev->devfn)) |
| 2676 | return; |
| 2677 | |
| 2678 | pci_read_config_byte(dev, 0xB7, &disable); |
| 2679 | if (disable & 0x02) |
| 2680 | return; |
| 2681 | |
| 2682 | pci_read_config_byte(dev, 0x8E, &write_enable); |
| 2683 | pci_write_config_byte(dev, 0x8E, 0xAA); |
| 2684 | pci_read_config_byte(dev, 0x8D, &write_target); |
| 2685 | pci_write_config_byte(dev, 0x8D, 0xB7); |
| 2686 | pci_write_config_byte(dev, 0xB7, disable | 0x02); |
| 2687 | pci_write_config_byte(dev, 0x8E, write_enable); |
| 2688 | pci_write_config_byte(dev, 0x8D, write_target); |
| 2689 | |
| 2690 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); |
| 2691 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); |
| 2692 | } |
| 2693 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); |
| 2694 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); |
| 2695 | |
| 2696 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) |
| 2697 | { |
| 2698 | /* disable via firewire interface */ |
| 2699 | u8 write_enable; |
| 2700 | u8 disable; |
| 2701 | |
| 2702 | /* disable must be done via function #0 */ |
| 2703 | if (PCI_FUNC(dev->devfn)) |
| 2704 | return; |
Manoj Iyer | 15bed0f | 2011-07-11 16:28:35 -0500 | [diff] [blame] | 2705 | /* |
Andy Lutomirski | 812089e | 2012-12-01 12:37:20 -0800 | [diff] [blame] | 2706 | * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize |
Manoj Iyer | 15bed0f | 2011-07-11 16:28:35 -0500 | [diff] [blame] | 2707 | * certain types of SD/MMC cards. Lowering the SD base |
| 2708 | * clock frequency from 200Mhz to 50Mhz fixes this issue. |
| 2709 | * |
| 2710 | * 0x150 - SD2.0 mode enable for changing base clock |
| 2711 | * frequency to 50Mhz |
| 2712 | * 0xe1 - Base clock frequency |
| 2713 | * 0x32 - 50Mhz new clock frequency |
| 2714 | * 0xf9 - Key register for 0x150 |
| 2715 | * 0xfc - key register for 0xe1 |
| 2716 | */ |
Andy Lutomirski | 812089e | 2012-12-01 12:37:20 -0800 | [diff] [blame] | 2717 | if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || |
| 2718 | dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { |
Manoj Iyer | 15bed0f | 2011-07-11 16:28:35 -0500 | [diff] [blame] | 2719 | pci_write_config_byte(dev, 0xf9, 0xfc); |
| 2720 | pci_write_config_byte(dev, 0x150, 0x10); |
| 2721 | pci_write_config_byte(dev, 0xf9, 0x00); |
| 2722 | pci_write_config_byte(dev, 0xfc, 0x01); |
| 2723 | pci_write_config_byte(dev, 0xe1, 0x32); |
| 2724 | pci_write_config_byte(dev, 0xfc, 0x00); |
| 2725 | |
| 2726 | dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); |
| 2727 | } |
Josh Boyer | 3e309cd | 2011-10-05 11:44:50 -0400 | [diff] [blame] | 2728 | |
| 2729 | pci_read_config_byte(dev, 0xCB, &disable); |
| 2730 | |
| 2731 | if (disable & 0x02) |
| 2732 | return; |
| 2733 | |
| 2734 | pci_read_config_byte(dev, 0xCA, &write_enable); |
| 2735 | pci_write_config_byte(dev, 0xCA, 0x57); |
| 2736 | pci_write_config_byte(dev, 0xCB, disable | 0x02); |
| 2737 | pci_write_config_byte(dev, 0xCA, write_enable); |
| 2738 | |
| 2739 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); |
| 2740 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); |
| 2741 | |
Maxim Levitsky | 03cd8f7 | 2010-03-05 13:43:20 -0800 | [diff] [blame] | 2742 | } |
| 2743 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); |
| 2744 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); |
Andy Lutomirski | 812089e | 2012-12-01 12:37:20 -0800 | [diff] [blame] | 2745 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
| 2746 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
Manoj Iyer | be98ca6 | 2011-05-26 11:19:05 -0500 | [diff] [blame] | 2747 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
| 2748 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
Maxim Levitsky | 03cd8f7 | 2010-03-05 13:43:20 -0800 | [diff] [blame] | 2749 | #endif /*CONFIG_MMC_RICOH_MMC*/ |
| 2750 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2751 | #ifdef CONFIG_DMAR_TABLE |
Suresh Siddha | 254e420 | 2010-12-06 12:26:30 -0800 | [diff] [blame] | 2752 | #define VTUNCERRMSK_REG 0x1ac |
| 2753 | #define VTD_MSK_SPEC_ERRORS (1 << 31) |
| 2754 | /* |
| 2755 | * This is a quirk for masking vt-d spec defined errors to platform error |
| 2756 | * handling logic. With out this, platforms using Intel 7500, 5500 chipsets |
| 2757 | * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based |
| 2758 | * on the RAS config settings of the platform) when a vt-d fault happens. |
| 2759 | * The resulting SMI caused the system to hang. |
| 2760 | * |
| 2761 | * VT-d spec related errors are already handled by the VT-d OS code, so no |
| 2762 | * need to report the same error through other channels. |
| 2763 | */ |
| 2764 | static void vtd_mask_spec_errors(struct pci_dev *dev) |
| 2765 | { |
| 2766 | u32 word; |
| 2767 | |
| 2768 | pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); |
| 2769 | pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); |
| 2770 | } |
| 2771 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); |
| 2772 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); |
| 2773 | #endif |
Maxim Levitsky | 03cd8f7 | 2010-03-05 13:43:20 -0800 | [diff] [blame] | 2774 | |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2775 | static void fixup_ti816x_class(struct pci_dev *dev) |
Hemant Pedanekar | 63c4408 | 2011-04-05 12:32:50 +0530 | [diff] [blame] | 2776 | { |
| 2777 | /* TI 816x devices do not have class code set when in PCIe boot mode */ |
Yinghai Lu | 40c9623 | 2012-02-23 23:46:58 -0800 | [diff] [blame] | 2778 | dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); |
| 2779 | dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; |
Hemant Pedanekar | 63c4408 | 2011-04-05 12:32:50 +0530 | [diff] [blame] | 2780 | } |
Yinghai Lu | 40c9623 | 2012-02-23 23:46:58 -0800 | [diff] [blame] | 2781 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, |
| 2782 | PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class); |
Hemant Pedanekar | 63c4408 | 2011-04-05 12:32:50 +0530 | [diff] [blame] | 2783 | |
Ben Hutchings | a94d072 | 2011-10-05 22:35:03 +0100 | [diff] [blame] | 2784 | /* Some PCIe devices do not work reliably with the claimed maximum |
| 2785 | * payload size supported. |
| 2786 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2787 | static void fixup_mpss_256(struct pci_dev *dev) |
Ben Hutchings | a94d072 | 2011-10-05 22:35:03 +0100 | [diff] [blame] | 2788 | { |
| 2789 | dev->pcie_mpss = 1; /* 256 bytes */ |
| 2790 | } |
| 2791 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, |
| 2792 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); |
| 2793 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, |
| 2794 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); |
| 2795 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, |
| 2796 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); |
| 2797 | |
Jon Mason | d387a8d | 2011-10-14 14:56:13 -0500 | [diff] [blame] | 2798 | /* Intel 5000 and 5100 Memory controllers have an errata with read completion |
| 2799 | * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. |
| 2800 | * Since there is no way of knowing what the PCIE MPS on each fabric will be |
| 2801 | * until all of the devices are discovered and buses walked, read completion |
| 2802 | * coalescing must be disabled. Unfortunately, it cannot be re-enabled because |
| 2803 | * it is possible to hotplug a device with MPS of 256B. |
| 2804 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2805 | static void quirk_intel_mc_errata(struct pci_dev *dev) |
Jon Mason | d387a8d | 2011-10-14 14:56:13 -0500 | [diff] [blame] | 2806 | { |
| 2807 | int err; |
| 2808 | u16 rcc; |
| 2809 | |
| 2810 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) |
| 2811 | return; |
| 2812 | |
| 2813 | /* Intel errata specifies bits to change but does not say what they are. |
| 2814 | * Keeping them magical until such time as the registers and values can |
| 2815 | * be explained. |
| 2816 | */ |
| 2817 | err = pci_read_config_word(dev, 0x48, &rcc); |
| 2818 | if (err) { |
| 2819 | dev_err(&dev->dev, "Error attempting to read the read " |
| 2820 | "completion coalescing register.\n"); |
| 2821 | return; |
| 2822 | } |
| 2823 | |
| 2824 | if (!(rcc & (1 << 10))) |
| 2825 | return; |
| 2826 | |
| 2827 | rcc &= ~(1 << 10); |
| 2828 | |
| 2829 | err = pci_write_config_word(dev, 0x48, rcc); |
| 2830 | if (err) { |
| 2831 | dev_err(&dev->dev, "Error attempting to write the read " |
| 2832 | "completion coalescing register.\n"); |
| 2833 | return; |
| 2834 | } |
| 2835 | |
| 2836 | pr_info_once("Read completion coalescing disabled due to hardware " |
| 2837 | "errata relating to 256B MPS.\n"); |
| 2838 | } |
| 2839 | /* Intel 5000 series memory controllers and ports 2-7 */ |
| 2840 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); |
| 2841 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); |
| 2842 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); |
| 2843 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); |
| 2844 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); |
| 2845 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); |
| 2846 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); |
| 2847 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); |
| 2848 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); |
| 2849 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); |
| 2850 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); |
| 2851 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); |
| 2852 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); |
| 2853 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); |
| 2854 | /* Intel 5100 series memory controllers and ports 2-7 */ |
| 2855 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); |
| 2856 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); |
| 2857 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); |
| 2858 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); |
| 2859 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); |
| 2860 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); |
| 2861 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); |
| 2862 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); |
| 2863 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); |
| 2864 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); |
| 2865 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); |
| 2866 | |
Arjan van de Ven | 3209874 | 2012-01-30 20:52:07 -0800 | [diff] [blame] | 2867 | |
Jon Mason | 12b0318 | 2013-05-06 08:03:33 +0000 | [diff] [blame] | 2868 | /* |
| 2869 | * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To |
| 2870 | * work around this, query the size it should be configured to by the device and |
| 2871 | * modify the resource end to correspond to this new size. |
| 2872 | */ |
| 2873 | static void quirk_intel_ntb(struct pci_dev *dev) |
| 2874 | { |
| 2875 | int rc; |
| 2876 | u8 val; |
| 2877 | |
| 2878 | rc = pci_read_config_byte(dev, 0x00D0, &val); |
| 2879 | if (rc) |
| 2880 | return; |
| 2881 | |
| 2882 | dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; |
| 2883 | |
| 2884 | rc = pci_read_config_byte(dev, 0x00D1, &val); |
| 2885 | if (rc) |
| 2886 | return; |
| 2887 | |
| 2888 | dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; |
| 2889 | } |
| 2890 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); |
| 2891 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); |
| 2892 | |
Myron Stowe | 2729d5b | 2012-07-09 15:36:02 -0600 | [diff] [blame] | 2893 | static ktime_t fixup_debug_start(struct pci_dev *dev, |
| 2894 | void (*fn)(struct pci_dev *dev)) |
Arjan van de Ven | 3209874 | 2012-01-30 20:52:07 -0800 | [diff] [blame] | 2895 | { |
Myron Stowe | 2729d5b | 2012-07-09 15:36:02 -0600 | [diff] [blame] | 2896 | ktime_t calltime = ktime_set(0, 0); |
| 2897 | |
| 2898 | dev_dbg(&dev->dev, "calling %pF\n", fn); |
| 2899 | if (initcall_debug) { |
| 2900 | pr_debug("calling %pF @ %i for %s\n", |
| 2901 | fn, task_pid_nr(current), dev_name(&dev->dev)); |
| 2902 | calltime = ktime_get(); |
| 2903 | } |
| 2904 | |
| 2905 | return calltime; |
| 2906 | } |
| 2907 | |
| 2908 | static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, |
| 2909 | void (*fn)(struct pci_dev *dev)) |
| 2910 | { |
| 2911 | ktime_t delta, rettime; |
Arjan van de Ven | 3209874 | 2012-01-30 20:52:07 -0800 | [diff] [blame] | 2912 | unsigned long long duration; |
| 2913 | |
Myron Stowe | 2729d5b | 2012-07-09 15:36:02 -0600 | [diff] [blame] | 2914 | if (initcall_debug) { |
| 2915 | rettime = ktime_get(); |
| 2916 | delta = ktime_sub(rettime, calltime); |
| 2917 | duration = (unsigned long long) ktime_to_ns(delta) >> 10; |
| 2918 | pr_debug("pci fixup %pF returned after %lld usecs for %s\n", |
| 2919 | fn, duration, dev_name(&dev->dev)); |
| 2920 | } |
Arjan van de Ven | 3209874 | 2012-01-30 20:52:07 -0800 | [diff] [blame] | 2921 | } |
| 2922 | |
Thomas Jarosch | f67fd55 | 2011-12-07 22:08:11 +0100 | [diff] [blame] | 2923 | /* |
| 2924 | * Some BIOS implementations leave the Intel GPU interrupts enabled, |
| 2925 | * even though no one is handling them (f.e. i915 driver is never loaded). |
| 2926 | * Additionally the interrupt destination is not set up properly |
| 2927 | * and the interrupt ends up -somewhere-. |
| 2928 | * |
| 2929 | * These spurious interrupts are "sticky" and the kernel disables |
| 2930 | * the (shared) interrupt line after 100.000+ generated interrupts. |
| 2931 | * |
| 2932 | * Fix it by disabling the still enabled interrupts. |
| 2933 | * This resolves crashes often seen on monitor unplug. |
| 2934 | */ |
| 2935 | #define I915_DEIER_REG 0x4400c |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2936 | static void disable_igfx_irq(struct pci_dev *dev) |
Thomas Jarosch | f67fd55 | 2011-12-07 22:08:11 +0100 | [diff] [blame] | 2937 | { |
| 2938 | void __iomem *regs = pci_iomap(dev, 0, 0); |
| 2939 | if (regs == NULL) { |
| 2940 | dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); |
| 2941 | return; |
| 2942 | } |
| 2943 | |
| 2944 | /* Check if any interrupt line is still enabled */ |
| 2945 | if (readl(regs + I915_DEIER_REG) != 0) { |
| 2946 | dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; " |
| 2947 | "disabling\n"); |
| 2948 | |
| 2949 | writel(0, regs + I915_DEIER_REG); |
| 2950 | } |
| 2951 | |
| 2952 | pci_iounmap(dev, regs); |
| 2953 | } |
| 2954 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); |
| 2955 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); |
| 2956 | |
Bjorn Helgaas | fbebb9f | 2012-06-16 14:40:22 -0600 | [diff] [blame] | 2957 | /* |
| 2958 | * Some devices may pass our check in pci_intx_mask_supported if |
| 2959 | * PCI_COMMAND_INTX_DISABLE works though they actually do not properly |
| 2960 | * support this feature. |
| 2961 | */ |
Bill Pemberton | 15856ad | 2012-11-21 15:35:00 -0500 | [diff] [blame] | 2962 | static void quirk_broken_intx_masking(struct pci_dev *dev) |
Bjorn Helgaas | fbebb9f | 2012-06-16 14:40:22 -0600 | [diff] [blame] | 2963 | { |
| 2964 | dev->broken_intx_masking = 1; |
| 2965 | } |
Jan Kiszka | de509f9 | 2012-06-07 10:30:59 +0200 | [diff] [blame] | 2966 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030, |
| 2967 | quirk_broken_intx_masking); |
Alex Williamson | 0bdb3b2 | 2012-06-07 11:01:59 -0600 | [diff] [blame] | 2968 | DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ |
| 2969 | quirk_broken_intx_masking); |
Bjorn Helgaas | fbebb9f | 2012-06-16 14:40:22 -0600 | [diff] [blame] | 2970 | |
Jesse Barnes | bfb0f33 | 2008-10-27 17:50:21 -0700 | [diff] [blame] | 2971 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, |
| 2972 | struct pci_fixup *end) |
Thomas Petazzoni | 3d13731 | 2008-08-19 10:28:24 +0200 | [diff] [blame] | 2973 | { |
Myron Stowe | 2729d5b | 2012-07-09 15:36:02 -0600 | [diff] [blame] | 2974 | ktime_t calltime; |
| 2975 | |
Yinghai Lu | f4ca5c6 | 2012-02-23 23:46:49 -0800 | [diff] [blame] | 2976 | for (; f < end; f++) |
| 2977 | if ((f->class == (u32) (dev->class >> f->class_shift) || |
| 2978 | f->class == (u32) PCI_ANY_ID) && |
| 2979 | (f->vendor == dev->vendor || |
| 2980 | f->vendor == (u16) PCI_ANY_ID) && |
| 2981 | (f->device == dev->device || |
| 2982 | f->device == (u16) PCI_ANY_ID)) { |
Myron Stowe | 2729d5b | 2012-07-09 15:36:02 -0600 | [diff] [blame] | 2983 | calltime = fixup_debug_start(dev, f->hook); |
| 2984 | f->hook(dev); |
| 2985 | fixup_debug_report(dev, calltime, f->hook); |
Thomas Petazzoni | 3d13731 | 2008-08-19 10:28:24 +0200 | [diff] [blame] | 2986 | } |
Thomas Petazzoni | 3d13731 | 2008-08-19 10:28:24 +0200 | [diff] [blame] | 2987 | } |
| 2988 | |
| 2989 | extern struct pci_fixup __start_pci_fixups_early[]; |
| 2990 | extern struct pci_fixup __end_pci_fixups_early[]; |
| 2991 | extern struct pci_fixup __start_pci_fixups_header[]; |
| 2992 | extern struct pci_fixup __end_pci_fixups_header[]; |
| 2993 | extern struct pci_fixup __start_pci_fixups_final[]; |
| 2994 | extern struct pci_fixup __end_pci_fixups_final[]; |
| 2995 | extern struct pci_fixup __start_pci_fixups_enable[]; |
| 2996 | extern struct pci_fixup __end_pci_fixups_enable[]; |
| 2997 | extern struct pci_fixup __start_pci_fixups_resume[]; |
| 2998 | extern struct pci_fixup __end_pci_fixups_resume[]; |
| 2999 | extern struct pci_fixup __start_pci_fixups_resume_early[]; |
| 3000 | extern struct pci_fixup __end_pci_fixups_resume_early[]; |
| 3001 | extern struct pci_fixup __start_pci_fixups_suspend[]; |
| 3002 | extern struct pci_fixup __end_pci_fixups_suspend[]; |
| 3003 | |
Myron Stowe | 95df8b8 | 2012-07-13 14:29:00 -0600 | [diff] [blame] | 3004 | static bool pci_apply_fixup_final_quirks; |
Thomas Petazzoni | 3d13731 | 2008-08-19 10:28:24 +0200 | [diff] [blame] | 3005 | |
| 3006 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) |
| 3007 | { |
| 3008 | struct pci_fixup *start, *end; |
| 3009 | |
| 3010 | switch(pass) { |
| 3011 | case pci_fixup_early: |
| 3012 | start = __start_pci_fixups_early; |
| 3013 | end = __end_pci_fixups_early; |
| 3014 | break; |
| 3015 | |
| 3016 | case pci_fixup_header: |
| 3017 | start = __start_pci_fixups_header; |
| 3018 | end = __end_pci_fixups_header; |
| 3019 | break; |
| 3020 | |
| 3021 | case pci_fixup_final: |
Myron Stowe | 95df8b8 | 2012-07-13 14:29:00 -0600 | [diff] [blame] | 3022 | if (!pci_apply_fixup_final_quirks) |
| 3023 | return; |
Thomas Petazzoni | 3d13731 | 2008-08-19 10:28:24 +0200 | [diff] [blame] | 3024 | start = __start_pci_fixups_final; |
| 3025 | end = __end_pci_fixups_final; |
| 3026 | break; |
| 3027 | |
| 3028 | case pci_fixup_enable: |
| 3029 | start = __start_pci_fixups_enable; |
| 3030 | end = __end_pci_fixups_enable; |
| 3031 | break; |
| 3032 | |
| 3033 | case pci_fixup_resume: |
| 3034 | start = __start_pci_fixups_resume; |
| 3035 | end = __end_pci_fixups_resume; |
| 3036 | break; |
| 3037 | |
| 3038 | case pci_fixup_resume_early: |
| 3039 | start = __start_pci_fixups_resume_early; |
| 3040 | end = __end_pci_fixups_resume_early; |
| 3041 | break; |
| 3042 | |
| 3043 | case pci_fixup_suspend: |
| 3044 | start = __start_pci_fixups_suspend; |
| 3045 | end = __end_pci_fixups_suspend; |
| 3046 | break; |
| 3047 | |
| 3048 | default: |
| 3049 | /* stupid compiler warning, you would think with an enum... */ |
| 3050 | return; |
| 3051 | } |
| 3052 | pci_do_fixups(dev, start, end); |
| 3053 | } |
Rafael J. Wysocki | 93177a7 | 2010-01-02 22:57:24 +0100 | [diff] [blame] | 3054 | EXPORT_SYMBOL(pci_fixup_device); |
David Woodhouse | 8d86fb2 | 2009-10-12 12:48:43 +0100 | [diff] [blame] | 3055 | |
Myron Stowe | 735bff1 | 2012-07-09 15:36:46 -0600 | [diff] [blame] | 3056 | |
David Woodhouse | 0001026 | 2009-10-12 12:50:34 +0100 | [diff] [blame] | 3057 | static int __init pci_apply_final_quirks(void) |
David Woodhouse | 8d86fb2 | 2009-10-12 12:48:43 +0100 | [diff] [blame] | 3058 | { |
| 3059 | struct pci_dev *dev = NULL; |
Jesse Barnes | ac1aa47 | 2009-10-26 13:20:44 -0700 | [diff] [blame] | 3060 | u8 cls = 0; |
| 3061 | u8 tmp; |
| 3062 | |
| 3063 | if (pci_cache_line_size) |
| 3064 | printk(KERN_DEBUG "PCI: CLS %u bytes\n", |
| 3065 | pci_cache_line_size << 2); |
David Woodhouse | 8d86fb2 | 2009-10-12 12:48:43 +0100 | [diff] [blame] | 3066 | |
Myron Stowe | 95df8b8 | 2012-07-13 14:29:00 -0600 | [diff] [blame] | 3067 | pci_apply_fixup_final_quirks = true; |
Kulikov Vasiliy | 4e344b1 | 2010-07-03 20:04:39 +0400 | [diff] [blame] | 3068 | for_each_pci_dev(dev) { |
David Woodhouse | 8d86fb2 | 2009-10-12 12:48:43 +0100 | [diff] [blame] | 3069 | pci_fixup_device(pci_fixup_final, dev); |
Jesse Barnes | ac1aa47 | 2009-10-26 13:20:44 -0700 | [diff] [blame] | 3070 | /* |
| 3071 | * If arch hasn't set it explicitly yet, use the CLS |
| 3072 | * value shared by all PCI devices. If there's a |
| 3073 | * mismatch, fall back to the default value. |
| 3074 | */ |
| 3075 | if (!pci_cache_line_size) { |
| 3076 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); |
| 3077 | if (!cls) |
| 3078 | cls = tmp; |
| 3079 | if (!tmp || cls == tmp) |
| 3080 | continue; |
| 3081 | |
| 3082 | printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " |
| 3083 | "using %u bytes\n", cls << 2, tmp << 2, |
| 3084 | pci_dfl_cache_line_size << 2); |
| 3085 | pci_cache_line_size = pci_dfl_cache_line_size; |
| 3086 | } |
| 3087 | } |
Myron Stowe | 735bff1 | 2012-07-09 15:36:46 -0600 | [diff] [blame] | 3088 | |
Jesse Barnes | ac1aa47 | 2009-10-26 13:20:44 -0700 | [diff] [blame] | 3089 | if (!pci_cache_line_size) { |
| 3090 | printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", |
| 3091 | cls << 2, pci_dfl_cache_line_size << 2); |
Csaba Henk | 2820f33 | 2009-12-15 17:55:25 +0530 | [diff] [blame] | 3092 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
David Woodhouse | 8d86fb2 | 2009-10-12 12:48:43 +0100 | [diff] [blame] | 3093 | } |
| 3094 | |
| 3095 | return 0; |
| 3096 | } |
| 3097 | |
David Woodhouse | cf6f3bf | 2009-10-12 12:51:22 +0100 | [diff] [blame] | 3098 | fs_initcall_sync(pci_apply_final_quirks); |
Dexuan Cui | b9c3b26 | 2009-12-07 13:03:21 +0800 | [diff] [blame] | 3099 | |
| 3100 | /* |
| 3101 | * Followings are device-specific reset methods which can be used to |
| 3102 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are |
| 3103 | * not available. |
| 3104 | */ |
Dexuan Cui | aeb3001 | 2009-12-07 13:03:22 +0800 | [diff] [blame] | 3105 | static int reset_intel_generic_dev(struct pci_dev *dev, int probe) |
| 3106 | { |
| 3107 | int pos; |
| 3108 | |
| 3109 | /* only implement PCI_CLASS_SERIAL_USB at present */ |
| 3110 | if (dev->class == PCI_CLASS_SERIAL_USB) { |
| 3111 | pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); |
| 3112 | if (!pos) |
| 3113 | return -ENOTTY; |
| 3114 | |
| 3115 | if (probe) |
| 3116 | return 0; |
| 3117 | |
| 3118 | pci_write_config_byte(dev, pos + 0x4, 1); |
| 3119 | msleep(100); |
| 3120 | |
| 3121 | return 0; |
| 3122 | } else { |
| 3123 | return -ENOTTY; |
| 3124 | } |
| 3125 | } |
| 3126 | |
Dexuan Cui | c763e7b | 2009-12-07 13:03:23 +0800 | [diff] [blame] | 3127 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) |
| 3128 | { |
Bjorn Helgaas | 76b57c6 | 2012-08-22 09:41:27 -0600 | [diff] [blame] | 3129 | /* |
| 3130 | * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf |
| 3131 | * |
| 3132 | * The 82599 supports FLR on VFs, but FLR support is reported only |
| 3133 | * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). |
| 3134 | * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP. |
| 3135 | */ |
| 3136 | |
Dexuan Cui | c763e7b | 2009-12-07 13:03:23 +0800 | [diff] [blame] | 3137 | if (probe) |
| 3138 | return 0; |
| 3139 | |
Casey Leedom | 4d708ab | 2013-08-06 15:48:39 +0530 | [diff] [blame] | 3140 | if (!pci_wait_for_pending_transaction(dev)) |
| 3141 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); |
Bjorn Helgaas | 76b57c6 | 2012-08-22 09:41:27 -0600 | [diff] [blame] | 3142 | |
Bjorn Helgaas | 76b57c6 | 2012-08-22 09:41:27 -0600 | [diff] [blame] | 3143 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
| 3144 | |
Dexuan Cui | c763e7b | 2009-12-07 13:03:23 +0800 | [diff] [blame] | 3145 | msleep(100); |
| 3146 | |
| 3147 | return 0; |
| 3148 | } |
| 3149 | |
Xudong Hao | df558de | 2012-04-27 09:16:46 -0600 | [diff] [blame] | 3150 | #include "../gpu/drm/i915/i915_reg.h" |
| 3151 | #define MSG_CTL 0x45010 |
| 3152 | #define NSDE_PWR_STATE 0xd0100 |
| 3153 | #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ |
| 3154 | |
| 3155 | static int reset_ivb_igd(struct pci_dev *dev, int probe) |
| 3156 | { |
| 3157 | void __iomem *mmio_base; |
| 3158 | unsigned long timeout; |
| 3159 | u32 val; |
| 3160 | |
| 3161 | if (probe) |
| 3162 | return 0; |
| 3163 | |
| 3164 | mmio_base = pci_iomap(dev, 0, 0); |
| 3165 | if (!mmio_base) |
| 3166 | return -ENOMEM; |
| 3167 | |
| 3168 | iowrite32(0x00000002, mmio_base + MSG_CTL); |
| 3169 | |
| 3170 | /* |
| 3171 | * Clobbering SOUTH_CHICKEN2 register is fine only if the next |
| 3172 | * driver loaded sets the right bits. However, this's a reset and |
| 3173 | * the bits have been set by i915 previously, so we clobber |
| 3174 | * SOUTH_CHICKEN2 register directly here. |
| 3175 | */ |
| 3176 | iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); |
| 3177 | |
| 3178 | val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; |
| 3179 | iowrite32(val, mmio_base + PCH_PP_CONTROL); |
| 3180 | |
| 3181 | timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); |
| 3182 | do { |
| 3183 | val = ioread32(mmio_base + PCH_PP_STATUS); |
| 3184 | if ((val & 0xb0000000) == 0) |
| 3185 | goto reset_complete; |
| 3186 | msleep(10); |
| 3187 | } while (time_before(jiffies, timeout)); |
| 3188 | dev_warn(&dev->dev, "timeout during reset\n"); |
| 3189 | |
| 3190 | reset_complete: |
| 3191 | iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); |
| 3192 | |
| 3193 | pci_iounmap(dev, mmio_base); |
| 3194 | return 0; |
| 3195 | } |
| 3196 | |
Casey Leedom | 2c6217e | 2013-08-06 15:48:37 +0530 | [diff] [blame] | 3197 | /* |
| 3198 | * Device-specific reset method for Chelsio T4-based adapters. |
| 3199 | */ |
| 3200 | static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) |
| 3201 | { |
| 3202 | u16 old_command; |
| 3203 | u16 msix_flags; |
| 3204 | |
| 3205 | /* |
| 3206 | * If this isn't a Chelsio T4-based device, return -ENOTTY indicating |
| 3207 | * that we have no device-specific reset method. |
| 3208 | */ |
| 3209 | if ((dev->device & 0xf000) != 0x4000) |
| 3210 | return -ENOTTY; |
| 3211 | |
| 3212 | /* |
| 3213 | * If this is the "probe" phase, return 0 indicating that we can |
| 3214 | * reset this device. |
| 3215 | */ |
| 3216 | if (probe) |
| 3217 | return 0; |
| 3218 | |
| 3219 | /* |
| 3220 | * T4 can wedge if there are DMAs in flight within the chip and Bus |
| 3221 | * Master has been disabled. We need to have it on till the Function |
| 3222 | * Level Reset completes. (BUS_MASTER is disabled in |
| 3223 | * pci_reset_function()). |
| 3224 | */ |
| 3225 | pci_read_config_word(dev, PCI_COMMAND, &old_command); |
| 3226 | pci_write_config_word(dev, PCI_COMMAND, |
| 3227 | old_command | PCI_COMMAND_MASTER); |
| 3228 | |
| 3229 | /* |
| 3230 | * Perform the actual device function reset, saving and restoring |
| 3231 | * configuration information around the reset. |
| 3232 | */ |
| 3233 | pci_save_state(dev); |
| 3234 | |
| 3235 | /* |
| 3236 | * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts |
| 3237 | * are disabled when an MSI-X interrupt message needs to be delivered. |
| 3238 | * So we briefly re-enable MSI-X interrupts for the duration of the |
| 3239 | * FLR. The pci_restore_state() below will restore the original |
| 3240 | * MSI-X state. |
| 3241 | */ |
| 3242 | pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); |
| 3243 | if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) |
| 3244 | pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, |
| 3245 | msix_flags | |
| 3246 | PCI_MSIX_FLAGS_ENABLE | |
| 3247 | PCI_MSIX_FLAGS_MASKALL); |
| 3248 | |
| 3249 | /* |
| 3250 | * Start of pcie_flr() code sequence. This reset code is a copy of |
| 3251 | * the guts of pcie_flr() because that's not an exported function. |
| 3252 | */ |
| 3253 | |
| 3254 | if (!pci_wait_for_pending_transaction(dev)) |
| 3255 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); |
| 3256 | |
| 3257 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
| 3258 | msleep(100); |
| 3259 | |
| 3260 | /* |
| 3261 | * End of pcie_flr() code sequence. |
| 3262 | */ |
| 3263 | |
| 3264 | /* |
| 3265 | * Restore the configuration information (BAR values, etc.) including |
| 3266 | * the original PCI Configuration Space Command word, and return |
| 3267 | * success. |
| 3268 | */ |
| 3269 | pci_restore_state(dev); |
| 3270 | pci_write_config_word(dev, PCI_COMMAND, old_command); |
| 3271 | return 0; |
| 3272 | } |
| 3273 | |
Dexuan Cui | c763e7b | 2009-12-07 13:03:23 +0800 | [diff] [blame] | 3274 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed |
Xudong Hao | df558de | 2012-04-27 09:16:46 -0600 | [diff] [blame] | 3275 | #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 |
| 3276 | #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 |
Dexuan Cui | c763e7b | 2009-12-07 13:03:23 +0800 | [diff] [blame] | 3277 | |
Rafael J. Wysocki | 5b889bf | 2009-12-31 19:06:35 +0100 | [diff] [blame] | 3278 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
Dexuan Cui | c763e7b | 2009-12-07 13:03:23 +0800 | [diff] [blame] | 3279 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
| 3280 | reset_intel_82599_sfp_virtfn }, |
Xudong Hao | df558de | 2012-04-27 09:16:46 -0600 | [diff] [blame] | 3281 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, |
| 3282 | reset_ivb_igd }, |
| 3283 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, |
| 3284 | reset_ivb_igd }, |
Dexuan Cui | aeb3001 | 2009-12-07 13:03:22 +0800 | [diff] [blame] | 3285 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
| 3286 | reset_intel_generic_dev }, |
Casey Leedom | 2c6217e | 2013-08-06 15:48:37 +0530 | [diff] [blame] | 3287 | { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, |
| 3288 | reset_chelsio_generic_dev }, |
Dexuan Cui | b9c3b26 | 2009-12-07 13:03:21 +0800 | [diff] [blame] | 3289 | { 0 } |
| 3290 | }; |
Rafael J. Wysocki | 5b889bf | 2009-12-31 19:06:35 +0100 | [diff] [blame] | 3291 | |
Xudong Hao | df558de | 2012-04-27 09:16:46 -0600 | [diff] [blame] | 3292 | /* |
| 3293 | * These device-specific reset methods are here rather than in a driver |
| 3294 | * because when a host assigns a device to a guest VM, the host may need |
| 3295 | * to reset the device but probably doesn't have a driver for it. |
| 3296 | */ |
Rafael J. Wysocki | 5b889bf | 2009-12-31 19:06:35 +0100 | [diff] [blame] | 3297 | int pci_dev_specific_reset(struct pci_dev *dev, int probe) |
| 3298 | { |
Linus Torvalds | df9d1e8 | 2009-12-31 16:44:43 -0800 | [diff] [blame] | 3299 | const struct pci_dev_reset_methods *i; |
Rafael J. Wysocki | 5b889bf | 2009-12-31 19:06:35 +0100 | [diff] [blame] | 3300 | |
| 3301 | for (i = pci_dev_reset_methods; i->reset; i++) { |
| 3302 | if ((i->vendor == dev->vendor || |
| 3303 | i->vendor == (u16)PCI_ANY_ID) && |
| 3304 | (i->device == dev->device || |
| 3305 | i->device == (u16)PCI_ANY_ID)) |
| 3306 | return i->reset(dev, probe); |
| 3307 | } |
| 3308 | |
| 3309 | return -ENOTTY; |
| 3310 | } |
Alex Williamson | 12ea6ca | 2012-06-11 05:26:55 +0000 | [diff] [blame] | 3311 | |
| 3312 | static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev) |
| 3313 | { |
| 3314 | if (!PCI_FUNC(dev->devfn)) |
| 3315 | return pci_dev_get(dev); |
| 3316 | |
| 3317 | return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
| 3318 | } |
| 3319 | |
| 3320 | static const struct pci_dev_dma_source { |
| 3321 | u16 vendor; |
| 3322 | u16 device; |
| 3323 | struct pci_dev *(*dma_source)(struct pci_dev *dev); |
| 3324 | } pci_dev_dma_source[] = { |
| 3325 | /* |
| 3326 | * https://bugzilla.redhat.com/show_bug.cgi?id=605888 |
| 3327 | * |
| 3328 | * Some Ricoh devices use the function 0 source ID for DMA on |
| 3329 | * other functions of a multifunction device. The DMA devices |
| 3330 | * is therefore function 0, which will have implications of the |
| 3331 | * iommu grouping of these devices. |
| 3332 | */ |
| 3333 | { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source }, |
| 3334 | { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source }, |
| 3335 | { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source }, |
| 3336 | { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source }, |
| 3337 | { 0 } |
| 3338 | }; |
| 3339 | |
| 3340 | /* |
| 3341 | * IOMMUs with isolation capabilities need to be programmed with the |
| 3342 | * correct source ID of a device. In most cases, the source ID matches |
| 3343 | * the device doing the DMA, but sometimes hardware is broken and will |
| 3344 | * tag the DMA as being sourced from a different device. This function |
| 3345 | * allows that translation. Note that the reference count of the |
| 3346 | * returned device is incremented on all paths. |
| 3347 | */ |
| 3348 | struct pci_dev *pci_get_dma_source(struct pci_dev *dev) |
| 3349 | { |
| 3350 | const struct pci_dev_dma_source *i; |
| 3351 | |
| 3352 | for (i = pci_dev_dma_source; i->dma_source; i++) { |
| 3353 | if ((i->vendor == dev->vendor || |
| 3354 | i->vendor == (u16)PCI_ANY_ID) && |
| 3355 | (i->device == dev->device || |
| 3356 | i->device == (u16)PCI_ANY_ID)) |
| 3357 | return i->dma_source(dev); |
| 3358 | } |
| 3359 | |
| 3360 | return pci_dev_get(dev); |
| 3361 | } |
Alex Williamson | ad80575 | 2012-06-11 05:27:07 +0000 | [diff] [blame] | 3362 | |
Alex Williamson | 15b100d | 2013-06-27 16:40:00 -0600 | [diff] [blame] | 3363 | /* |
| 3364 | * AMD has indicated that the devices below do not support peer-to-peer |
| 3365 | * in any system where they are found in the southbridge with an AMD |
| 3366 | * IOMMU in the system. Multifunction devices that do not support |
| 3367 | * peer-to-peer between functions can claim to support a subset of ACS. |
| 3368 | * Such devices effectively enable request redirect (RR) and completion |
| 3369 | * redirect (CR) since all transactions are redirected to the upstream |
| 3370 | * root complex. |
| 3371 | * |
| 3372 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 |
| 3373 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 |
| 3374 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 |
| 3375 | * |
| 3376 | * 1002:4385 SBx00 SMBus Controller |
| 3377 | * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller |
| 3378 | * 1002:4383 SBx00 Azalia (Intel HDA) |
| 3379 | * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller |
| 3380 | * 1002:4384 SBx00 PCI to PCI Bridge |
| 3381 | * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller |
| 3382 | */ |
| 3383 | static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) |
| 3384 | { |
| 3385 | #ifdef CONFIG_ACPI |
| 3386 | struct acpi_table_header *header = NULL; |
| 3387 | acpi_status status; |
| 3388 | |
| 3389 | /* Targeting multifunction devices on the SB (appears on root bus) */ |
| 3390 | if (!dev->multifunction || !pci_is_root_bus(dev->bus)) |
| 3391 | return -ENODEV; |
| 3392 | |
| 3393 | /* The IVRS table describes the AMD IOMMU */ |
| 3394 | status = acpi_get_table("IVRS", 0, &header); |
| 3395 | if (ACPI_FAILURE(status)) |
| 3396 | return -ENODEV; |
| 3397 | |
| 3398 | /* Filter out flags not applicable to multifunction */ |
| 3399 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); |
| 3400 | |
| 3401 | return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; |
| 3402 | #else |
| 3403 | return -ENODEV; |
| 3404 | #endif |
| 3405 | } |
| 3406 | |
Alex Williamson | ad80575 | 2012-06-11 05:27:07 +0000 | [diff] [blame] | 3407 | static const struct pci_dev_acs_enabled { |
| 3408 | u16 vendor; |
| 3409 | u16 device; |
| 3410 | int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); |
| 3411 | } pci_dev_acs_enabled[] = { |
Alex Williamson | 15b100d | 2013-06-27 16:40:00 -0600 | [diff] [blame] | 3412 | { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, |
| 3413 | { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, |
| 3414 | { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, |
| 3415 | { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, |
| 3416 | { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, |
| 3417 | { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, |
Alex Williamson | ad80575 | 2012-06-11 05:27:07 +0000 | [diff] [blame] | 3418 | { 0 } |
| 3419 | }; |
| 3420 | |
| 3421 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) |
| 3422 | { |
| 3423 | const struct pci_dev_acs_enabled *i; |
| 3424 | int ret; |
| 3425 | |
| 3426 | /* |
| 3427 | * Allow devices that do not expose standard PCIe ACS capabilities |
| 3428 | * or control to indicate their support here. Multi-function express |
| 3429 | * devices which do not allow internal peer-to-peer between functions, |
| 3430 | * but do not implement PCIe ACS may wish to return true here. |
| 3431 | */ |
| 3432 | for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { |
| 3433 | if ((i->vendor == dev->vendor || |
| 3434 | i->vendor == (u16)PCI_ANY_ID) && |
| 3435 | (i->device == dev->device || |
| 3436 | i->device == (u16)PCI_ANY_ID)) { |
| 3437 | ret = i->acs_enabled(dev, acs_flags); |
| 3438 | if (ret >= 0) |
| 3439 | return ret; |
| 3440 | } |
| 3441 | } |
| 3442 | |
| 3443 | return -ENOTTY; |
| 3444 | } |