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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
3 * differently than every other instruction, so it is set to 0 (write)
4 * even though the instructions are read instructions. This means that
5 * during an abort the instructions will be treated as a write and the
6 * handler will raise a signal from unwriteable locations if they
7 * fault. We have to specifically check for these instructions
8 * from the abort handlers to treat them properly.
9 *
10 */
11
Russell Kingbe020f82011-06-26 13:42:01 +010012 .macro do_thumb_abort, fsr, pc, psr, tmp
13 tst \psr, #PSR_T_BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 beq not_thumb
Russell Kingbe020f82011-06-26 13:42:01 +010015 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
Russell King2190fed2015-08-20 10:32:02 +010016 uaccess_disable ip @ disable userspace access
Russell Kingbe020f82011-06-26 13:42:01 +010017 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
18 cmp \tmp, # 0x5600 @ Is it ldrsb?
19 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
20 tst \tmp, #1 << 11 @ L = 0 -> write
Janusz Krzysztofik6c6d8de2011-09-08 18:45:40 +010021 orreq \fsr, \fsr, #1 << 11 @ yes.
Russell Kingda740472011-06-26 16:01:26 +010022 b do_DataAbort
Linus Torvalds1da177e2005-04-16 15:20:36 -070023not_thumb:
24 .endm
25
26/*
Russell Kingbe020f82011-06-26 13:42:01 +010027 * We check for the following instruction encoding for LDRD.
Linus Torvalds1da177e2005-04-16 15:20:36 -070028 *
Russell Kingbe020f82011-06-26 13:42:01 +010029 * [27:25] == 000
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * [7:4] == 1101
31 * [20] == 0
32 */
Russell King08446b12015-08-25 14:59:15 +010033 .macro teq_ldrd, tmp, insn
34 mov \tmp, #0x0e100000
35 orr \tmp, #0x000000f0
36 and \tmp, \insn, \tmp
37 teq \tmp, #0x000000d0
Linus Torvalds1da177e2005-04-16 15:20:36 -070038 .endm