blob: d86a9ffb3f13eadde3ee66380945b8932622dc93 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/***************************************************************************/
2
3/*
Greg Ungererb671b652006-06-26 10:33:10 +10004 * pit.c -- Freescale ColdFire PIT timer. Currently this type of
5 * hardware timer only exists in the Freescale ColdFire
Greg Ungerer8d80c5e2008-02-01 17:40:21 +10006 * 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
7 * family members will probably use it too.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
Greg Ungerer8d80c5e2008-02-01 17:40:21 +10009 * Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12
13/***************************************************************************/
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/param.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
Greg Ungerer5c4525d2007-07-27 01:09:00 +100020#include <linux/irq.h>
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020021#include <linux/clockchips.h>
Greg Ungerer2f2c2672007-10-23 14:37:54 +100022#include <asm/machdep.h>
Greg Ungererb671b652006-06-26 10:33:10 +100023#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/coldfire.h>
25#include <asm/mcfpit.h>
26#include <asm/mcfsim.h>
27
28/***************************************************************************/
29
Greg Ungererb671b652006-06-26 10:33:10 +100030/*
31 * By default use timer1 as the system clock timer.
32 */
Greg Ungerer8d80c5e2008-02-01 17:40:21 +100033#define FREQ ((MCF_CLK / 2) / 64)
Greg Ungererf317c712011-03-05 23:32:35 +100034#define TA(a) (MCFPIT_BASE1 + (a))
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020035#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
Greg Ungerer8d80c5e2008-02-01 17:40:21 +100036
Greg Ungerer8d80c5e2008-02-01 17:40:21 +100037static u32 pit_cnt;
Greg Ungererb671b652006-06-26 10:33:10 +100038
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020039/*
40 * Initialize the PIT timer.
41 *
42 * This is also called after resume to bring the PIT into operation again.
43 */
44
Viresh Kumar5bbc08f2015-07-16 16:56:20 +053045static int cf_pit_set_periodic(struct clock_event_device *evt)
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020046{
Viresh Kumar5bbc08f2015-07-16 16:56:20 +053047 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
48 __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
49 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
50 MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
51 MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
52 return 0;
53}
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020054
Viresh Kumar5bbc08f2015-07-16 16:56:20 +053055static int cf_pit_set_oneshot(struct clock_event_device *evt)
56{
57 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
58 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
59 MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
60 return 0;
61}
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020062
Viresh Kumar5bbc08f2015-07-16 16:56:20 +053063static int cf_pit_shutdown(struct clock_event_device *evt)
64{
65 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
66 return 0;
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020067}
68
69/*
70 * Program the next event in oneshot mode
71 *
72 * Delta is given in PIT ticks
73 */
74static int cf_pit_next_event(unsigned long delta,
75 struct clock_event_device *evt)
76{
77 __raw_writew(delta, TA(MCFPIT_PMR));
78 return 0;
79}
80
81struct clock_event_device cf_pit_clockevent = {
Viresh Kumar5bbc08f2015-07-16 16:56:20 +053082 .name = "pit",
83 .features = CLOCK_EVT_FEAT_PERIODIC |
84 CLOCK_EVT_FEAT_ONESHOT,
85 .set_state_shutdown = cf_pit_shutdown,
86 .set_state_periodic = cf_pit_set_periodic,
87 .set_state_oneshot = cf_pit_set_oneshot,
88 .set_next_event = cf_pit_next_event,
89 .shift = 32,
90 .irq = MCF_IRQ_PIT1,
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020091};
92
93
94
Greg Ungererb671b652006-06-26 10:33:10 +100095/***************************************************************************/
96
Greg Ungerer8d80c5e2008-02-01 17:40:21 +100097static irqreturn_t pit_tick(int irq, void *dummy)
Linus Torvalds1da177e2005-04-16 15:20:36 -070098{
Sebastian Siewior2b9a6982008-04-28 11:43:04 +020099 struct clock_event_device *evt = &cf_pit_clockevent;
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000100 u16 pcsr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
102 /* Reset the ColdFire timer */
Greg Ungererb671b652006-06-26 10:33:10 +1000103 pcsr = __raw_readw(TA(MCFPIT_PCSR));
104 __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
Greg Ungerer2f2c2672007-10-23 14:37:54 +1000105
Sebastian Siewior2b9a6982008-04-28 11:43:04 +0200106 pit_cnt += PIT_CYCLES_PER_JIFFY;
107 evt->event_handler(evt);
108 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109}
110
111/***************************************************************************/
112
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000113static struct irqaction pit_irq = {
Greg Ungerer2f2c2672007-10-23 14:37:54 +1000114 .name = "timer",
Michael Opdenacker77a42792013-09-07 07:43:08 +0200115 .flags = IRQF_TIMER,
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000116 .handler = pit_tick,
Greg Ungerer5c4525d2007-07-27 01:09:00 +1000117};
118
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000119/***************************************************************************/
120
Magnus Damm8e196082009-04-21 12:24:00 -0700121static cycle_t pit_read_clk(struct clocksource *cs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122{
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000123 unsigned long flags;
124 u32 cycles;
125 u16 pcntr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000127 local_irq_save(flags);
128 pcntr = __raw_readw(TA(MCFPIT_PCNTR));
129 cycles = pit_cnt;
130 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131
Sebastian Siewior2b9a6982008-04-28 11:43:04 +0200132 return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133}
134
135/***************************************************************************/
136
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000137static struct clocksource pit_clk = {
138 .name = "pit",
Sebastian Siewior2b9a6982008-04-28 11:43:04 +0200139 .rating = 100,
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000140 .read = pit_read_clk,
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000141 .mask = CLOCKSOURCE_MASK(32),
Greg Ungerer8d80c5e2008-02-01 17:40:21 +1000142};
143
144/***************************************************************************/
145
Greg Ungerer35aefb22012-01-23 15:34:58 +1000146void hw_timer_init(irq_handler_t handler)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147{
Rusty Russell320ab2b2008-12-13 21:20:26 +1030148 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
Sebastian Siewior2b9a6982008-04-28 11:43:04 +0200149 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
150 cf_pit_clockevent.max_delta_ns =
151 clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
152 cf_pit_clockevent.min_delta_ns =
153 clockevent_delta2ns(0x3f, &cf_pit_clockevent);
154 clockevents_register_device(&cf_pit_clockevent);
155
Steven Kingbdee4e22012-06-06 14:02:14 -0700156 setup_irq(MCF_IRQ_PIT1, &pit_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
John Stultz010f3f12010-04-26 20:21:52 -0700158 clocksource_register_hz(&pit_clk, FREQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159}
160
161/***************************************************************************/