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Murali Karicheri0c4ffcf2014-09-02 17:26:19 -06001/*
2 * Keystone PCI Controller's common includes
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060015#define MAX_MSI_HOST_IRQS 8
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060016
17struct keystone_pcie {
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +053018 struct dw_pcie *pci;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060019 struct clk *clk;
Murali Karicheri8665a482014-09-10 13:12:39 -040020 /* PCI Device ID */
21 u32 device_id;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060022 int num_legacy_host_irqs;
Bjorn Helgaasda4c4be2017-08-15 16:27:57 -050023 int legacy_host_irqs[PCI_NUM_INTX];
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060024 struct device_node *legacy_intc_np;
25
26 int num_msi_host_irqs;
27 int msi_host_irqs[MAX_MSI_HOST_IRQS];
28 struct device_node *msi_intc_np;
29 struct irq_domain *legacy_irq_domain;
Murali Karicheri025dd3d2016-04-11 10:50:30 -040030 struct device_node *np;
31
32 int error_irq;
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060033
34 /* Application register space */
Bjorn Helgaas4841f3ad2016-10-06 13:36:57 -050035 void __iomem *va_app_base; /* DT 1st resource */
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060036 struct resource app;
37};
38
39/* Keystone DW specific MSI controller APIs/definitions */
40void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
Lucas Stach98a97e62015-09-18 13:58:35 -050041phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060042
43/* Keystone specific PCI controller APIs */
44void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
45void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
Bjorn Helgaas5649e4c2016-10-06 13:36:56 -050046void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
47irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060048int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
49 struct device_node *msi_intc_np);
50int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
51 unsigned int devfn, int where, int size, u32 val);
52int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
53 unsigned int devfn, int where, int size, u32 *val);
54void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
Murali Karicheri0c4ffcf2014-09-02 17:26:19 -060055void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
56void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
57void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
58void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
59int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
Yijing Wangc2791b82014-11-11 17:45:45 -070060 struct msi_controller *chip);
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +053061int ks_dw_pcie_link_up(struct dw_pcie *pci);