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Paul Walmsleyf2ab9972009-01-28 12:27:37 -07001/*
2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
3 *
4 * Copyright (C) 2005, 2008 Texas Instruments Inc.
5 * Copyright (C) 2005, 2008 Nokia Corporation
6 *
7 * Tony Lindgren <tony@atomide.com>
8 * Paul Walmsley
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
Paul Walmsley87246b72009-01-28 12:27:39 -070015#undef DEBUG
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070016
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
Paul Walmsleya135eaa2012-09-27 10:33:34 -060026#include "common.h"
27#include "clock.h"
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070028#include "sdrc.h"
29
Jean Pihet58cda882009-07-24 19:43:25 -060030static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
Paul Walmsley87246b72009-01-28 12:27:39 -070031
Paul Walmsleyf2ab9972009-01-28 12:27:37 -070032void __iomem *omap2_sdrc_base;
33void __iomem *omap2_sms_base;
34
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +030035struct omap2_sms_regs {
36 u32 sms_sysconfig;
37};
38
39static struct omap2_sms_regs sms_context;
40
Paul Walmsley98cfe5a2009-05-12 17:27:09 -060041/* SDRC_POWER register bits */
42#define SDRC_POWER_EXTCLKDIS_SHIFT 3
43#define SDRC_POWER_PWDENA_SHIFT 2
44#define SDRC_POWER_PAGEPOLICY_SHIFT 0
Paul Walmsley87246b72009-01-28 12:27:39 -070045
46/**
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +030047 * omap2_sms_save_context - Save SMS registers
48 *
49 * Save SMS registers that need to be restored after off mode.
50 */
51void omap2_sms_save_context(void)
52{
53 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
54}
55
56/**
57 * omap2_sms_restore_context - Restore SMS registers
58 *
59 * Restore SMS registers that need to be Restored after off mode.
60 */
61void omap2_sms_restore_context(void)
62{
63 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
64}
65
66/**
Paul Walmsley87246b72009-01-28 12:27:39 -070067 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
68 * @r: SDRC clock rate (in Hz)
Jean Pihet58cda882009-07-24 19:43:25 -060069 * @sdrc_cs0: chip select 0 ram timings **
70 * @sdrc_cs1: chip select 1 ram timings **
Paul Walmsley87246b72009-01-28 12:27:39 -070071 *
72 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
Jean Pihet58cda882009-07-24 19:43:25 -060073 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
74 * structs,for a given SDRC clock rate 'r'.
75 * These parameters control various timing delays in the SDRAM controller
76 * that are expressed in terms of the number of SDRC clock cycles to
77 * wait; hence the clock rate dependency.
78 *
79 * Supports 2 different timing parameters for both chip selects.
80 *
81 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
82 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
83 * as sdrc_init_params_cs_0.
84 *
85 * Fills in the struct omap_sdrc_params * for each chip select.
86 * Returns 0 upon success or -1 upon failure.
Paul Walmsley87246b72009-01-28 12:27:39 -070087 */
Jean Pihet58cda882009-07-24 19:43:25 -060088int omap2_sdrc_get_params(unsigned long r,
89 struct omap_sdrc_params **sdrc_cs0,
90 struct omap_sdrc_params **sdrc_cs1)
Paul Walmsley87246b72009-01-28 12:27:39 -070091{
Jean Pihet58cda882009-07-24 19:43:25 -060092 struct omap_sdrc_params *sp0, *sp1;
Paul Walmsley87246b72009-01-28 12:27:39 -070093
Jean Pihet58cda882009-07-24 19:43:25 -060094 if (!sdrc_init_params_cs0)
95 return -1;
Kevin Hilman8bd22942009-05-28 10:56:16 -070096
Jean Pihet58cda882009-07-24 19:43:25 -060097 sp0 = sdrc_init_params_cs0;
98 sp1 = sdrc_init_params_cs1;
Paul Walmsley87246b72009-01-28 12:27:39 -070099
Jean Pihet58cda882009-07-24 19:43:25 -0600100 while (sp0->rate && sp0->rate != r) {
101 sp0++;
102 if (sdrc_init_params_cs1)
103 sp1++;
104 }
Paul Walmsley87246b72009-01-28 12:27:39 -0700105
Jean Pihet58cda882009-07-24 19:43:25 -0600106 if (!sp0->rate)
107 return -1;
Paul Walmsley87246b72009-01-28 12:27:39 -0700108
Jean Pihet58cda882009-07-24 19:43:25 -0600109 *sdrc_cs0 = sp0;
110 *sdrc_cs1 = sp1;
111 return 0;
Paul Walmsley87246b72009-01-28 12:27:39 -0700112}
113
114
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600115void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700116{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600117 omap2_sdrc_base = sdrc;
118 omap2_sms_base = sms;
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700119}
120
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600121/**
122 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
Jean Pihet58cda882009-07-24 19:43:25 -0600123 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
124 * Support for 2 chip selects timings
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600125 *
126 * Turn on smart idle modes for SDRAM scheduler and controller.
127 * Program a known-good configuration for the SDRC to deal with buggy
128 * bootloaders.
129 */
Jean Pihet58cda882009-07-24 19:43:25 -0600130void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
131 struct omap_sdrc_params *sdrc_cs1)
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700132{
133 u32 l;
134
135 l = sms_read_reg(SMS_SYSCONFIG);
136 l &= ~(0x3 << 3);
137 l |= (0x2 << 3);
138 sms_write_reg(l, SMS_SYSCONFIG);
139
140 l = sdrc_read_reg(SDRC_SYSCONFIG);
141 l &= ~(0x3 << 3);
142 l |= (0x2 << 3);
143 sdrc_write_reg(l, SDRC_SYSCONFIG);
Paul Walmsley87246b72009-01-28 12:27:39 -0700144
Jean Pihet58cda882009-07-24 19:43:25 -0600145 sdrc_init_params_cs0 = sdrc_cs0;
146 sdrc_init_params_cs1 = sdrc_cs1;
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600147
148 /* XXX Enable SRFRONIDLEREQ here also? */
Paul Walmsley75f251e2009-07-24 19:44:01 -0600149 /*
150 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
151 * can cause random memory corruption
152 */
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600153 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
Paul Walmsley98cfe5a2009-05-12 17:27:09 -0600154 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
155 sdrc_write_reg(l, SDRC_POWER);
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300156 omap2_sms_save_context();
Paul Walmsleyf2ab9972009-01-28 12:27:37 -0700157}