Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 1 | /* |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 2 | * Blackfin On-Chip Sport Emulated UART Driver |
Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 3 | * |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 4 | * Copyright 2006-2008 Analog Devices Inc. |
Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 5 | * |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 7 | * |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 8 | * Licensed under the GPL-2 or later. |
Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 9 | */ |
| 10 | |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 11 | /* |
| 12 | * This driver and the hardware supported are in term of EE-191 of ADI. |
Justin P. Mattock | 631dd1a | 2010-10-18 11:03:14 +0200 | [diff] [blame] | 13 | * http://www.analog.com/static/imported-files/application_notes/EE191.pdf |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 14 | * This application note describe how to implement a UART on a Sharc DSP, |
| 15 | * but this driver is implemented on Blackfin Processor. |
| 16 | * Transmit Frame Sync is not used by this driver to transfer data out. |
| 17 | */ |
| 18 | |
| 19 | #ifndef _BFIN_SPORT_UART_H |
| 20 | #define _BFIN_SPORT_UART_H |
Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 21 | |
| 22 | #define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */ |
| 23 | #define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */ |
| 24 | #define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */ |
| 25 | #define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */ |
| 26 | #define OFFSET_TX 0x10 /* Transmit Data Register */ |
| 27 | #define OFFSET_RX 0x18 /* Receive Data Register */ |
| 28 | #define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */ |
| 29 | #define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */ |
| 30 | #define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */ |
| 31 | #define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */ |
| 32 | #define OFFSET_STAT 0x30 /* Status Register */ |
| 33 | |
| 34 | #define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1)) |
| 35 | #define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2)) |
| 36 | #define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV)) |
| 37 | #define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV)) |
| 38 | #define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX)) |
| 39 | #define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX)) |
Sonic Zhang | a5a420d | 2010-03-09 12:25:28 -0500 | [diff] [blame] | 40 | /* |
| 41 | * If another interrupt fires while doing a 32-bit read from RX FIFO, |
| 42 | * a fake RX underflow error will be generated. So disable interrupts |
| 43 | * to prevent interruption while reading the FIFO. |
| 44 | */ |
| 45 | #define SPORT_GET_RX32(sport) \ |
| 46 | ({ \ |
| 47 | unsigned int __ret; \ |
Sonic Zhang | 07143eae | 2011-12-06 15:16:33 +0800 | [diff] [blame] | 48 | unsigned long flags; \ |
Sonic Zhang | a5a420d | 2010-03-09 12:25:28 -0500 | [diff] [blame] | 49 | if (ANOMALY_05000473) \ |
Sonic Zhang | 07143eae | 2011-12-06 15:16:33 +0800 | [diff] [blame] | 50 | local_irq_save(flags); \ |
Sonic Zhang | a5a420d | 2010-03-09 12:25:28 -0500 | [diff] [blame] | 51 | __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \ |
| 52 | if (ANOMALY_05000473) \ |
Sonic Zhang | 07143eae | 2011-12-06 15:16:33 +0800 | [diff] [blame] | 53 | local_irq_restore(flags); \ |
Sonic Zhang | a5a420d | 2010-03-09 12:25:28 -0500 | [diff] [blame] | 54 | __ret; \ |
| 55 | }) |
Bryan Wu | 2f35174 | 2008-04-30 00:52:12 -0700 | [diff] [blame] | 56 | #define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1)) |
| 57 | #define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2)) |
| 58 | #define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV)) |
| 59 | #define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV)) |
| 60 | #define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT)) |
| 61 | |
| 62 | #define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v) |
| 63 | #define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v) |
| 64 | #define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v) |
| 65 | #define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v) |
| 66 | #define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v) |
| 67 | #define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v) |
| 68 | #define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v) |
| 69 | #define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v) |
| 70 | #define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v) |
| 71 | #define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v) |
| 72 | #define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v) |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 73 | |
| 74 | #define SPORT_TX_FIFO_SIZE 8 |
| 75 | |
Sonic Zhang | 1f7d1c8 | 2010-03-09 12:25:33 -0500 | [diff] [blame] | 76 | #define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin) |
| 77 | #define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) |
| 78 | #define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) |
| 79 | |
| 80 | #if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \ |
| 81 | || defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \ |
| 82 | || defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \ |
| 83 | || defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS) |
| 84 | # define CONFIG_SERIAL_BFIN_SPORT_CTSRTS |
| 85 | #endif |
| 86 | |
sonic zhang | ccf68e5 | 2009-12-09 12:31:28 -0800 | [diff] [blame] | 87 | #endif /* _BFIN_SPORT_UART_H */ |