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gerrit-public.fairphone.software / kernel / msm-4.19 / c86845db77ce220f77e6645b18800744684946ac / . / arch / arm / plat-omap / include / plat / omap-serial.h
blob: a740a6c0e104edd221fc8bdd6f13cf724bd883b5 [file] [log] [blame]
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __OMAP_SERIAL_H__
18#define __OMAP_SERIAL_H__
19
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]23#include <plat/mux.h>
24
Benoit Cousson374b8cf2010-12-09 14:24:17 +0000[diff] [blame]25#define DRIVER_NAME "omap_uart"
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]26
27/*
28 * Use tty device name as ttyO, [O -> OMAP]
29 * in bootargs we specify as console=ttyO0 if uart1
30 * is used as console uart.
31 */
32#define OMAP_SERIAL_NAME "ttyO"
33
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]34#define OMAP_MODE13X_SPEED 230400
35
Govindraj.R32212892011-11-07 18:58:55 +0530[diff] [blame]36#define OMAP_UART_SCR_TX_EMPTY 0x08
37
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]38/* WER = 0x7F
39 * Enable module level wakeup in WER reg
40 */
41#define OMAP_UART_WER_MOD_WKUP 0X7F
42
43/* Enable XON/XOFF flow control on output */
44#define OMAP_UART_SW_TX 0x04
45
46/* Enable XON/XOFF flow control on input */
47#define OMAP_UART_SW_RX 0x04
48
49#define OMAP_UART_SYSC_RESET 0X07
50#define OMAP_UART_TCR_TRIG 0X0F
51#define OMAP_UART_SW_CLR 0XF0
52#define OMAP_UART_FIFO_CLR 0X06
53
54#define OMAP_UART_DMA_CH_FREE -1
55
56#define RX_TIMEOUT (3 * HZ)
57#define OMAP_MAX_HSUART_PORTS 4
58
59#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
60
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]61#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
62#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
63
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]64struct omap_uart_port_info {
65 bool dma_enabled; /* To specify DMA Mode */
66 unsigned int uartclk; /* UART clock rate */
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]67 upf_t flags; /* UPF_* flags */
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]68 u32 errata;
Deepak Kc86845db2011-11-09 17:33:38 +0530[diff] [blame^]69 unsigned int dma_rx_buf_size;
70 unsigned int dma_rx_timeout;
71 unsigned int autosuspend_timeout;
Govindraj.Rec3bebc2011-10-11 19:11:27 +0530[diff] [blame]72
73 int (*get_context_loss_count)(struct device *);
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]74 void (*set_forceidle)(struct platform_device *);
75 void (*set_noidle)(struct platform_device *);
Govindraj.R62f3ec5f2011-10-13 14:11:09 +0530[diff] [blame]76 void (*enable_wakeup)(struct platform_device *, bool);
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]77};
78
79struct uart_omap_dma {
80 u8 uart_dma_tx;
81 u8 uart_dma_rx;
82 int rx_dma_channel;
83 int tx_dma_channel;
84 dma_addr_t rx_buf_dma_phys;
85 dma_addr_t tx_buf_dma_phys;
86 unsigned int uart_base;
87 /*
88 * Buffer for rx dma.It is not required for tx because the buffer
89 * comes from port structure.
90 */
91 unsigned char *rx_buf;
92 unsigned int prev_rx_dma_pos;
93 int tx_buf_size;
94 int tx_dma_used;
95 int rx_dma_used;
96 spinlock_t tx_lock;
97 spinlock_t rx_lock;
98 /* timer to poll activity on rx dma */
99 struct timer_list rx_timer;
Deepak Kc86845db2011-11-09 17:33:38 +0530[diff] [blame^]100 unsigned int rx_buf_size;
101 unsigned int rx_timeout;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]102};
103
104struct uart_omap_port {
105 struct uart_port port;
106 struct uart_omap_dma uart_dma;
107 struct platform_device *pdev;
108
109 unsigned char ier;
110 unsigned char lcr;
111 unsigned char mcr;
112 unsigned char fcr;
113 unsigned char efr;
Govindraj.Rc538d202011-11-07 18:57:03 +0530[diff] [blame]114 unsigned char dll;
115 unsigned char dlh;
116 unsigned char mdr1;
117 unsigned char scr;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]118
119 int use_dma;
120 /*
121 * Some bits in registers are cleared on a read, so they must
122 * be saved whenever the register is read but the bits will not
123 * be immediately processed.
124 */
125 unsigned int lsr_break_flag;
126 unsigned char msr_saved_flags;
127 char name[20];
128 unsigned long port_activity;
Govindraj.Rec3bebc2011-10-11 19:11:27 +0530[diff] [blame]129 u32 context_loss_cnt;
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]130 u32 errata;
Govindraj.R62f3ec5f2011-10-13 14:11:09 +0530[diff] [blame]131 u8 wakeups_enabled;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]132};
133
134#endif /* __OMAP_SERIAL_H__ */