blob: 99d2dd979d1c7556ce108d29d3e7fb6b2e4ea133 [file] [log] [blame]
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -04001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -04003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Paul Gortmaker6eb07ca2011-09-15 19:46:05 -040017#include <linux/moduleparam.h>
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040018#include "hw.h"
19#include "ar5008_initvals.h"
20#include "ar9001_initvals.h"
21#include "ar9002_initvals.h"
Sujithe9141f72010-06-01 15:14:10 +053022#include "ar9002_phy.h"
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040023
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -040024int modparam_force_new_ani;
25module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
John W. Linville33af8812011-01-05 14:05:00 -050026MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -040027
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040028/* General hardware code for the A5008/AR9001/AR9002 hadware families */
29
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040030static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
31{
32 if (AR_SREV_9271(ah)) {
33 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020034 ARRAY_SIZE(ar9271Modes_9271), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040035 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
36 ARRAY_SIZE(ar9271Common_9271), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040037 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
38 ar9271Modes_9271_1_0_only,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020039 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040040 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020041 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040042 return;
43 }
44
Felix Fietkau14fec8d2012-02-15 21:53:16 +010045 if (ah->config.pcie_clock_req)
46 INIT_INI_ARRAY(&ah->iniPcieSerdes,
47 ar9280PciePhy_clkreq_off_L1_9280,
48 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
49 else
50 INIT_INI_ARRAY(&ah->iniPcieSerdes,
51 ar9280PciePhy_clkreq_always_on_L1_9280,
52 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
53
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040054 if (AR_SREV_9287_11_OR_LATER(ah)) {
55 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020056 ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040057 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
58 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040059 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040060 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020061 ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040062 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
63 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040064 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
65 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020066 ARRAY_SIZE(ar9280Modes_9280_2), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040067 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
68 ARRAY_SIZE(ar9280Common_9280_2), 2);
69
Felix Fietkauc7d36f92012-03-14 16:40:31 +010070 INIT_INI_ARRAY(&ah->iniModesFastClock,
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040071 ar9280Modes_fast_clock_9280_2,
72 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040073 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
74 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020075 ARRAY_SIZE(ar5416Modes_9160), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040076 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
77 ARRAY_SIZE(ar5416Common_9160), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040078 if (AR_SREV_9160_11(ah)) {
79 INIT_INI_ARRAY(&ah->iniAddac,
Felix Fietkauf504f5f2010-07-02 00:09:47 +020080 ar5416Addac_9160_1_1,
81 ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040082 } else {
83 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
84 ARRAY_SIZE(ar5416Addac_9160), 2);
85 }
86 } else if (AR_SREV_9100_OR_LATER(ah)) {
87 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020088 ARRAY_SIZE(ar5416Modes_9100), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040089 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
90 ARRAY_SIZE(ar5416Common_9100), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040091 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
92 ARRAY_SIZE(ar5416Bank6_9100), 3);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040093 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
94 ARRAY_SIZE(ar5416Addac_9100), 2);
95 } else {
96 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
Felix Fietkaub8b0b972011-08-29 13:39:46 +020097 ARRAY_SIZE(ar5416Modes), 5);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -040098 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
99 ARRAY_SIZE(ar5416Common), 2);
Felix Fietkau14fec8d2012-02-15 21:53:16 +0100100 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
101 ARRAY_SIZE(ar5416Bank6TPC), 3);
102 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
103 ARRAY_SIZE(ar5416Addac), 2);
104 }
105
106 if (!AR_SREV_9280_20_OR_LATER(ah)) {
107 /* Common for AR5416, AR913x, AR9160 */
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400108 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
109 ARRAY_SIZE(ar5416BB_RfGain), 3);
Felix Fietkau14fec8d2012-02-15 21:53:16 +0100110
111 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
112 ARRAY_SIZE(ar5416Bank0), 2);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400113 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
114 ARRAY_SIZE(ar5416Bank1), 2);
115 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
116 ARRAY_SIZE(ar5416Bank2), 2);
117 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
118 ARRAY_SIZE(ar5416Bank3), 3);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400119 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
120 ARRAY_SIZE(ar5416Bank7), 2);
Felix Fietkau14fec8d2012-02-15 21:53:16 +0100121
122 /* Common for AR5416, AR9160 */
123 if (!AR_SREV_9100(ah))
124 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
125 ARRAY_SIZE(ar5416Bank6), 3);
126
127 /* Common for AR913x, AR9160 */
128 if (!AR_SREV_5416(ah))
129 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
130 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400131 }
Felix Fietkau9bbb8162012-02-15 19:31:20 +0100132
133 /* iniAddac needs to be modified for these chips */
134 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) {
135 struct ar5416IniArray *addac = &ah->iniAddac;
136 u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
137 u32 *data;
138
139 data = kmalloc(size, GFP_KERNEL);
140 if (!data)
141 return;
142
143 memcpy(data, addac->ia_array, size);
144 addac->ia_array = data;
145
146 if (!AR_SREV_5416_22_OR_LATER(ah)) {
147 /* override CLKDRV value */
148 INI_RA(addac, 31,1) = 0;
149 }
150 }
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -0400151 if (AR_SREV_9287_11_OR_LATER(ah)) {
152 INIT_INI_ARRAY(&ah->iniCckfirNormal,
Felix Fietkauf504f5f2010-07-02 00:09:47 +0200153 ar9287Common_normal_cck_fir_coeff_9287_1_1,
154 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -0400155 2);
156 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
Felix Fietkauf504f5f2010-07-02 00:09:47 +0200157 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
158 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -0400159 2);
160 }
161}
162
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400163static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
164{
165 u32 rxgain_type;
166
167 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
168 AR5416_EEP_MINOR_VER_17) {
169 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
170
171 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
172 INIT_INI_ARRAY(&ah->iniModesRxGain,
173 ar9280Modes_backoff_13db_rxgain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200174 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400175 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
176 INIT_INI_ARRAY(&ah->iniModesRxGain,
177 ar9280Modes_backoff_23db_rxgain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200178 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400179 else
180 INIT_INI_ARRAY(&ah->iniModesRxGain,
181 ar9280Modes_original_rxgain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200182 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400183 } else {
184 INIT_INI_ARRAY(&ah->iniModesRxGain,
185 ar9280Modes_original_rxgain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200186 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400187 }
188}
189
Felix Fietkauaa0e5782012-03-14 16:40:32 +0100190static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400191{
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400192 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
193 AR5416_EEP_MINOR_VER_19) {
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400194 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
195 INIT_INI_ARRAY(&ah->iniModesTxGain,
196 ar9280Modes_high_power_tx_gain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200197 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400198 else
199 INIT_INI_ARRAY(&ah->iniModesTxGain,
200 ar9280Modes_original_tx_gain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200201 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400202 } else {
203 INIT_INI_ARRAY(&ah->iniModesTxGain,
204 ar9280Modes_original_tx_gain_9280_2,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200205 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400206 }
207}
208
Felix Fietkauaa0e5782012-03-14 16:40:32 +0100209static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
210{
211 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
212 INIT_INI_ARRAY(&ah->iniModesTxGain,
213 ar9271Modes_high_power_tx_gain_9271,
214 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
215 else
216 INIT_INI_ARRAY(&ah->iniModesTxGain,
217 ar9271Modes_normal_power_tx_gain_9271,
218 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
219}
220
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400221static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
222{
Felix Fietkauaa0e5782012-03-14 16:40:32 +0100223 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
224
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400225 if (AR_SREV_9287_11_OR_LATER(ah))
226 INIT_INI_ARRAY(&ah->iniModesRxGain,
227 ar9287Modes_rx_gain_9287_1_1,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200228 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400229 else if (AR_SREV_9280_20(ah))
230 ar9280_20_hw_init_rxgain_ini(ah);
231
Felix Fietkauaa0e5782012-03-14 16:40:32 +0100232 if (AR_SREV_9271(ah)) {
233 ar9271_hw_init_txgain_ini(ah, txgain_type);
234 } else if (AR_SREV_9287_11_OR_LATER(ah)) {
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400235 INIT_INI_ARRAY(&ah->iniModesTxGain,
236 ar9287Modes_tx_gain_9287_1_1,
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200237 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400238 } else if (AR_SREV_9280_20(ah)) {
Felix Fietkauaa0e5782012-03-14 16:40:32 +0100239 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400240 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400241 /* txgain table */
242 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
243 if (AR_SREV_9285E_20(ah)) {
244 INIT_INI_ARRAY(&ah->iniModesTxGain,
245 ar9285Modes_XE2_0_high_power,
246 ARRAY_SIZE(
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200247 ar9285Modes_XE2_0_high_power), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400248 } else {
249 INIT_INI_ARRAY(&ah->iniModesTxGain,
250 ar9285Modes_high_power_tx_gain_9285_1_2,
251 ARRAY_SIZE(
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200252 ar9285Modes_high_power_tx_gain_9285_1_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400253 }
254 } else {
255 if (AR_SREV_9285E_20(ah)) {
256 INIT_INI_ARRAY(&ah->iniModesTxGain,
257 ar9285Modes_XE2_0_normal_power,
258 ARRAY_SIZE(
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200259 ar9285Modes_XE2_0_normal_power), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400260 } else {
261 INIT_INI_ARRAY(&ah->iniModesTxGain,
262 ar9285Modes_original_tx_gain_9285_1_2,
263 ARRAY_SIZE(
Felix Fietkaub8b0b972011-08-29 13:39:46 +0200264 ar9285Modes_original_tx_gain_9285_1_2), 5);
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400265 }
266 }
267 }
268}
269
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400270/*
271 * Helper for ASPM support.
272 *
273 * Disable PLL when in L0s as well as receiver clock when in L1.
274 * This power saving option must be enabled through the SerDes.
275 *
276 * Programming the SerDes must go through the same 288 bit serial shift
277 * register as the other analog registers. Hence the 9 writes.
278 */
279static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
Stanislaw Gruszka84c87dc2011-08-05 13:10:32 +0200280 bool power_off)
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400281{
282 u8 i;
283 u32 val;
284
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400285 /* Nothing to do on restore for 11N */
Stanislaw Gruszka84c87dc2011-08-05 13:10:32 +0200286 if (!power_off /* !restore */) {
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400287 if (AR_SREV_9280_20_OR_LATER(ah)) {
288 /*
289 * AR9280 2.0 or later chips use SerDes values from the
290 * initvals.h initialized depending on chipset during
291 * __ath9k_hw_init()
292 */
293 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
294 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
295 INI_RA(&ah->iniPcieSerdes, i, 1));
296 }
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400297 } else {
Sujithd5e347b2010-04-23 10:28:11 +0530298 ENABLE_REGWRITE_BUFFER(ah);
299
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400300 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
301 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
302
303 /* RX shut off when elecidle is asserted */
304 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
305 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
306 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
307
308 /*
309 * Ignore ah->ah_config.pcie_clock_req setting for
310 * pre-AR9280 11n
311 */
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
313
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
317
318 /* Load the new settings */
319 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
Sujithd5e347b2010-04-23 10:28:11 +0530320
321 REGWRITE_BUFFER_FLUSH(ah);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400322 }
323
324 udelay(1000);
Sujith15ae7332010-06-01 15:14:09 +0530325 }
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400326
Sujith15ae7332010-06-01 15:14:09 +0530327 if (power_off) {
328 /* clear bit 19 to disable L1 */
329 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400330
Sujith15ae7332010-06-01 15:14:09 +0530331 val = REG_READ(ah, AR_WA);
332
333 /*
334 * Set PCIe workaround bits
335 * In AR9280 and AR9285, bit 14 in WA register (disable L1)
336 * should only be set when device enters D3 and be
337 * cleared when device comes back to D0.
338 */
339 if (ah->config.pcie_waen) {
340 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
341 val |= AR_WA_D3_L1_DISABLE;
342 } else {
343 if (((AR_SREV_9285(ah) ||
344 AR_SREV_9271(ah) ||
345 AR_SREV_9287(ah)) &&
346 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
347 (AR_SREV_9280(ah) &&
348 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
349 val |= AR_WA_D3_L1_DISABLE;
350 }
351 }
352
353 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
354 /*
355 * Disable bit 6 and 7 before entering D3 to
356 * prevent system hang.
357 */
358 val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
359 }
360
Vasanthakumar Thiagarajanf119da32010-11-04 17:41:25 -0700361 if (AR_SREV_9280(ah))
362 val |= AR_WA_BIT22;
363
Sujith15ae7332010-06-01 15:14:09 +0530364 if (AR_SREV_9285E_20(ah))
365 val |= AR_WA_BIT23;
366
367 REG_WRITE(ah, AR_WA, val);
368 } else {
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400369 if (ah->config.pcie_waen) {
370 val = ah->config.pcie_waen;
371 if (!power_off)
372 val &= (~AR_WA_D3_L1_DISABLE);
373 } else {
Sujith15ae7332010-06-01 15:14:09 +0530374 if (AR_SREV_9285(ah) ||
375 AR_SREV_9271(ah) ||
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400376 AR_SREV_9287(ah)) {
377 val = AR9285_WA_DEFAULT;
378 if (!power_off)
379 val &= (~AR_WA_D3_L1_DISABLE);
Sujith15ae7332010-06-01 15:14:09 +0530380 }
381 else if (AR_SREV_9280(ah)) {
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400382 /*
Sujith15ae7332010-06-01 15:14:09 +0530383 * For AR9280 chips, bit 22 of 0x4004
384 * needs to be set.
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400385 */
386 val = AR9280_WA_DEFAULT;
387 if (!power_off)
388 val &= (~AR_WA_D3_L1_DISABLE);
Sujith15ae7332010-06-01 15:14:09 +0530389 } else {
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400390 val = AR_WA_DEFAULT;
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400391 }
392 }
Sujith15ae7332010-06-01 15:14:09 +0530393
394 /* WAR for ASPM system hang */
Rajkumar Manoharan5b64aa72011-01-27 18:39:37 +0530395 if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
Sujith15ae7332010-06-01 15:14:09 +0530396 val |= (AR_WA_BIT6 | AR_WA_BIT7);
Sujith15ae7332010-06-01 15:14:09 +0530397
398 if (AR_SREV_9285E_20(ah))
399 val |= AR_WA_BIT23;
400
401 REG_WRITE(ah, AR_WA, val);
402
403 /* set bit 19 to allow forcing of pcie core into L1 state */
404 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400405 }
406}
407
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400408static int ar9002_hw_get_radiorev(struct ath_hw *ah)
409{
410 u32 val;
411 int i;
412
Sujith7d0d0df2010-04-16 11:53:57 +0530413 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400414
Sujith7d0d0df2010-04-16 11:53:57 +0530415 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400416 for (i = 0; i < 8; i++)
417 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
Sujith7d0d0df2010-04-16 11:53:57 +0530418
419 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530420
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400421 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
422 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
423
424 return ath9k_hw_reverse_bits(val, 8);
425}
426
427int ar9002_hw_rf_claim(struct ath_hw *ah)
428{
429 u32 val;
430
431 REG_WRITE(ah, AR_PHY(0), 0x00000007);
432
433 val = ar9002_hw_get_radiorev(ah);
434 switch (val & AR_RADIO_SREV_MAJOR) {
435 case 0:
436 val = AR_RAD5133_SREV_MAJOR;
437 break;
438 case AR_RAD5133_SREV_MAJOR:
439 case AR_RAD5122_SREV_MAJOR:
440 case AR_RAD2133_SREV_MAJOR:
441 case AR_RAD2122_SREV_MAJOR:
442 break;
443 default:
Joe Perches38002762010-12-02 19:12:36 -0800444 ath_err(ath9k_hw_common(ah),
445 "Radio Chip Rev 0x%02X not supported\n",
446 val & AR_RADIO_SREV_MAJOR);
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400447 return -EOPNOTSUPP;
448 }
449
450 ah->hw_version.analog5GhzRev = val;
451
452 return 0;
453}
454
Sujithe9141f72010-06-01 15:14:10 +0530455void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
456{
457 if (AR_SREV_9287_13_OR_LATER(ah)) {
458 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
459 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
460 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
461 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
462 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
463 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
464 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
465 }
466}
467
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400468/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
469void ar9002_hw_attach_ops(struct ath_hw *ah)
470{
471 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
472 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
473
474 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400475 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400476
477 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
478
479 ar5008_hw_attach_phy_ops(ah);
Felix Fietkau7a370812010-09-22 12:34:52 +0200480 if (AR_SREV_9280_20_OR_LATER(ah))
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400481 ar9002_hw_attach_phy_ops(ah);
482
483 ar9002_hw_attach_calib_ops(ah);
484 ar9002_hw_attach_mac_ops(ah);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -0400485}
Rajkumar Manoharanc2ba3342010-09-03 16:00:00 +0530486
487void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
488{
489 u32 modesIndex;
490 int i;
491
492 switch (chan->chanmode) {
493 case CHANNEL_A:
494 case CHANNEL_A_HT20:
495 modesIndex = 1;
496 break;
497 case CHANNEL_A_HT40PLUS:
498 case CHANNEL_A_HT40MINUS:
499 modesIndex = 2;
500 break;
501 case CHANNEL_G:
502 case CHANNEL_G_HT20:
503 case CHANNEL_B:
504 modesIndex = 4;
505 break;
506 case CHANNEL_G_HT40PLUS:
507 case CHANNEL_G_HT40MINUS:
508 modesIndex = 3;
509 break;
510
511 default:
512 return;
513 }
514
515 ENABLE_REGWRITE_BUFFER(ah);
516
517 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
518 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
519 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
520 u32 val_orig;
521
522 if (reg == AR_PHY_CCK_DETECT) {
523 val_orig = REG_READ(ah, reg);
524 val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
525 val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
526
527 REG_WRITE(ah, reg, val|val_orig);
528 } else
529 REG_WRITE(ah, reg, val);
530 }
531
532 REGWRITE_BUFFER_FLUSH(ah);
Rajkumar Manoharanc2ba3342010-09-03 16:00:00 +0530533}