Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
Paul Gortmaker | 6eb07ca | 2011-09-15 19:46:05 -0400 | [diff] [blame] | 17 | #include <linux/moduleparam.h> |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 18 | #include "hw.h" |
| 19 | #include "ar5008_initvals.h" |
| 20 | #include "ar9001_initvals.h" |
| 21 | #include "ar9002_initvals.h" |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 22 | #include "ar9002_phy.h" |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 23 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 24 | int modparam_force_new_ani; |
| 25 | module_param_named(force_new_ani, modparam_force_new_ani, int, 0444); |
John W. Linville | 33af881 | 2011-01-05 14:05:00 -0500 | [diff] [blame] | 26 | MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002"); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 27 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 28 | /* General hardware code for the A5008/AR9001/AR9002 hadware families */ |
| 29 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 30 | static void ar9002_hw_init_mode_regs(struct ath_hw *ah) |
| 31 | { |
| 32 | if (AR_SREV_9271(ah)) { |
| 33 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 34 | ARRAY_SIZE(ar9271Modes_9271), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 35 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, |
| 36 | ARRAY_SIZE(ar9271Common_9271), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 37 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
| 38 | ar9271Modes_9271_1_0_only, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 39 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 40 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 41 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 42 | return; |
| 43 | } |
| 44 | |
Felix Fietkau | 14fec8d | 2012-02-15 21:53:16 +0100 | [diff] [blame] | 45 | if (ah->config.pcie_clock_req) |
| 46 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 47 | ar9280PciePhy_clkreq_off_L1_9280, |
| 48 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2); |
| 49 | else |
| 50 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 51 | ar9280PciePhy_clkreq_always_on_L1_9280, |
| 52 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); |
| 53 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 54 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 55 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 56 | ARRAY_SIZE(ar9287Modes_9287_1_1), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 57 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, |
| 58 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 59 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 60 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 61 | ARRAY_SIZE(ar9285Modes_9285_1_2), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 62 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
| 63 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 64 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 65 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 66 | ARRAY_SIZE(ar9280Modes_9280_2), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 67 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
| 68 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
| 69 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 70 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 71 | ar9280Modes_fast_clock_9280_2, |
| 72 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 73 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 74 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 75 | ARRAY_SIZE(ar5416Modes_9160), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 76 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
| 77 | ARRAY_SIZE(ar5416Common_9160), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 78 | if (AR_SREV_9160_11(ah)) { |
| 79 | INIT_INI_ARRAY(&ah->iniAddac, |
Felix Fietkau | f504f5f | 2010-07-02 00:09:47 +0200 | [diff] [blame] | 80 | ar5416Addac_9160_1_1, |
| 81 | ARRAY_SIZE(ar5416Addac_9160_1_1), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 82 | } else { |
| 83 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
| 84 | ARRAY_SIZE(ar5416Addac_9160), 2); |
| 85 | } |
| 86 | } else if (AR_SREV_9100_OR_LATER(ah)) { |
| 87 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 88 | ARRAY_SIZE(ar5416Modes_9100), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 89 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
| 90 | ARRAY_SIZE(ar5416Common_9100), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 91 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
| 92 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 93 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
| 94 | ARRAY_SIZE(ar5416Addac_9100), 2); |
| 95 | } else { |
| 96 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 97 | ARRAY_SIZE(ar5416Modes), 5); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 98 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
| 99 | ARRAY_SIZE(ar5416Common), 2); |
Felix Fietkau | 14fec8d | 2012-02-15 21:53:16 +0100 | [diff] [blame] | 100 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
| 101 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
| 102 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
| 103 | ARRAY_SIZE(ar5416Addac), 2); |
| 104 | } |
| 105 | |
| 106 | if (!AR_SREV_9280_20_OR_LATER(ah)) { |
| 107 | /* Common for AR5416, AR913x, AR9160 */ |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 108 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
| 109 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
Felix Fietkau | 14fec8d | 2012-02-15 21:53:16 +0100 | [diff] [blame] | 110 | |
| 111 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
| 112 | ARRAY_SIZE(ar5416Bank0), 2); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 113 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
| 114 | ARRAY_SIZE(ar5416Bank1), 2); |
| 115 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
| 116 | ARRAY_SIZE(ar5416Bank2), 2); |
| 117 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
| 118 | ARRAY_SIZE(ar5416Bank3), 3); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 119 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
| 120 | ARRAY_SIZE(ar5416Bank7), 2); |
Felix Fietkau | 14fec8d | 2012-02-15 21:53:16 +0100 | [diff] [blame] | 121 | |
| 122 | /* Common for AR5416, AR9160 */ |
| 123 | if (!AR_SREV_9100(ah)) |
| 124 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
| 125 | ARRAY_SIZE(ar5416Bank6), 3); |
| 126 | |
| 127 | /* Common for AR913x, AR9160 */ |
| 128 | if (!AR_SREV_5416(ah)) |
| 129 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
| 130 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 131 | } |
Felix Fietkau | 9bbb816 | 2012-02-15 19:31:20 +0100 | [diff] [blame] | 132 | |
| 133 | /* iniAddac needs to be modified for these chips */ |
| 134 | if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { |
| 135 | struct ar5416IniArray *addac = &ah->iniAddac; |
| 136 | u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns; |
| 137 | u32 *data; |
| 138 | |
| 139 | data = kmalloc(size, GFP_KERNEL); |
| 140 | if (!data) |
| 141 | return; |
| 142 | |
| 143 | memcpy(data, addac->ia_array, size); |
| 144 | addac->ia_array = data; |
| 145 | |
| 146 | if (!AR_SREV_5416_22_OR_LATER(ah)) { |
| 147 | /* override CLKDRV value */ |
| 148 | INI_RA(addac, 31,1) = 0; |
| 149 | } |
| 150 | } |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 151 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 152 | INIT_INI_ARRAY(&ah->iniCckfirNormal, |
Felix Fietkau | f504f5f | 2010-07-02 00:09:47 +0200 | [diff] [blame] | 153 | ar9287Common_normal_cck_fir_coeff_9287_1_1, |
| 154 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1), |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 155 | 2); |
| 156 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
Felix Fietkau | f504f5f | 2010-07-02 00:09:47 +0200 | [diff] [blame] | 157 | ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, |
| 158 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1), |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 159 | 2); |
| 160 | } |
| 161 | } |
| 162 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 163 | static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) |
| 164 | { |
| 165 | u32 rxgain_type; |
| 166 | |
| 167 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= |
| 168 | AR5416_EEP_MINOR_VER_17) { |
| 169 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); |
| 170 | |
| 171 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) |
| 172 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 173 | ar9280Modes_backoff_13db_rxgain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 174 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 175 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) |
| 176 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 177 | ar9280Modes_backoff_23db_rxgain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 178 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 179 | else |
| 180 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 181 | ar9280Modes_original_rxgain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 182 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 183 | } else { |
| 184 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 185 | ar9280Modes_original_rxgain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 186 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 187 | } |
| 188 | } |
| 189 | |
Felix Fietkau | aa0e578 | 2012-03-14 16:40:32 +0100 | [diff] [blame^] | 190 | static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 191 | { |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 192 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= |
| 193 | AR5416_EEP_MINOR_VER_19) { |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 194 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
| 195 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 196 | ar9280Modes_high_power_tx_gain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 197 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 198 | else |
| 199 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 200 | ar9280Modes_original_tx_gain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 201 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 202 | } else { |
| 203 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 204 | ar9280Modes_original_tx_gain_9280_2, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 205 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 206 | } |
| 207 | } |
| 208 | |
Felix Fietkau | aa0e578 | 2012-03-14 16:40:32 +0100 | [diff] [blame^] | 209 | static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) |
| 210 | { |
| 211 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
| 212 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 213 | ar9271Modes_high_power_tx_gain_9271, |
| 214 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5); |
| 215 | else |
| 216 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 217 | ar9271Modes_normal_power_tx_gain_9271, |
| 218 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5); |
| 219 | } |
| 220 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 221 | static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 222 | { |
Felix Fietkau | aa0e578 | 2012-03-14 16:40:32 +0100 | [diff] [blame^] | 223 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
| 224 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 225 | if (AR_SREV_9287_11_OR_LATER(ah)) |
| 226 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 227 | ar9287Modes_rx_gain_9287_1_1, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 228 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 229 | else if (AR_SREV_9280_20(ah)) |
| 230 | ar9280_20_hw_init_rxgain_ini(ah); |
| 231 | |
Felix Fietkau | aa0e578 | 2012-03-14 16:40:32 +0100 | [diff] [blame^] | 232 | if (AR_SREV_9271(ah)) { |
| 233 | ar9271_hw_init_txgain_ini(ah, txgain_type); |
| 234 | } else if (AR_SREV_9287_11_OR_LATER(ah)) { |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 235 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 236 | ar9287Modes_tx_gain_9287_1_1, |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 237 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 238 | } else if (AR_SREV_9280_20(ah)) { |
Felix Fietkau | aa0e578 | 2012-03-14 16:40:32 +0100 | [diff] [blame^] | 239 | ar9280_20_hw_init_txgain_ini(ah, txgain_type); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 240 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 241 | /* txgain table */ |
| 242 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { |
| 243 | if (AR_SREV_9285E_20(ah)) { |
| 244 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 245 | ar9285Modes_XE2_0_high_power, |
| 246 | ARRAY_SIZE( |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 247 | ar9285Modes_XE2_0_high_power), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 248 | } else { |
| 249 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 250 | ar9285Modes_high_power_tx_gain_9285_1_2, |
| 251 | ARRAY_SIZE( |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 252 | ar9285Modes_high_power_tx_gain_9285_1_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 253 | } |
| 254 | } else { |
| 255 | if (AR_SREV_9285E_20(ah)) { |
| 256 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 257 | ar9285Modes_XE2_0_normal_power, |
| 258 | ARRAY_SIZE( |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 259 | ar9285Modes_XE2_0_normal_power), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 260 | } else { |
| 261 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 262 | ar9285Modes_original_tx_gain_9285_1_2, |
| 263 | ARRAY_SIZE( |
Felix Fietkau | b8b0b97 | 2011-08-29 13:39:46 +0200 | [diff] [blame] | 264 | ar9285Modes_original_tx_gain_9285_1_2), 5); |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 265 | } |
| 266 | } |
| 267 | } |
| 268 | } |
| 269 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 270 | /* |
| 271 | * Helper for ASPM support. |
| 272 | * |
| 273 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 274 | * This power saving option must be enabled through the SerDes. |
| 275 | * |
| 276 | * Programming the SerDes must go through the same 288 bit serial shift |
| 277 | * register as the other analog registers. Hence the 9 writes. |
| 278 | */ |
| 279 | static void ar9002_hw_configpcipowersave(struct ath_hw *ah, |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 280 | bool power_off) |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 281 | { |
| 282 | u8 i; |
| 283 | u32 val; |
| 284 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 285 | /* Nothing to do on restore for 11N */ |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 286 | if (!power_off /* !restore */) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 287 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 288 | /* |
| 289 | * AR9280 2.0 or later chips use SerDes values from the |
| 290 | * initvals.h initialized depending on chipset during |
| 291 | * __ath9k_hw_init() |
| 292 | */ |
| 293 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
| 294 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), |
| 295 | INI_RA(&ah->iniPcieSerdes, i, 1)); |
| 296 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 297 | } else { |
Sujith | d5e347b | 2010-04-23 10:28:11 +0530 | [diff] [blame] | 298 | ENABLE_REGWRITE_BUFFER(ah); |
| 299 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 300 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 301 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 302 | |
| 303 | /* RX shut off when elecidle is asserted */ |
| 304 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
| 305 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); |
| 306 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); |
| 307 | |
| 308 | /* |
| 309 | * Ignore ah->ah_config.pcie_clock_req setting for |
| 310 | * pre-AR9280 11n |
| 311 | */ |
| 312 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); |
| 313 | |
| 314 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 315 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 316 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); |
| 317 | |
| 318 | /* Load the new settings */ |
| 319 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
Sujith | d5e347b | 2010-04-23 10:28:11 +0530 | [diff] [blame] | 320 | |
| 321 | REGWRITE_BUFFER_FLUSH(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | udelay(1000); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 325 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 326 | |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 327 | if (power_off) { |
| 328 | /* clear bit 19 to disable L1 */ |
| 329 | REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 330 | |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 331 | val = REG_READ(ah, AR_WA); |
| 332 | |
| 333 | /* |
| 334 | * Set PCIe workaround bits |
| 335 | * In AR9280 and AR9285, bit 14 in WA register (disable L1) |
| 336 | * should only be set when device enters D3 and be |
| 337 | * cleared when device comes back to D0. |
| 338 | */ |
| 339 | if (ah->config.pcie_waen) { |
| 340 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) |
| 341 | val |= AR_WA_D3_L1_DISABLE; |
| 342 | } else { |
| 343 | if (((AR_SREV_9285(ah) || |
| 344 | AR_SREV_9271(ah) || |
| 345 | AR_SREV_9287(ah)) && |
| 346 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || |
| 347 | (AR_SREV_9280(ah) && |
| 348 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { |
| 349 | val |= AR_WA_D3_L1_DISABLE; |
| 350 | } |
| 351 | } |
| 352 | |
| 353 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { |
| 354 | /* |
| 355 | * Disable bit 6 and 7 before entering D3 to |
| 356 | * prevent system hang. |
| 357 | */ |
| 358 | val &= ~(AR_WA_BIT6 | AR_WA_BIT7); |
| 359 | } |
| 360 | |
Vasanthakumar Thiagarajan | f119da3 | 2010-11-04 17:41:25 -0700 | [diff] [blame] | 361 | if (AR_SREV_9280(ah)) |
| 362 | val |= AR_WA_BIT22; |
| 363 | |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 364 | if (AR_SREV_9285E_20(ah)) |
| 365 | val |= AR_WA_BIT23; |
| 366 | |
| 367 | REG_WRITE(ah, AR_WA, val); |
| 368 | } else { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 369 | if (ah->config.pcie_waen) { |
| 370 | val = ah->config.pcie_waen; |
| 371 | if (!power_off) |
| 372 | val &= (~AR_WA_D3_L1_DISABLE); |
| 373 | } else { |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 374 | if (AR_SREV_9285(ah) || |
| 375 | AR_SREV_9271(ah) || |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 376 | AR_SREV_9287(ah)) { |
| 377 | val = AR9285_WA_DEFAULT; |
| 378 | if (!power_off) |
| 379 | val &= (~AR_WA_D3_L1_DISABLE); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 380 | } |
| 381 | else if (AR_SREV_9280(ah)) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 382 | /* |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 383 | * For AR9280 chips, bit 22 of 0x4004 |
| 384 | * needs to be set. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 385 | */ |
| 386 | val = AR9280_WA_DEFAULT; |
| 387 | if (!power_off) |
| 388 | val &= (~AR_WA_D3_L1_DISABLE); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 389 | } else { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 390 | val = AR_WA_DEFAULT; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 391 | } |
| 392 | } |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 393 | |
| 394 | /* WAR for ASPM system hang */ |
Rajkumar Manoharan | 5b64aa7 | 2011-01-27 18:39:37 +0530 | [diff] [blame] | 395 | if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 396 | val |= (AR_WA_BIT6 | AR_WA_BIT7); |
Sujith | 15ae733 | 2010-06-01 15:14:09 +0530 | [diff] [blame] | 397 | |
| 398 | if (AR_SREV_9285E_20(ah)) |
| 399 | val |= AR_WA_BIT23; |
| 400 | |
| 401 | REG_WRITE(ah, AR_WA, val); |
| 402 | |
| 403 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 404 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 405 | } |
| 406 | } |
| 407 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 408 | static int ar9002_hw_get_radiorev(struct ath_hw *ah) |
| 409 | { |
| 410 | u32 val; |
| 411 | int i; |
| 412 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 413 | ENABLE_REGWRITE_BUFFER(ah); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 414 | |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 415 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 416 | for (i = 0; i < 8; i++) |
| 417 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 418 | |
| 419 | REGWRITE_BUFFER_FLUSH(ah); |
Sujith | 7d0d0df | 2010-04-16 11:53:57 +0530 | [diff] [blame] | 420 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 421 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; |
| 422 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); |
| 423 | |
| 424 | return ath9k_hw_reverse_bits(val, 8); |
| 425 | } |
| 426 | |
| 427 | int ar9002_hw_rf_claim(struct ath_hw *ah) |
| 428 | { |
| 429 | u32 val; |
| 430 | |
| 431 | REG_WRITE(ah, AR_PHY(0), 0x00000007); |
| 432 | |
| 433 | val = ar9002_hw_get_radiorev(ah); |
| 434 | switch (val & AR_RADIO_SREV_MAJOR) { |
| 435 | case 0: |
| 436 | val = AR_RAD5133_SREV_MAJOR; |
| 437 | break; |
| 438 | case AR_RAD5133_SREV_MAJOR: |
| 439 | case AR_RAD5122_SREV_MAJOR: |
| 440 | case AR_RAD2133_SREV_MAJOR: |
| 441 | case AR_RAD2122_SREV_MAJOR: |
| 442 | break; |
| 443 | default: |
Joe Perches | 3800276 | 2010-12-02 19:12:36 -0800 | [diff] [blame] | 444 | ath_err(ath9k_hw_common(ah), |
| 445 | "Radio Chip Rev 0x%02X not supported\n", |
| 446 | val & AR_RADIO_SREV_MAJOR); |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 447 | return -EOPNOTSUPP; |
| 448 | } |
| 449 | |
| 450 | ah->hw_version.analog5GhzRev = val; |
| 451 | |
| 452 | return 0; |
| 453 | } |
| 454 | |
Sujith | e9141f7 | 2010-06-01 15:14:10 +0530 | [diff] [blame] | 455 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah) |
| 456 | { |
| 457 | if (AR_SREV_9287_13_OR_LATER(ah)) { |
| 458 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 459 | AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); |
| 460 | REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); |
| 461 | REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 462 | AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
| 463 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
| 464 | AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
| 465 | } |
| 466 | } |
| 467 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 468 | /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ |
| 469 | void ar9002_hw_attach_ops(struct ath_hw *ah) |
| 470 | { |
| 471 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 472 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 473 | |
| 474 | priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 475 | priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 476 | |
| 477 | ops->config_pci_powersave = ar9002_hw_configpcipowersave; |
| 478 | |
| 479 | ar5008_hw_attach_phy_ops(ah); |
Felix Fietkau | 7a37081 | 2010-09-22 12:34:52 +0200 | [diff] [blame] | 480 | if (AR_SREV_9280_20_OR_LATER(ah)) |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 481 | ar9002_hw_attach_phy_ops(ah); |
| 482 | |
| 483 | ar9002_hw_attach_calib_ops(ah); |
| 484 | ar9002_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 485 | } |
Rajkumar Manoharan | c2ba334 | 2010-09-03 16:00:00 +0530 | [diff] [blame] | 486 | |
| 487 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) |
| 488 | { |
| 489 | u32 modesIndex; |
| 490 | int i; |
| 491 | |
| 492 | switch (chan->chanmode) { |
| 493 | case CHANNEL_A: |
| 494 | case CHANNEL_A_HT20: |
| 495 | modesIndex = 1; |
| 496 | break; |
| 497 | case CHANNEL_A_HT40PLUS: |
| 498 | case CHANNEL_A_HT40MINUS: |
| 499 | modesIndex = 2; |
| 500 | break; |
| 501 | case CHANNEL_G: |
| 502 | case CHANNEL_G_HT20: |
| 503 | case CHANNEL_B: |
| 504 | modesIndex = 4; |
| 505 | break; |
| 506 | case CHANNEL_G_HT40PLUS: |
| 507 | case CHANNEL_G_HT40MINUS: |
| 508 | modesIndex = 3; |
| 509 | break; |
| 510 | |
| 511 | default: |
| 512 | return; |
| 513 | } |
| 514 | |
| 515 | ENABLE_REGWRITE_BUFFER(ah); |
| 516 | |
| 517 | for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { |
| 518 | u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); |
| 519 | u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); |
| 520 | u32 val_orig; |
| 521 | |
| 522 | if (reg == AR_PHY_CCK_DETECT) { |
| 523 | val_orig = REG_READ(ah, reg); |
| 524 | val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; |
| 525 | val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; |
| 526 | |
| 527 | REG_WRITE(ah, reg, val|val_orig); |
| 528 | } else |
| 529 | REG_WRITE(ah, reg, val); |
| 530 | } |
| 531 | |
| 532 | REGWRITE_BUFFER_FLUSH(ah); |
Rajkumar Manoharan | c2ba334 | 2010-09-03 16:00:00 +0530 | [diff] [blame] | 533 | } |