blob: a5498dce1cb5fe5693e64aa6757c5d08add213c5 [file] [log] [blame]
Will Newtonf95f3852011-01-02 01:11:59 -05001/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Robert P. J. Day100e9182011-05-27 16:04:03 -040014#ifndef LINUX_MMC_DW_MMC_H
15#define LINUX_MMC_DW_MMC_H
Will Newtonf95f3852011-01-02 01:11:59 -050016
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +090017#include <linux/scatterlist.h>
18
Will Newtonf95f3852011-01-02 01:11:59 -050019#define MAX_MCI_SLOTS 2
20
21enum dw_mci_state {
22 STATE_IDLE = 0,
23 STATE_SENDING_CMD,
24 STATE_SENDING_DATA,
25 STATE_DATA_BUSY,
26 STATE_SENDING_STOP,
27 STATE_DATA_ERROR,
28};
29
30enum {
31 EVENT_CMD_COMPLETE = 0,
32 EVENT_XFER_COMPLETE,
33 EVENT_DATA_COMPLETE,
34 EVENT_DATA_ERROR,
35 EVENT_XFER_ERROR
36};
37
38struct mmc_data;
39
40/**
41 * struct dw_mci - MMC controller state shared between all slots
42 * @lock: Spinlock protecting the queue and associated data.
43 * @regs: Pointer to MMIO registers.
44 * @sg: Scatterlist entry currently being processed by PIO code, if any.
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +090045 * @sg_miter: PIO mapping scatterlist iterator.
Will Newtonf95f3852011-01-02 01:11:59 -050046 * @cur_slot: The slot which is currently using the controller.
47 * @mrq: The request currently being processed on @cur_slot,
48 * or NULL if the controller is idle.
49 * @cmd: The command currently being sent to the card, or NULL.
50 * @data: The data currently being transferred, or NULL if no data
51 * transfer is in progress.
52 * @use_dma: Whether DMA channel is initialized or not.
James Hogan03e8cb52011-06-29 09:28:43 +010053 * @using_dma: Whether DMA is in use for the current transfer.
Will Newtonf95f3852011-01-02 01:11:59 -050054 * @sg_dma: Bus address of DMA buffer.
55 * @sg_cpu: Virtual address of DMA buffer.
56 * @dma_ops: Pointer to platform-specific DMA callbacks.
57 * @cmd_status: Snapshot of SR taken upon completion of the current
58 * command. Only valid when EVENT_CMD_COMPLETE is pending.
59 * @data_status: Snapshot of SR taken upon completion of the current
60 * data transfer. Only valid when EVENT_DATA_COMPLETE or
61 * EVENT_DATA_ERROR is pending.
62 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
63 * to be sent.
64 * @dir_status: Direction of current transfer.
65 * @tasklet: Tasklet running the request state machine.
66 * @card_tasklet: Tasklet handling card detect.
67 * @pending_events: Bitmask of events flagged by the interrupt handler
68 * to be processed by the tasklet.
69 * @completed_events: Bitmask of events which the state machine has
70 * processed.
71 * @state: Tasklet state.
72 * @queue: List of slots waiting for access to the controller.
73 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
74 * rate and timeout calculations.
75 * @current_speed: Configured rate of the controller.
76 * @num_slots: Number of slots available.
Jaehoon Chung4e0a5ad2011-10-17 19:36:23 +090077 * @verid: Denote Version ID.
78 * @data_offset: Set the offset of DATA register according to VERID.
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +053079 * @dev: Device associated with the MMC controller.
Will Newtonf95f3852011-01-02 01:11:59 -050080 * @pdata: Platform data associated with the MMC controller.
Thomas Abraham800d78b2012-09-17 18:16:42 +000081 * @drv_data: Driver specific data for identified variant of the controller
82 * @priv: Implementation defined private data.
Thomas Abrahamf90a0612012-09-17 18:16:38 +000083 * @biu_clk: Pointer to bus interface unit clock instance.
84 * @ciu_clk: Pointer to card interface unit clock instance.
Will Newtonf95f3852011-01-02 01:11:59 -050085 * @slot: Slots sharing this MMC controller.
James Hoganb86d8252011-06-24 13:57:18 +010086 * @fifo_depth: depth of FIFO.
Will Newtonf95f3852011-01-02 01:11:59 -050087 * @data_shift: log2 of FIFO item size.
James Hogan34b664a2011-06-24 13:57:56 +010088 * @part_buf_start: Start index in part_buf.
89 * @part_buf_count: Bytes of partial data in part_buf.
90 * @part_buf: Simple buffer for partial fifo reads/writes.
Will Newtonf95f3852011-01-02 01:11:59 -050091 * @push_data: Pointer to FIFO push function.
92 * @pull_data: Pointer to FIFO pull function.
93 * @quirks: Set of quirks that apply to specific versions of the IP.
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +053094 * @irq_flags: The flags to be passed to request_irq.
95 * @irq: The irq value to be passed to request_irq.
Will Newtonf95f3852011-01-02 01:11:59 -050096 *
97 * Locking
98 * =======
99 *
100 * @lock is a softirq-safe spinlock protecting @queue as well as
101 * @cur_slot, @mrq and @state. These must always be updated
102 * at the same time while holding @lock.
103 *
104 * The @mrq field of struct dw_mci_slot is also protected by @lock,
105 * and must always be written at the same time as the slot is added to
106 * @queue.
107 *
108 * @pending_events and @completed_events are accessed using atomic bit
109 * operations, so they don't need any locking.
110 *
111 * None of the fields touched by the interrupt handler need any
112 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
113 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
114 * interrupts must be disabled and @data_status updated with a
115 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300116 * CMDRDY interrupt must be disabled and @cmd_status updated with a
Will Newtonf95f3852011-01-02 01:11:59 -0500117 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
118 * bytes_xfered field of @data must be written. This is ensured by
119 * using barriers.
120 */
121struct dw_mci {
122 spinlock_t lock;
123 void __iomem *regs;
124
125 struct scatterlist *sg;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +0900126 struct sg_mapping_iter sg_miter;
Will Newtonf95f3852011-01-02 01:11:59 -0500127
128 struct dw_mci_slot *cur_slot;
129 struct mmc_request *mrq;
130 struct mmc_command *cmd;
131 struct mmc_data *data;
Thomas Abraham95dcc2c2012-05-01 14:57:36 -0700132 struct workqueue_struct *card_workqueue;
Will Newtonf95f3852011-01-02 01:11:59 -0500133
134 /* DMA interface members*/
135 int use_dma;
James Hogan03e8cb52011-06-29 09:28:43 +0100136 int using_dma;
Will Newtonf95f3852011-01-02 01:11:59 -0500137
138 dma_addr_t sg_dma;
139 void *sg_cpu;
Arnd Bergmann8e2b36e2012-11-06 22:55:31 +0100140 const struct dw_mci_dma_ops *dma_ops;
Will Newtonf95f3852011-01-02 01:11:59 -0500141#ifdef CONFIG_MMC_DW_IDMAC
142 unsigned int ring_size;
143#else
144 struct dw_mci_dma_data *dma_data;
145#endif
146 u32 cmd_status;
147 u32 data_status;
148 u32 stop_cmdr;
149 u32 dir_status;
150 struct tasklet_struct tasklet;
James Hogan1791b13e2011-06-24 13:55:55 +0100151 struct work_struct card_work;
Will Newtonf95f3852011-01-02 01:11:59 -0500152 unsigned long pending_events;
153 unsigned long completed_events;
154 enum dw_mci_state state;
155 struct list_head queue;
156
157 u32 bus_hz;
158 u32 current_speed;
159 u32 num_slots;
Jaehoon Chunge61cf112011-03-17 20:32:33 +0900160 u32 fifoth_val;
Jaehoon Chung4e0a5ad2011-10-17 19:36:23 +0900161 u16 verid;
162 u16 data_offset;
Thomas Abraham4a909202012-09-17 18:16:35 +0000163 struct device *dev;
Will Newtonf95f3852011-01-02 01:11:59 -0500164 struct dw_mci_board *pdata;
Arnd Bergmann8e2b36e2012-11-06 22:55:31 +0100165 const struct dw_mci_drv_data *drv_data;
Thomas Abraham800d78b2012-09-17 18:16:42 +0000166 void *priv;
Thomas Abrahamf90a0612012-09-17 18:16:38 +0000167 struct clk *biu_clk;
168 struct clk *ciu_clk;
Will Newtonf95f3852011-01-02 01:11:59 -0500169 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
170
171 /* FIFO push and pull */
James Hoganb86d8252011-06-24 13:57:18 +0100172 int fifo_depth;
Will Newtonf95f3852011-01-02 01:11:59 -0500173 int data_shift;
James Hogan34b664a2011-06-24 13:57:56 +0100174 u8 part_buf_start;
175 u8 part_buf_count;
176 union {
177 u16 part_buf16;
178 u32 part_buf32;
179 u64 part_buf;
180 };
Will Newtonf95f3852011-01-02 01:11:59 -0500181 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
182 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
183
184 /* Workaround flags */
185 u32 quirks;
Jaehoon Chungc07946a2011-02-25 11:08:14 +0900186
187 struct regulator *vmmc; /* Power regulator */
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +0530188 unsigned long irq_flags; /* IRQ flags */
Seungwon Jeond6761882012-09-28 14:21:59 +0900189 int irq;
Will Newtonf95f3852011-01-02 01:11:59 -0500190};
191
192/* DMA ops for Internal/External DMAC interface */
193struct dw_mci_dma_ops {
194 /* DMA Ops */
195 int (*init)(struct dw_mci *host);
196 void (*start)(struct dw_mci *host, unsigned int sg_len);
197 void (*complete)(struct dw_mci *host);
198 void (*stop)(struct dw_mci *host);
199 void (*cleanup)(struct dw_mci *host);
200 void (*exit)(struct dw_mci *host);
201};
202
203/* IP Quirks/flags. */
Will Newtonf95f3852011-01-02 01:11:59 -0500204/* DTO fix for command transmission with IDMAC configured */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900205#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
Will Newtonf95f3852011-01-02 01:11:59 -0500206/* delay needed between retries on some 2.11a implementations */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900207#define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300208/* High Speed Capable - Supports HS cards (up to 50MHz) */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900209#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
210/* Unreliable card detection */
211#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
Thomas Abrahamb4967aa2012-09-17 18:16:39 +0000212/* Write Protect detection not available */
213#define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4)
Will Newtonf95f3852011-01-02 01:11:59 -0500214
215struct dma_pdata;
216
217struct block_settings {
218 unsigned short max_segs; /* see blk_queue_max_segments */
219 unsigned int max_blk_size; /* maximum size of one mmc block */
220 unsigned int max_blk_count; /* maximum number of blocks in one req*/
221 unsigned int max_req_size; /* maximum number of bytes in one req*/
222 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
223};
224
225/* Board platform data */
226struct dw_mci_board {
227 u32 num_slots;
228
229 u32 quirks; /* Workaround / Quirk flags */
Thomas Abrahamc3665002012-09-17 18:16:43 +0000230 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
Will Newtonf95f3852011-01-02 01:11:59 -0500231
Lee Jones5f1a4dd2012-11-14 12:35:51 +0000232 u32 caps; /* Capabilities */
233 u32 caps2; /* More capabilities */
James Hoganb86d8252011-06-24 13:57:18 +0100234 /*
235 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
236 * but note that this may not be reliable after a bootloader has used
237 * it.
238 */
239 unsigned int fifo_depth;
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900240
Will Newtonf95f3852011-01-02 01:11:59 -0500241 /* delay in mS before detecting cards after interrupt */
242 u32 detect_delay_ms;
243
244 int (*init)(u32 slot_id, irq_handler_t , void *);
245 int (*get_ro)(u32 slot_id);
246 int (*get_cd)(u32 slot_id);
247 int (*get_ocr)(u32 slot_id);
248 int (*get_bus_wd)(u32 slot_id);
249 /*
250 * Enable power to selected slot and set voltage to desired level.
251 * Voltage levels are specified using MMC_VDD_xxx defines defined
252 * in linux/mmc/host.h file.
253 */
254 void (*setpower)(u32 slot_id, u32 volt);
255 void (*exit)(u32 slot_id);
256 void (*select_slot)(u32 slot_id);
257
258 struct dw_mci_dma_ops *dma_ops;
259 struct dma_pdata *data;
260 struct block_settings *blk_settings;
261};
262
Robert P. J. Day100e9182011-05-27 16:04:03 -0400263#endif /* LINUX_MMC_DW_MMC_H */