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Tomas Winkler6f83eaa2008-03-04 18:09:28 -08001/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
Reinette Chatreeb7ae892008-03-11 16:17:17 -070033 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
Tomas Winkler6f83eaa2008-03-04 18:09:28 -080034 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63/*=== CSR (control and status registers) ===*/
64#define CSR_BASE (0x000)
65
66#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
67#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
68#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
69#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
70#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
71#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
72#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
73#define CSR_GP_CNTRL (CSR_BASE+0x024)
74
75/*
76 * Hardware revision info
77 * Bit fields:
78 * 31-8: Reserved
79 * 7-4: Type of device: 0x0 = 4965, 0xd = 3945
80 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
81 * 1-0: "Dash" value, as in A-1, etc.
82 *
83 * NOTE: Revision step affects calculation of CCK txpower for 4965.
84 */
85#define CSR_HW_REV (CSR_BASE+0x028)
86
87/* EEPROM reads */
88#define CSR_EEPROM_REG (CSR_BASE+0x02c)
89#define CSR_EEPROM_GP (CSR_BASE+0x030)
90#define CSR_GP_UCODE (CSR_BASE+0x044)
91#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
92#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
93#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
94#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
95#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
Mohamed Abbasab53d8a2008-03-25 16:33:36 -070096#define CSR_LED_REG (CSR_BASE+0x094)
Tomas Winkler6f83eaa2008-03-04 18:09:28 -080097
98/* Analog phase-lock-loop configuration (3945 only)
99 * Set bit 24. */
100#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
101/*
102 * Indicates hardware rev, to determine CCK backoff for txpower calculation.
103 * Bit fields:
104 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
105 */
106#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
107
108/* Bits for CSR_HW_IF_CONFIG_REG */
109#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
110#define CSR49_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
111#define CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
112#define CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
113
114#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100)
115#define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200)
116#define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
117#define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
118#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
119#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
120
121#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
122
123/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
124 * acknowledged (reset) by host writing "1" to flagged bits. */
125#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
126#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
127#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
128#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
129#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
130#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
131#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
132#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
133#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
134#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
135#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
136
137#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
138 CSR_INT_BIT_HW_ERR | \
139 CSR_INT_BIT_FH_TX | \
140 CSR_INT_BIT_SW_ERR | \
141 CSR_INT_BIT_RF_KILL | \
142 CSR_INT_BIT_SW_RX | \
143 CSR_INT_BIT_WAKEUP | \
144 CSR_INT_BIT_ALIVE)
145
146/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
147#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
148#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
149#define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */
150#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
151#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
152#define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */
153#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
154#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
155
156#define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
157 CSR39_FH_INT_BIT_RX_CHNL2 | \
158 CSR_FH_INT_BIT_RX_CHNL1 | \
159 CSR_FH_INT_BIT_RX_CHNL0)
160
161
162#define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \
163 CSR_FH_INT_BIT_TX_CHNL1 | \
164 CSR_FH_INT_BIT_TX_CHNL0)
165
166#define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
167 CSR_FH_INT_BIT_RX_CHNL1 | \
168 CSR_FH_INT_BIT_RX_CHNL0)
169
170#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
171 CSR_FH_INT_BIT_TX_CHNL0)
172
173
174/* RESET */
175#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
176#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
177#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
178#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
179#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
180
181/* GP (general purpose) CONTROL */
182#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
183#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
184#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
185#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
186
187#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
188
189#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
190#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
191#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
192
193
194/* EEPROM REG */
195#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
196#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
197
198/* EEPROM GP */
199#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
200#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
201#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
202
203/* UCODE DRV GP */
204#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
205#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
206#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
207#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
208
209/* GPIO */
210#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
211#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
212#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
213
214/* GI Chicken Bits */
215#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
216#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
217
Mohamed Abbasab53d8a2008-03-25 16:33:36 -0700218/* LED */
219#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
220#define CSR_LED_REG_TRUN_ON (0x78)
221#define CSR_LED_REG_TRUN_OFF (0x38)
222
Tomas Winkler750fe632008-03-04 18:09:29 -0800223/*=== HBUS (Host-side Bus) ===*/
224#define HBUS_BASE (0x400)
225/*
226 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
227 * structures, error log, event log, verifying uCode load).
228 * First write to address register, then read from or write to data register
229 * to complete the job. Once the address register is set up, accesses to
230 * data registers auto-increment the address by one dword.
231 * Bit usage for address registers (read or write):
232 * 0-31: memory address within device
233 */
234#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
235#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
236#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
237#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
238
239/*
240 * Registers for accessing device's internal peripheral registers
241 * (e.g. SCD, BSM, etc.). First write to address register,
242 * then read from or write to data register to complete the job.
243 * Bit usage for address registers (read or write):
244 * 0-15: register address (offset) within device
245 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
246 */
247#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
248#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
249#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
250#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
251
252/*
253 * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
254 * Indicates index to next TFD that driver will fill (1 past latest filled).
255 * Bit usage:
256 * 0-7: queue write index
257 * 11-8: queue selector
258 */
259#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
260#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
261
262#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
263
264
Tomas Winkler6f83eaa2008-03-04 18:09:28 -0800265