blob: 5d17b63c107cc5664b5ad3b1bff24031d7ef6c0f [file] [log] [blame]
Alex Dai33a732f2015-08-12 15:43:36 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
28 */
29#include <linux/firmware.h>
30#include "i915_drv.h"
31#include "intel_guc.h"
32
33/**
34 * DOC: GuC
35 *
36 * intel_guc:
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
40 *
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
46 * of firmware.
47 *
48 * GuC address space:
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
53 *
54 * Firmware log:
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
58 * registers value.
59 *
60 */
61
Alex Daiaa557ab2015-08-18 14:32:35 -070062#define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
Alex Dai33a732f2015-08-12 15:43:36 +010063MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
64
65/* User-friendly representation of an enum */
66const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
67{
68 switch (status) {
69 case GUC_FIRMWARE_FAIL:
70 return "FAIL";
71 case GUC_FIRMWARE_NONE:
72 return "NONE";
73 case GUC_FIRMWARE_PENDING:
74 return "PENDING";
75 case GUC_FIRMWARE_SUCCESS:
76 return "SUCCESS";
77 default:
78 return "UNKNOWN!";
79 }
80};
81
Dave Gordon4df001d2015-08-12 15:43:42 +010082static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
83{
84 struct intel_engine_cs *ring;
85 int i, irqs;
86
87 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
88 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
89 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
90 for_each_ring(ring, dev_priv, i)
91 I915_WRITE(RING_MODE_GEN7(ring), irqs);
92
93 /* tell DE to send nothing to GuC */
94 I915_WRITE(DE_GUCRMR, ~0);
95
96 /* route all GT interrupts to the host */
97 I915_WRITE(GUC_BCS_RCS_IER, 0);
98 I915_WRITE(GUC_VCS2_VCS1_IER, 0);
99 I915_WRITE(GUC_WD_VECS_IER, 0);
100}
101
102static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
103{
104 struct intel_engine_cs *ring;
105 int i, irqs;
106
107 /* tell all command streamers to forward interrupts and vblank to GuC */
108 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
109 irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
110 for_each_ring(ring, dev_priv, i)
111 I915_WRITE(RING_MODE_GEN7(ring), irqs);
112
113 /* tell DE to send (all) flip_done to GuC */
114 irqs = DERRMR_PIPEA_PRI_FLIP_DONE | DERRMR_PIPEA_SPR_FLIP_DONE |
115 DERRMR_PIPEB_PRI_FLIP_DONE | DERRMR_PIPEB_SPR_FLIP_DONE |
116 DERRMR_PIPEC_PRI_FLIP_DONE | DERRMR_PIPEC_SPR_FLIP_DONE;
117 /* Unmasked bits will cause GuC response message to be sent */
118 I915_WRITE(DE_GUCRMR, ~irqs);
119
120 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
121 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
122 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
123 /* These three registers have the same bit definitions */
124 I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
125 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
126 I915_WRITE(GUC_WD_VECS_IER, ~irqs);
127}
128
Alex Dai33a732f2015-08-12 15:43:36 +0100129static u32 get_gttype(struct drm_i915_private *dev_priv)
130{
131 /* XXX: GT type based on PCI device ID? field seems unused by fw */
132 return 0;
133}
134
135static u32 get_core_family(struct drm_i915_private *dev_priv)
136{
137 switch (INTEL_INFO(dev_priv)->gen) {
138 case 9:
139 return GFXCORE_FAMILY_GEN9;
140
141 default:
142 DRM_ERROR("GUC: unsupported core family\n");
143 return GFXCORE_FAMILY_UNKNOWN;
144 }
145}
146
147static void set_guc_init_params(struct drm_i915_private *dev_priv)
148{
149 struct intel_guc *guc = &dev_priv->guc;
150 u32 params[GUC_CTL_MAX_DWORDS];
151 int i;
152
153 memset(&params, 0, sizeof(params));
154
155 params[GUC_CTL_DEVICE_INFO] |=
156 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
157 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
158
159 /*
160 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
161 * second. This ARAR is calculated by:
162 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
163 */
164 params[GUC_CTL_ARAT_HIGH] = 0;
165 params[GUC_CTL_ARAT_LOW] = 100000000;
166
167 params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
168
169 params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
170 GUC_CTL_VCS2_ENABLED;
171
172 if (i915.guc_log_level >= 0) {
173 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
174 params[GUC_CTL_DEBUG] =
175 i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
176 }
177
Alex Daibac427f2015-08-12 15:43:39 +0100178 /* If GuC submission is enabled, set up additional parameters here */
179 if (i915.enable_guc_submission) {
180 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
181 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
182
183 pgs >>= PAGE_SHIFT;
184 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
185 (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
186
187 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
188
189 /* Unmask this bit to enable the GuC's internal scheduler */
190 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
191 }
192
Alex Dai33a732f2015-08-12 15:43:36 +0100193 I915_WRITE(SOFT_SCRATCH(0), 0);
194
195 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
196 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
197}
198
199/*
200 * Read the GuC status register (GUC_STATUS) and store it in the
201 * specified location; then return a boolean indicating whether
202 * the value matches either of two values representing completion
203 * of the GuC boot process.
204 *
205 * This is used for polling the GuC status in a wait_for_atomic()
206 * loop below.
207 */
208static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
209 u32 *status)
210{
211 u32 val = I915_READ(GUC_STATUS);
Alex Dai0d44d3f2015-09-22 13:48:40 -0700212 u32 uk_val = val & GS_UKERNEL_MASK;
Alex Dai33a732f2015-08-12 15:43:36 +0100213 *status = val;
Alex Dai0d44d3f2015-09-22 13:48:40 -0700214 return (uk_val == GS_UKERNEL_READY ||
215 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
Alex Dai33a732f2015-08-12 15:43:36 +0100216}
217
218/*
219 * Transfer the firmware image to RAM for execution by the microcontroller.
220 *
221 * GuC Firmware layout:
222 * +-------------------------------+ ----
223 * | CSS header | 128B
224 * | contains major/minor version |
225 * +-------------------------------+ ----
226 * | uCode |
227 * +-------------------------------+ ----
228 * | RSA signature | 256B
229 * +-------------------------------+ ----
Alex Dai33a732f2015-08-12 15:43:36 +0100230 *
231 * Architecturally, the DMA engine is bidirectional, and can potentially even
232 * transfer between GTT locations. This functionality is left out of the API
233 * for now as there is no need for it.
234 *
235 * Note that GuC needs the CSS header plus uKernel code to be copied by the
236 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
237 */
238
239#define UOS_CSS_HEADER_OFFSET 0
240#define UOS_VER_MINOR_OFFSET 0x44
241#define UOS_VER_MAJOR_OFFSET 0x46
242#define UOS_CSS_HEADER_SIZE 0x80
243#define UOS_RSA_SIG_SIZE 0x100
Alex Dai33a732f2015-08-12 15:43:36 +0100244
245static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
246{
247 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
248 struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
249 unsigned long offset;
250 struct sg_table *sg = fw_obj->pages;
251 u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
252 int i, ret = 0;
253
254 /* uCode size, also is where RSA signature starts */
Alex Daiaa557ab2015-08-18 14:32:35 -0700255 offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
Alex Dai33a732f2015-08-12 15:43:36 +0100256 I915_WRITE(DMA_COPY_SIZE, ucode_size);
257
258 /* Copy RSA signature from the fw image to HW for verification */
259 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
260 for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
Ville Syrjäläab9cc552015-09-18 20:03:24 +0300261 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
Alex Dai33a732f2015-08-12 15:43:36 +0100262
263 /* Set the source address for the new blob */
264 offset = i915_gem_obj_ggtt_offset(fw_obj);
265 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
266 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
267
268 /*
269 * Set the DMA destination. Current uCode expects the code to be
270 * loaded at 8k; locations below this are used for the stack.
271 */
272 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
273 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
274
275 /* Finally start the DMA */
276 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
277
278 /*
279 * Spin-wait for the DMA to complete & the GuC to start up.
280 * NB: Docs recommend not using the interrupt for completion.
281 * Measurements indicate this should take no more than 20ms, so a
282 * timeout here indicates that the GuC has failed and is unusable.
283 * (Higher levels of the driver will attempt to fall back to
284 * execlist mode if this happens.)
285 */
286 ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
287
288 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
289 I915_READ(DMA_CTRL), status);
290
291 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
292 DRM_ERROR("GuC firmware signature verification failed\n");
293 ret = -ENOEXEC;
294 }
295
296 DRM_DEBUG_DRIVER("returning %d\n", ret);
297
298 return ret;
299}
300
301/*
302 * Load the GuC firmware blob into the MinuteIA.
303 */
304static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
305{
306 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
307 struct drm_device *dev = dev_priv->dev;
308 int ret;
309
310 ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
311 if (ret) {
312 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
313 return ret;
314 }
315
316 ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
317 if (ret) {
318 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
319 return ret;
320 }
321
322 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
323 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
324
325 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
326
327 /* init WOPCM */
328 I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
329 I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
330
331 /* Enable MIA caching. GuC clock gating is disabled. */
332 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
333
Nick Hoathb970b482015-09-08 10:31:53 +0100334 /* WaDisableMinuteIaClockGating:skl,bxt */
335 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
336 (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
337 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
338 ~GUC_ENABLE_MIA_CLOCK_GATING));
339 }
340
Alex Dai33a732f2015-08-12 15:43:36 +0100341 /* WaC6DisallowByGfxPause*/
342 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
343
344 if (IS_BROXTON(dev))
345 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
346 else
347 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
348
349 if (IS_GEN9(dev)) {
350 /* DOP Clock Gating Enable for GuC clocks */
351 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
352 I915_READ(GEN7_MISCCPCTL)));
353
354 /* allows for 5us before GT can go to RC6 */
355 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
356 }
357
358 set_guc_init_params(dev_priv);
359
360 ret = guc_ucode_xfer_dma(dev_priv);
361
362 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
363
364 /*
365 * We keep the object pages for reuse during resume. But we can unpin it
366 * now that DMA has completed, so it doesn't continue to take up space.
367 */
368 i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
369
370 return ret;
371}
372
373/**
374 * intel_guc_ucode_load() - load GuC uCode into the device
375 * @dev: drm device
376 *
377 * Called from gem_init_hw() during driver loading and also after a GPU reset.
378 *
379 * The firmware image should have already been fetched into memory by the
380 * earlier call to intel_guc_ucode_init(), so here we need only check that
381 * is succeeded, and then transfer the image to the h/w.
382 *
383 * Return: non-zero code on error
384 */
385int intel_guc_ucode_load(struct drm_device *dev)
386{
387 struct drm_i915_private *dev_priv = dev->dev_private;
388 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
389 int err = 0;
390
391 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
392 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
393 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
394
Dave Gordon4df001d2015-08-12 15:43:42 +0100395 direct_interrupts_to_host(dev_priv);
Dave Gordon44a28b12015-08-12 15:43:41 +0100396 i915_guc_submission_disable(dev);
397
Alex Dai33a732f2015-08-12 15:43:36 +0100398 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
399 return 0;
400
401 if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
402 guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
403 return -ENOEXEC;
404
405 guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
406
407 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
408 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
409
410 switch (guc_fw->guc_fw_fetch_status) {
411 case GUC_FIRMWARE_FAIL:
412 /* something went wrong :( */
413 err = -EIO;
414 goto fail;
415
416 case GUC_FIRMWARE_NONE:
417 case GUC_FIRMWARE_PENDING:
418 default:
419 /* "can't happen" */
420 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
421 guc_fw->guc_fw_path,
422 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
423 guc_fw->guc_fw_fetch_status);
424 err = -ENXIO;
425 goto fail;
426
427 case GUC_FIRMWARE_SUCCESS:
428 break;
429 }
430
Alex Daibac427f2015-08-12 15:43:39 +0100431 err = i915_guc_submission_init(dev);
432 if (err)
433 goto fail;
434
Alex Dai33a732f2015-08-12 15:43:36 +0100435 err = guc_ucode_xfer(dev_priv);
436 if (err)
437 goto fail;
438
439 guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
440
441 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
442 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
443 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
444
Dave Gordon44a28b12015-08-12 15:43:41 +0100445 if (i915.enable_guc_submission) {
446 err = i915_guc_submission_enable(dev);
447 if (err)
448 goto fail;
Dave Gordon4df001d2015-08-12 15:43:42 +0100449 direct_interrupts_to_guc(dev_priv);
Dave Gordon44a28b12015-08-12 15:43:41 +0100450 }
451
Alex Dai33a732f2015-08-12 15:43:36 +0100452 return 0;
453
454fail:
455 if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
456 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
457
Dave Gordon4df001d2015-08-12 15:43:42 +0100458 direct_interrupts_to_host(dev_priv);
Dave Gordon44a28b12015-08-12 15:43:41 +0100459 i915_guc_submission_disable(dev);
460
Alex Dai33a732f2015-08-12 15:43:36 +0100461 return err;
462}
463
464static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
465{
466 struct drm_i915_gem_object *obj;
467 const struct firmware *fw;
468 const u8 *css_header;
Alex Daiaa557ab2015-08-18 14:32:35 -0700469 const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
470 const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
Alex Dai33a732f2015-08-12 15:43:36 +0100471 - 0x8000; /* 32k reserved (8K stack + 24k context) */
472 int err;
473
474 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
475 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
476
477 err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
478 if (err)
479 goto fail;
480 if (!fw)
481 goto fail;
482
483 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
484 guc_fw->guc_fw_path, fw);
485 DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
486 fw->size, minsize, maxsize);
487
488 /* Check the size of the blob befoe examining buffer contents */
489 if (fw->size < minsize || fw->size > maxsize)
490 goto fail;
491
492 /*
493 * The GuC firmware image has the version number embedded at a well-known
494 * offset within the firmware blob; note that major / minor version are
495 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
496 * in terms of bytes (u8).
497 */
498 css_header = fw->data + UOS_CSS_HEADER_OFFSET;
499 guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
500 guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
501
502 if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
503 guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
504 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
505 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
506 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
507 err = -ENOEXEC;
508 goto fail;
509 }
510
511 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
512 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
513 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
514
515 obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
516 if (IS_ERR_OR_NULL(obj)) {
517 err = obj ? PTR_ERR(obj) : -ENOMEM;
518 goto fail;
519 }
520
521 guc_fw->guc_fw_obj = obj;
522 guc_fw->guc_fw_size = fw->size;
523
524 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
525 guc_fw->guc_fw_obj);
526
527 release_firmware(fw);
528 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
529 return;
530
531fail:
532 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
533 err, fw, guc_fw->guc_fw_obj);
534 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
535 guc_fw->guc_fw_path, err);
536
537 obj = guc_fw->guc_fw_obj;
538 if (obj)
539 drm_gem_object_unreference(&obj->base);
540 guc_fw->guc_fw_obj = NULL;
541
542 release_firmware(fw); /* OK even if fw is NULL */
543 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
544}
545
546/**
547 * intel_guc_ucode_init() - define parameters and fetch firmware
548 * @dev: drm device
549 *
550 * Called early during driver load, but after GEM is initialised.
551 * The device struct_mutex must be held by the caller, as we're
552 * going to allocate a GEM object to hold the firmware image.
553 *
554 * The firmware will be transferred to the GuC's memory later,
555 * when intel_guc_ucode_load() is called.
556 */
557void intel_guc_ucode_init(struct drm_device *dev)
558{
559 struct drm_i915_private *dev_priv = dev->dev_private;
560 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
561 const char *fw_path;
562
563 if (!HAS_GUC_SCHED(dev))
564 i915.enable_guc_submission = false;
565
566 if (!HAS_GUC_UCODE(dev)) {
567 fw_path = NULL;
568 } else if (IS_SKYLAKE(dev)) {
569 fw_path = I915_SKL_GUC_UCODE;
Alex Daiaa557ab2015-08-18 14:32:35 -0700570 guc_fw->guc_fw_major_wanted = 4;
571 guc_fw->guc_fw_minor_wanted = 3;
Alex Dai33a732f2015-08-12 15:43:36 +0100572 } else {
573 i915.enable_guc_submission = false;
574 fw_path = ""; /* unknown device */
575 }
576
577 guc_fw->guc_dev = dev;
578 guc_fw->guc_fw_path = fw_path;
579 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
580 guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
581
582 if (fw_path == NULL)
583 return;
584
585 if (*fw_path == '\0') {
586 DRM_ERROR("No GuC firmware known for this platform\n");
587 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
588 return;
589 }
590
591 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
592 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
593 guc_fw_fetch(dev, guc_fw);
594 /* status must now be FAIL or SUCCESS */
595}
596
597/**
598 * intel_guc_ucode_fini() - clean up all allocated resources
599 * @dev: drm device
600 */
601void intel_guc_ucode_fini(struct drm_device *dev)
602{
603 struct drm_i915_private *dev_priv = dev->dev_private;
604 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
605
Dave Gordon4df001d2015-08-12 15:43:42 +0100606 direct_interrupts_to_host(dev_priv);
Alex Daibac427f2015-08-12 15:43:39 +0100607 i915_guc_submission_fini(dev);
608
Alex Dai33a732f2015-08-12 15:43:36 +0100609 if (guc_fw->guc_fw_obj)
610 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
611 guc_fw->guc_fw_obj = NULL;
612
613 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
614}