blob: 97e98278c21a82146adaca03c78a08ea42c20875 [file] [log] [blame]
Stephen Boyd6d00b562014-01-15 10:47:29 -08001/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
Stephen Boyd88036092015-06-19 15:00:46 -070022#include <linux/clk.h>
Stephen Boyd6d00b562014-01-15 10:47:29 -080023#include <linux/clk-provider.h>
24#include <linux/regmap.h>
25#include <linux/reset-controller.h>
26
27#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
28#include <dt-bindings/reset/qcom,mmcc-msm8960.h>
29
Stephen Boyd49fc8252014-03-21 17:59:37 -070030#include "common.h"
Stephen Boyd6d00b562014-01-15 10:47:29 -080031#include "clk-regmap.h"
32#include "clk-pll.h"
33#include "clk-rcg.h"
34#include "clk-branch.h"
35#include "reset.h"
36
Georgi Djakov293d2e972015-03-20 18:30:26 +020037enum {
38 P_PXO,
39 P_PLL8,
40 P_PLL2,
41 P_PLL3,
42 P_PLL15,
43 P_HDMI_PLL,
44};
Stephen Boyd6d00b562014-01-15 10:47:29 -080045
Stephen Boydff207832014-07-08 18:36:06 -070046#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
Stephen Boyd6d00b562014-01-15 10:47:29 -080047
Georgi Djakov293d2e972015-03-20 18:30:26 +020048static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
49 { P_PXO, 0 },
50 { P_PLL8, 2 },
51 { P_PLL2, 1 }
Stephen Boyd6d00b562014-01-15 10:47:29 -080052};
53
Georgi Djakovadb11a42015-07-06 16:51:30 +030054static const char * const mmcc_pxo_pll8_pll2[] = {
Stephen Boyd6d00b562014-01-15 10:47:29 -080055 "pxo",
56 "pll8_vote",
57 "pll2",
58};
59
Georgi Djakov293d2e972015-03-20 18:30:26 +020060static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
61 { P_PXO, 0 },
62 { P_PLL8, 2 },
63 { P_PLL2, 1 },
64 { P_PLL3, 3 }
Stephen Boyd6d00b562014-01-15 10:47:29 -080065};
66
Georgi Djakovadb11a42015-07-06 16:51:30 +030067static const char * const mmcc_pxo_pll8_pll2_pll15[] = {
Stephen Boyde216ce62014-07-15 14:52:22 -070068 "pxo",
69 "pll8_vote",
70 "pll2",
71 "pll15",
72};
73
Georgi Djakov293d2e972015-03-20 18:30:26 +020074static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
75 { P_PXO, 0 },
76 { P_PLL8, 2 },
77 { P_PLL2, 1 },
78 { P_PLL15, 3 }
Stephen Boyde216ce62014-07-15 14:52:22 -070079};
80
Georgi Djakovadb11a42015-07-06 16:51:30 +030081static const char * const mmcc_pxo_pll8_pll2_pll3[] = {
Stephen Boyd6d00b562014-01-15 10:47:29 -080082 "pxo",
Stephen Boyd6d00b562014-01-15 10:47:29 -080083 "pll8_vote",
Stephen Boydff207832014-07-08 18:36:06 -070084 "pll2",
Stephen Boyd6d00b562014-01-15 10:47:29 -080085 "pll3",
86};
87
88static struct clk_pll pll2 = {
89 .l_reg = 0x320,
90 .m_reg = 0x324,
91 .n_reg = 0x328,
92 .config_reg = 0x32c,
93 .mode_reg = 0x31c,
94 .status_reg = 0x334,
95 .status_bit = 16,
96 .clkr.hw.init = &(struct clk_init_data){
97 .name = "pll2",
98 .parent_names = (const char *[]){ "pxo" },
99 .num_parents = 1,
100 .ops = &clk_pll_ops,
101 },
102};
103
Stephen Boyde216ce62014-07-15 14:52:22 -0700104static struct clk_pll pll15 = {
105 .l_reg = 0x33c,
106 .m_reg = 0x340,
107 .n_reg = 0x344,
108 .config_reg = 0x348,
109 .mode_reg = 0x338,
110 .status_reg = 0x350,
111 .status_bit = 16,
112 .clkr.hw.init = &(struct clk_init_data){
113 .name = "pll15",
114 .parent_names = (const char *[]){ "pxo" },
115 .num_parents = 1,
116 .ops = &clk_pll_ops,
117 },
118};
119
120static const struct pll_config pll15_config = {
121 .l = 33,
122 .m = 1,
123 .n = 3,
124 .vco_val = 0x2 << 16,
125 .vco_mask = 0x3 << 16,
126 .pre_div_val = 0x0,
127 .pre_div_mask = BIT(19),
128 .post_div_val = 0x0,
129 .post_div_mask = 0x3 << 20,
130 .mn_ena_mask = BIT(22),
131 .main_output_mask = BIT(23),
132};
133
Stephen Boyd6d00b562014-01-15 10:47:29 -0800134static struct freq_tbl clk_tbl_cam[] = {
135 { 6000000, P_PLL8, 4, 1, 16 },
136 { 8000000, P_PLL8, 4, 1, 12 },
137 { 12000000, P_PLL8, 4, 1, 8 },
138 { 16000000, P_PLL8, 4, 1, 6 },
139 { 19200000, P_PLL8, 4, 1, 5 },
140 { 24000000, P_PLL8, 4, 1, 4 },
141 { 32000000, P_PLL8, 4, 1, 3 },
142 { 48000000, P_PLL8, 4, 1, 2 },
143 { 64000000, P_PLL8, 3, 1, 2 },
144 { 96000000, P_PLL8, 4, 0, 0 },
145 { 128000000, P_PLL8, 3, 0, 0 },
146 { }
147};
148
149static struct clk_rcg camclk0_src = {
150 .ns_reg = 0x0148,
151 .md_reg = 0x0144,
152 .mn = {
153 .mnctr_en_bit = 5,
154 .mnctr_reset_bit = 8,
155 .reset_in_cc = true,
156 .mnctr_mode_shift = 6,
157 .n_val_shift = 24,
158 .m_val_shift = 8,
159 .width = 8,
160 },
161 .p = {
162 .pre_div_shift = 14,
163 .pre_div_width = 2,
164 },
165 .s = {
166 .src_sel_shift = 0,
167 .parent_map = mmcc_pxo_pll8_pll2_map,
168 },
169 .freq_tbl = clk_tbl_cam,
170 .clkr = {
171 .enable_reg = 0x0140,
172 .enable_mask = BIT(2),
173 .hw.init = &(struct clk_init_data){
174 .name = "camclk0_src",
175 .parent_names = mmcc_pxo_pll8_pll2,
176 .num_parents = 3,
177 .ops = &clk_rcg_ops,
178 },
179 },
180};
181
182static struct clk_branch camclk0_clk = {
183 .halt_reg = 0x01e8,
184 .halt_bit = 15,
185 .clkr = {
186 .enable_reg = 0x0140,
187 .enable_mask = BIT(0),
188 .hw.init = &(struct clk_init_data){
189 .name = "camclk0_clk",
190 .parent_names = (const char *[]){ "camclk0_src" },
191 .num_parents = 1,
192 .ops = &clk_branch_ops,
193 },
194 },
195
196};
197
198static struct clk_rcg camclk1_src = {
199 .ns_reg = 0x015c,
200 .md_reg = 0x0158,
201 .mn = {
202 .mnctr_en_bit = 5,
203 .mnctr_reset_bit = 8,
204 .reset_in_cc = true,
205 .mnctr_mode_shift = 6,
206 .n_val_shift = 24,
207 .m_val_shift = 8,
208 .width = 8,
209 },
210 .p = {
211 .pre_div_shift = 14,
212 .pre_div_width = 2,
213 },
214 .s = {
215 .src_sel_shift = 0,
216 .parent_map = mmcc_pxo_pll8_pll2_map,
217 },
218 .freq_tbl = clk_tbl_cam,
219 .clkr = {
220 .enable_reg = 0x0154,
221 .enable_mask = BIT(2),
222 .hw.init = &(struct clk_init_data){
223 .name = "camclk1_src",
224 .parent_names = mmcc_pxo_pll8_pll2,
225 .num_parents = 3,
226 .ops = &clk_rcg_ops,
227 },
228 },
229};
230
231static struct clk_branch camclk1_clk = {
232 .halt_reg = 0x01e8,
233 .halt_bit = 16,
234 .clkr = {
235 .enable_reg = 0x0154,
236 .enable_mask = BIT(0),
237 .hw.init = &(struct clk_init_data){
238 .name = "camclk1_clk",
239 .parent_names = (const char *[]){ "camclk1_src" },
240 .num_parents = 1,
241 .ops = &clk_branch_ops,
242 },
243 },
244
245};
246
247static struct clk_rcg camclk2_src = {
248 .ns_reg = 0x0228,
249 .md_reg = 0x0224,
250 .mn = {
251 .mnctr_en_bit = 5,
252 .mnctr_reset_bit = 8,
253 .reset_in_cc = true,
254 .mnctr_mode_shift = 6,
255 .n_val_shift = 24,
256 .m_val_shift = 8,
257 .width = 8,
258 },
259 .p = {
260 .pre_div_shift = 14,
261 .pre_div_width = 2,
262 },
263 .s = {
264 .src_sel_shift = 0,
265 .parent_map = mmcc_pxo_pll8_pll2_map,
266 },
267 .freq_tbl = clk_tbl_cam,
268 .clkr = {
269 .enable_reg = 0x0220,
270 .enable_mask = BIT(2),
271 .hw.init = &(struct clk_init_data){
272 .name = "camclk2_src",
273 .parent_names = mmcc_pxo_pll8_pll2,
274 .num_parents = 3,
275 .ops = &clk_rcg_ops,
276 },
277 },
278};
279
280static struct clk_branch camclk2_clk = {
281 .halt_reg = 0x01e8,
282 .halt_bit = 16,
283 .clkr = {
284 .enable_reg = 0x0220,
285 .enable_mask = BIT(0),
286 .hw.init = &(struct clk_init_data){
287 .name = "camclk2_clk",
288 .parent_names = (const char *[]){ "camclk2_src" },
289 .num_parents = 1,
290 .ops = &clk_branch_ops,
291 },
292 },
293
294};
295
296static struct freq_tbl clk_tbl_csi[] = {
297 { 27000000, P_PXO, 1, 0, 0 },
298 { 85330000, P_PLL8, 1, 2, 9 },
299 { 177780000, P_PLL2, 1, 2, 9 },
300 { }
301};
302
303static struct clk_rcg csi0_src = {
304 .ns_reg = 0x0048,
305 .md_reg = 0x0044,
306 .mn = {
307 .mnctr_en_bit = 5,
308 .mnctr_reset_bit = 7,
309 .mnctr_mode_shift = 6,
310 .n_val_shift = 24,
311 .m_val_shift = 8,
312 .width = 8,
313 },
314 .p = {
315 .pre_div_shift = 14,
316 .pre_div_width = 2,
317 },
318 .s = {
319 .src_sel_shift = 0,
320 .parent_map = mmcc_pxo_pll8_pll2_map,
321 },
322 .freq_tbl = clk_tbl_csi,
323 .clkr = {
324 .enable_reg = 0x0040,
325 .enable_mask = BIT(2),
326 .hw.init = &(struct clk_init_data){
327 .name = "csi0_src",
328 .parent_names = mmcc_pxo_pll8_pll2,
329 .num_parents = 3,
330 .ops = &clk_rcg_ops,
331 },
332 },
333};
334
335static struct clk_branch csi0_clk = {
336 .halt_reg = 0x01cc,
337 .halt_bit = 13,
338 .clkr = {
339 .enable_reg = 0x0040,
340 .enable_mask = BIT(0),
341 .hw.init = &(struct clk_init_data){
342 .parent_names = (const char *[]){ "csi0_src" },
343 .num_parents = 1,
344 .name = "csi0_clk",
345 .ops = &clk_branch_ops,
346 .flags = CLK_SET_RATE_PARENT,
347 },
348 },
349};
350
351static struct clk_branch csi0_phy_clk = {
352 .halt_reg = 0x01e8,
353 .halt_bit = 9,
354 .clkr = {
355 .enable_reg = 0x0040,
356 .enable_mask = BIT(8),
357 .hw.init = &(struct clk_init_data){
358 .parent_names = (const char *[]){ "csi0_src" },
359 .num_parents = 1,
360 .name = "csi0_phy_clk",
361 .ops = &clk_branch_ops,
362 .flags = CLK_SET_RATE_PARENT,
363 },
364 },
365};
366
367static struct clk_rcg csi1_src = {
368 .ns_reg = 0x0010,
369 .md_reg = 0x0028,
370 .mn = {
371 .mnctr_en_bit = 5,
372 .mnctr_reset_bit = 7,
373 .mnctr_mode_shift = 6,
374 .n_val_shift = 24,
375 .m_val_shift = 8,
376 .width = 8,
377 },
378 .p = {
379 .pre_div_shift = 14,
380 .pre_div_width = 2,
381 },
382 .s = {
383 .src_sel_shift = 0,
384 .parent_map = mmcc_pxo_pll8_pll2_map,
385 },
386 .freq_tbl = clk_tbl_csi,
387 .clkr = {
388 .enable_reg = 0x0024,
389 .enable_mask = BIT(2),
390 .hw.init = &(struct clk_init_data){
391 .name = "csi1_src",
392 .parent_names = mmcc_pxo_pll8_pll2,
393 .num_parents = 3,
394 .ops = &clk_rcg_ops,
395 },
396 },
397};
398
399static struct clk_branch csi1_clk = {
400 .halt_reg = 0x01cc,
401 .halt_bit = 14,
402 .clkr = {
403 .enable_reg = 0x0024,
404 .enable_mask = BIT(0),
405 .hw.init = &(struct clk_init_data){
406 .parent_names = (const char *[]){ "csi1_src" },
407 .num_parents = 1,
408 .name = "csi1_clk",
409 .ops = &clk_branch_ops,
410 .flags = CLK_SET_RATE_PARENT,
411 },
412 },
413};
414
415static struct clk_branch csi1_phy_clk = {
416 .halt_reg = 0x01e8,
417 .halt_bit = 10,
418 .clkr = {
419 .enable_reg = 0x0024,
420 .enable_mask = BIT(8),
421 .hw.init = &(struct clk_init_data){
422 .parent_names = (const char *[]){ "csi1_src" },
423 .num_parents = 1,
424 .name = "csi1_phy_clk",
425 .ops = &clk_branch_ops,
426 .flags = CLK_SET_RATE_PARENT,
427 },
428 },
429};
430
431static struct clk_rcg csi2_src = {
432 .ns_reg = 0x0234,
433 .md_reg = 0x022c,
434 .mn = {
435 .mnctr_en_bit = 5,
436 .mnctr_reset_bit = 7,
437 .mnctr_mode_shift = 6,
438 .n_val_shift = 24,
439 .m_val_shift = 8,
440 .width = 8,
441 },
442 .p = {
443 .pre_div_shift = 14,
444 .pre_div_width = 2,
445 },
446 .s = {
447 .src_sel_shift = 0,
448 .parent_map = mmcc_pxo_pll8_pll2_map,
449 },
450 .freq_tbl = clk_tbl_csi,
451 .clkr = {
452 .enable_reg = 0x022c,
453 .enable_mask = BIT(2),
454 .hw.init = &(struct clk_init_data){
455 .name = "csi2_src",
456 .parent_names = mmcc_pxo_pll8_pll2,
457 .num_parents = 3,
458 .ops = &clk_rcg_ops,
459 },
460 },
461};
462
463static struct clk_branch csi2_clk = {
464 .halt_reg = 0x01cc,
465 .halt_bit = 29,
466 .clkr = {
467 .enable_reg = 0x022c,
468 .enable_mask = BIT(0),
469 .hw.init = &(struct clk_init_data){
470 .parent_names = (const char *[]){ "csi2_src" },
471 .num_parents = 1,
472 .name = "csi2_clk",
473 .ops = &clk_branch_ops,
474 .flags = CLK_SET_RATE_PARENT,
475 },
476 },
477};
478
479static struct clk_branch csi2_phy_clk = {
480 .halt_reg = 0x01e8,
481 .halt_bit = 29,
482 .clkr = {
483 .enable_reg = 0x022c,
484 .enable_mask = BIT(8),
485 .hw.init = &(struct clk_init_data){
486 .parent_names = (const char *[]){ "csi2_src" },
487 .num_parents = 1,
488 .name = "csi2_phy_clk",
489 .ops = &clk_branch_ops,
490 .flags = CLK_SET_RATE_PARENT,
491 },
492 },
493};
494
495struct clk_pix_rdi {
496 u32 s_reg;
497 u32 s_mask;
498 u32 s2_reg;
499 u32 s2_mask;
500 struct clk_regmap clkr;
501};
502
503#define to_clk_pix_rdi(_hw) \
504 container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
505
506static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
507{
508 int i;
509 int ret = 0;
510 u32 val;
511 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
512 struct clk *clk = hw->clk;
Stephen Boyd497295a2015-06-25 16:53:23 -0700513 int num_parents = clk_hw_get_num_parents(hw);
Stephen Boyd6d00b562014-01-15 10:47:29 -0800514
515 /*
516 * These clocks select three inputs via two muxes. One mux selects
517 * between csi0 and csi1 and the second mux selects between that mux's
518 * output and csi2. The source and destination selections for each
519 * mux must be clocking for the switch to succeed so just turn on
520 * all three sources because it's easier than figuring out what source
521 * needs to be on at what time.
522 */
523 for (i = 0; i < num_parents; i++) {
524 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
525 if (ret)
526 goto err;
527 }
528
529 if (index == 2)
530 val = rdi->s2_mask;
531 else
532 val = 0;
533 regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
534 /*
535 * Wait at least 6 cycles of slowest clock
536 * for the glitch-free MUX to fully switch sources.
537 */
538 udelay(1);
539
540 if (index == 1)
541 val = rdi->s_mask;
542 else
543 val = 0;
544 regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
545 /*
546 * Wait at least 6 cycles of slowest clock
547 * for the glitch-free MUX to fully switch sources.
548 */
549 udelay(1);
550
551err:
552 for (i--; i >= 0; i--)
553 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
554
555 return ret;
556}
557
558static u8 pix_rdi_get_parent(struct clk_hw *hw)
559{
560 u32 val;
561 struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
562
563
564 regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
565 if (val & rdi->s2_mask)
566 return 2;
567
568 regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
569 if (val & rdi->s_mask)
570 return 1;
571
572 return 0;
573}
574
575static const struct clk_ops clk_ops_pix_rdi = {
576 .enable = clk_enable_regmap,
577 .disable = clk_disable_regmap,
578 .set_parent = pix_rdi_set_parent,
579 .get_parent = pix_rdi_get_parent,
580 .determine_rate = __clk_mux_determine_rate,
581};
582
Georgi Djakovadb11a42015-07-06 16:51:30 +0300583static const char * const pix_rdi_parents[] = {
Stephen Boyd6d00b562014-01-15 10:47:29 -0800584 "csi0_clk",
585 "csi1_clk",
586 "csi2_clk",
587};
588
589static struct clk_pix_rdi csi_pix_clk = {
590 .s_reg = 0x0058,
591 .s_mask = BIT(25),
592 .s2_reg = 0x0238,
593 .s2_mask = BIT(13),
594 .clkr = {
595 .enable_reg = 0x0058,
596 .enable_mask = BIT(26),
597 .hw.init = &(struct clk_init_data){
598 .name = "csi_pix_clk",
599 .parent_names = pix_rdi_parents,
600 .num_parents = 3,
601 .ops = &clk_ops_pix_rdi,
602 },
603 },
604};
605
606static struct clk_pix_rdi csi_pix1_clk = {
607 .s_reg = 0x0238,
608 .s_mask = BIT(8),
609 .s2_reg = 0x0238,
610 .s2_mask = BIT(9),
611 .clkr = {
612 .enable_reg = 0x0238,
613 .enable_mask = BIT(10),
614 .hw.init = &(struct clk_init_data){
615 .name = "csi_pix1_clk",
616 .parent_names = pix_rdi_parents,
617 .num_parents = 3,
618 .ops = &clk_ops_pix_rdi,
619 },
620 },
621};
622
623static struct clk_pix_rdi csi_rdi_clk = {
624 .s_reg = 0x0058,
625 .s_mask = BIT(12),
626 .s2_reg = 0x0238,
627 .s2_mask = BIT(12),
628 .clkr = {
629 .enable_reg = 0x0058,
630 .enable_mask = BIT(13),
631 .hw.init = &(struct clk_init_data){
632 .name = "csi_rdi_clk",
633 .parent_names = pix_rdi_parents,
634 .num_parents = 3,
635 .ops = &clk_ops_pix_rdi,
636 },
637 },
638};
639
640static struct clk_pix_rdi csi_rdi1_clk = {
641 .s_reg = 0x0238,
642 .s_mask = BIT(0),
643 .s2_reg = 0x0238,
644 .s2_mask = BIT(1),
645 .clkr = {
646 .enable_reg = 0x0238,
647 .enable_mask = BIT(2),
648 .hw.init = &(struct clk_init_data){
649 .name = "csi_rdi1_clk",
650 .parent_names = pix_rdi_parents,
651 .num_parents = 3,
652 .ops = &clk_ops_pix_rdi,
653 },
654 },
655};
656
657static struct clk_pix_rdi csi_rdi2_clk = {
658 .s_reg = 0x0238,
659 .s_mask = BIT(4),
660 .s2_reg = 0x0238,
661 .s2_mask = BIT(5),
662 .clkr = {
663 .enable_reg = 0x0238,
664 .enable_mask = BIT(6),
665 .hw.init = &(struct clk_init_data){
666 .name = "csi_rdi2_clk",
667 .parent_names = pix_rdi_parents,
668 .num_parents = 3,
669 .ops = &clk_ops_pix_rdi,
670 },
671 },
672};
673
674static struct freq_tbl clk_tbl_csiphytimer[] = {
675 { 85330000, P_PLL8, 1, 2, 9 },
676 { 177780000, P_PLL2, 1, 2, 9 },
677 { }
678};
679
680static struct clk_rcg csiphytimer_src = {
681 .ns_reg = 0x0168,
682 .md_reg = 0x0164,
683 .mn = {
684 .mnctr_en_bit = 5,
685 .mnctr_reset_bit = 8,
686 .reset_in_cc = true,
687 .mnctr_mode_shift = 6,
688 .n_val_shift = 24,
689 .m_val_shift = 8,
690 .width = 8,
691 },
692 .p = {
693 .pre_div_shift = 14,
694 .pre_div_width = 2,
695 },
696 .s = {
697 .src_sel_shift = 0,
698 .parent_map = mmcc_pxo_pll8_pll2_map,
699 },
700 .freq_tbl = clk_tbl_csiphytimer,
701 .clkr = {
702 .enable_reg = 0x0160,
703 .enable_mask = BIT(2),
704 .hw.init = &(struct clk_init_data){
705 .name = "csiphytimer_src",
706 .parent_names = mmcc_pxo_pll8_pll2,
707 .num_parents = 3,
708 .ops = &clk_rcg_ops,
709 },
710 },
711};
712
Georgi Djakovadb11a42015-07-06 16:51:30 +0300713static const char * const csixphy_timer_src[] = { "csiphytimer_src" };
Stephen Boyd6d00b562014-01-15 10:47:29 -0800714
715static struct clk_branch csiphy0_timer_clk = {
716 .halt_reg = 0x01e8,
717 .halt_bit = 17,
718 .clkr = {
719 .enable_reg = 0x0160,
720 .enable_mask = BIT(0),
721 .hw.init = &(struct clk_init_data){
722 .parent_names = csixphy_timer_src,
723 .num_parents = 1,
724 .name = "csiphy0_timer_clk",
725 .ops = &clk_branch_ops,
726 .flags = CLK_SET_RATE_PARENT,
727 },
728 },
729};
730
731static struct clk_branch csiphy1_timer_clk = {
732 .halt_reg = 0x01e8,
733 .halt_bit = 18,
734 .clkr = {
735 .enable_reg = 0x0160,
736 .enable_mask = BIT(9),
737 .hw.init = &(struct clk_init_data){
738 .parent_names = csixphy_timer_src,
739 .num_parents = 1,
740 .name = "csiphy1_timer_clk",
741 .ops = &clk_branch_ops,
742 .flags = CLK_SET_RATE_PARENT,
743 },
744 },
745};
746
747static struct clk_branch csiphy2_timer_clk = {
748 .halt_reg = 0x01e8,
749 .halt_bit = 30,
750 .clkr = {
751 .enable_reg = 0x0160,
752 .enable_mask = BIT(11),
753 .hw.init = &(struct clk_init_data){
754 .parent_names = csixphy_timer_src,
755 .num_parents = 1,
756 .name = "csiphy2_timer_clk",
757 .ops = &clk_branch_ops,
758 .flags = CLK_SET_RATE_PARENT,
759 },
760 },
761};
762
763static struct freq_tbl clk_tbl_gfx2d[] = {
Stephen Boydff207832014-07-08 18:36:06 -0700764 F_MN( 27000000, P_PXO, 1, 0),
765 F_MN( 48000000, P_PLL8, 1, 8),
766 F_MN( 54857000, P_PLL8, 1, 7),
767 F_MN( 64000000, P_PLL8, 1, 6),
768 F_MN( 76800000, P_PLL8, 1, 5),
769 F_MN( 96000000, P_PLL8, 1, 4),
770 F_MN(128000000, P_PLL8, 1, 3),
771 F_MN(145455000, P_PLL2, 2, 11),
772 F_MN(160000000, P_PLL2, 1, 5),
773 F_MN(177778000, P_PLL2, 2, 9),
774 F_MN(200000000, P_PLL2, 1, 4),
775 F_MN(228571000, P_PLL2, 2, 7),
Stephen Boyd6d00b562014-01-15 10:47:29 -0800776 { }
777};
778
779static struct clk_dyn_rcg gfx2d0_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -0700780 .ns_reg[0] = 0x0070,
781 .ns_reg[1] = 0x0070,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800782 .md_reg[0] = 0x0064,
783 .md_reg[1] = 0x0068,
Stephen Boyd229fd4a2014-04-28 15:59:16 -0700784 .bank_reg = 0x0060,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800785 .mn[0] = {
786 .mnctr_en_bit = 8,
787 .mnctr_reset_bit = 25,
788 .mnctr_mode_shift = 9,
789 .n_val_shift = 20,
790 .m_val_shift = 4,
791 .width = 4,
792 },
793 .mn[1] = {
794 .mnctr_en_bit = 5,
795 .mnctr_reset_bit = 24,
796 .mnctr_mode_shift = 6,
797 .n_val_shift = 16,
798 .m_val_shift = 4,
799 .width = 4,
800 },
801 .s[0] = {
802 .src_sel_shift = 3,
803 .parent_map = mmcc_pxo_pll8_pll2_map,
804 },
805 .s[1] = {
806 .src_sel_shift = 0,
807 .parent_map = mmcc_pxo_pll8_pll2_map,
808 },
809 .mux_sel_bit = 11,
810 .freq_tbl = clk_tbl_gfx2d,
811 .clkr = {
812 .enable_reg = 0x0060,
813 .enable_mask = BIT(2),
814 .hw.init = &(struct clk_init_data){
815 .name = "gfx2d0_src",
816 .parent_names = mmcc_pxo_pll8_pll2,
817 .num_parents = 3,
818 .ops = &clk_dyn_rcg_ops,
819 },
820 },
821};
822
823static struct clk_branch gfx2d0_clk = {
824 .halt_reg = 0x01c8,
825 .halt_bit = 9,
826 .clkr = {
827 .enable_reg = 0x0060,
828 .enable_mask = BIT(0),
829 .hw.init = &(struct clk_init_data){
830 .name = "gfx2d0_clk",
831 .parent_names = (const char *[]){ "gfx2d0_src" },
832 .num_parents = 1,
833 .ops = &clk_branch_ops,
834 .flags = CLK_SET_RATE_PARENT,
835 },
836 },
837};
838
839static struct clk_dyn_rcg gfx2d1_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -0700840 .ns_reg[0] = 0x007c,
841 .ns_reg[1] = 0x007c,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800842 .md_reg[0] = 0x0078,
843 .md_reg[1] = 0x006c,
Stephen Boyd229fd4a2014-04-28 15:59:16 -0700844 .bank_reg = 0x0074,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800845 .mn[0] = {
846 .mnctr_en_bit = 8,
847 .mnctr_reset_bit = 25,
848 .mnctr_mode_shift = 9,
849 .n_val_shift = 20,
850 .m_val_shift = 4,
851 .width = 4,
852 },
853 .mn[1] = {
854 .mnctr_en_bit = 5,
855 .mnctr_reset_bit = 24,
856 .mnctr_mode_shift = 6,
857 .n_val_shift = 16,
858 .m_val_shift = 4,
859 .width = 4,
860 },
861 .s[0] = {
862 .src_sel_shift = 3,
863 .parent_map = mmcc_pxo_pll8_pll2_map,
864 },
865 .s[1] = {
866 .src_sel_shift = 0,
867 .parent_map = mmcc_pxo_pll8_pll2_map,
868 },
869 .mux_sel_bit = 11,
870 .freq_tbl = clk_tbl_gfx2d,
871 .clkr = {
872 .enable_reg = 0x0074,
873 .enable_mask = BIT(2),
874 .hw.init = &(struct clk_init_data){
875 .name = "gfx2d1_src",
876 .parent_names = mmcc_pxo_pll8_pll2,
877 .num_parents = 3,
878 .ops = &clk_dyn_rcg_ops,
879 },
880 },
881};
882
883static struct clk_branch gfx2d1_clk = {
884 .halt_reg = 0x01c8,
885 .halt_bit = 14,
886 .clkr = {
887 .enable_reg = 0x0074,
888 .enable_mask = BIT(0),
889 .hw.init = &(struct clk_init_data){
890 .name = "gfx2d1_clk",
891 .parent_names = (const char *[]){ "gfx2d1_src" },
892 .num_parents = 1,
893 .ops = &clk_branch_ops,
894 .flags = CLK_SET_RATE_PARENT,
895 },
896 },
897};
898
899static struct freq_tbl clk_tbl_gfx3d[] = {
Stephen Boydff207832014-07-08 18:36:06 -0700900 F_MN( 27000000, P_PXO, 1, 0),
901 F_MN( 48000000, P_PLL8, 1, 8),
902 F_MN( 54857000, P_PLL8, 1, 7),
903 F_MN( 64000000, P_PLL8, 1, 6),
904 F_MN( 76800000, P_PLL8, 1, 5),
905 F_MN( 96000000, P_PLL8, 1, 4),
906 F_MN(128000000, P_PLL8, 1, 3),
907 F_MN(145455000, P_PLL2, 2, 11),
908 F_MN(160000000, P_PLL2, 1, 5),
909 F_MN(177778000, P_PLL2, 2, 9),
910 F_MN(200000000, P_PLL2, 1, 4),
911 F_MN(228571000, P_PLL2, 2, 7),
912 F_MN(266667000, P_PLL2, 1, 3),
913 F_MN(300000000, P_PLL3, 1, 4),
914 F_MN(320000000, P_PLL2, 2, 5),
915 F_MN(400000000, P_PLL2, 1, 2),
Stephen Boyd6d00b562014-01-15 10:47:29 -0800916 { }
917};
918
Stephen Boyde216ce62014-07-15 14:52:22 -0700919static struct freq_tbl clk_tbl_gfx3d_8064[] = {
920 F_MN( 27000000, P_PXO, 0, 0),
921 F_MN( 48000000, P_PLL8, 1, 8),
922 F_MN( 54857000, P_PLL8, 1, 7),
923 F_MN( 64000000, P_PLL8, 1, 6),
924 F_MN( 76800000, P_PLL8, 1, 5),
925 F_MN( 96000000, P_PLL8, 1, 4),
926 F_MN(128000000, P_PLL8, 1, 3),
927 F_MN(145455000, P_PLL2, 2, 11),
928 F_MN(160000000, P_PLL2, 1, 5),
929 F_MN(177778000, P_PLL2, 2, 9),
930 F_MN(192000000, P_PLL8, 1, 2),
931 F_MN(200000000, P_PLL2, 1, 4),
932 F_MN(228571000, P_PLL2, 2, 7),
933 F_MN(266667000, P_PLL2, 1, 3),
934 F_MN(320000000, P_PLL2, 2, 5),
935 F_MN(400000000, P_PLL2, 1, 2),
936 F_MN(450000000, P_PLL15, 1, 2),
Stephen Boyd6d00b562014-01-15 10:47:29 -0800937 { }
938};
939
940static struct clk_dyn_rcg gfx3d_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -0700941 .ns_reg[0] = 0x008c,
942 .ns_reg[1] = 0x008c,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800943 .md_reg[0] = 0x0084,
944 .md_reg[1] = 0x0088,
Stephen Boyd229fd4a2014-04-28 15:59:16 -0700945 .bank_reg = 0x0080,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800946 .mn[0] = {
947 .mnctr_en_bit = 8,
948 .mnctr_reset_bit = 25,
949 .mnctr_mode_shift = 9,
950 .n_val_shift = 18,
951 .m_val_shift = 4,
952 .width = 4,
953 },
954 .mn[1] = {
955 .mnctr_en_bit = 5,
956 .mnctr_reset_bit = 24,
957 .mnctr_mode_shift = 6,
958 .n_val_shift = 14,
959 .m_val_shift = 4,
960 .width = 4,
961 },
962 .s[0] = {
963 .src_sel_shift = 3,
964 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
965 },
966 .s[1] = {
967 .src_sel_shift = 0,
968 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
969 },
970 .mux_sel_bit = 11,
971 .freq_tbl = clk_tbl_gfx3d,
972 .clkr = {
973 .enable_reg = 0x0080,
974 .enable_mask = BIT(2),
975 .hw.init = &(struct clk_init_data){
976 .name = "gfx3d_src",
977 .parent_names = mmcc_pxo_pll8_pll2_pll3,
Stephen Boydff207832014-07-08 18:36:06 -0700978 .num_parents = 4,
Stephen Boyd6d00b562014-01-15 10:47:29 -0800979 .ops = &clk_dyn_rcg_ops,
980 },
981 },
982};
983
Stephen Boyde216ce62014-07-15 14:52:22 -0700984static const struct clk_init_data gfx3d_8064_init = {
985 .name = "gfx3d_src",
986 .parent_names = mmcc_pxo_pll8_pll2_pll15,
987 .num_parents = 4,
988 .ops = &clk_dyn_rcg_ops,
989};
990
Stephen Boyd6d00b562014-01-15 10:47:29 -0800991static struct clk_branch gfx3d_clk = {
992 .halt_reg = 0x01c8,
993 .halt_bit = 4,
994 .clkr = {
995 .enable_reg = 0x0080,
996 .enable_mask = BIT(0),
997 .hw.init = &(struct clk_init_data){
998 .name = "gfx3d_clk",
999 .parent_names = (const char *[]){ "gfx3d_src" },
1000 .num_parents = 1,
1001 .ops = &clk_branch_ops,
1002 .flags = CLK_SET_RATE_PARENT,
1003 },
1004 },
1005};
1006
Stephen Boyde216ce62014-07-15 14:52:22 -07001007static struct freq_tbl clk_tbl_vcap[] = {
1008 F_MN( 27000000, P_PXO, 0, 0),
1009 F_MN( 54860000, P_PLL8, 1, 7),
1010 F_MN( 64000000, P_PLL8, 1, 6),
1011 F_MN( 76800000, P_PLL8, 1, 5),
1012 F_MN(128000000, P_PLL8, 1, 3),
1013 F_MN(160000000, P_PLL2, 1, 5),
1014 F_MN(200000000, P_PLL2, 1, 4),
1015 { }
1016};
1017
1018static struct clk_dyn_rcg vcap_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001019 .ns_reg[0] = 0x021c,
1020 .ns_reg[1] = 0x021c,
Stephen Boyde216ce62014-07-15 14:52:22 -07001021 .md_reg[0] = 0x01ec,
1022 .md_reg[1] = 0x0218,
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001023 .bank_reg = 0x0178,
Stephen Boyde216ce62014-07-15 14:52:22 -07001024 .mn[0] = {
1025 .mnctr_en_bit = 8,
1026 .mnctr_reset_bit = 23,
1027 .mnctr_mode_shift = 9,
1028 .n_val_shift = 18,
1029 .m_val_shift = 4,
1030 .width = 4,
1031 },
1032 .mn[1] = {
1033 .mnctr_en_bit = 5,
1034 .mnctr_reset_bit = 22,
1035 .mnctr_mode_shift = 6,
1036 .n_val_shift = 14,
1037 .m_val_shift = 4,
1038 .width = 4,
1039 },
1040 .s[0] = {
1041 .src_sel_shift = 3,
1042 .parent_map = mmcc_pxo_pll8_pll2_map,
1043 },
1044 .s[1] = {
1045 .src_sel_shift = 0,
1046 .parent_map = mmcc_pxo_pll8_pll2_map,
1047 },
1048 .mux_sel_bit = 11,
1049 .freq_tbl = clk_tbl_vcap,
1050 .clkr = {
1051 .enable_reg = 0x0178,
1052 .enable_mask = BIT(2),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "vcap_src",
1055 .parent_names = mmcc_pxo_pll8_pll2,
1056 .num_parents = 3,
1057 .ops = &clk_dyn_rcg_ops,
1058 },
1059 },
1060};
1061
1062static struct clk_branch vcap_clk = {
1063 .halt_reg = 0x0240,
1064 .halt_bit = 15,
1065 .clkr = {
1066 .enable_reg = 0x0178,
1067 .enable_mask = BIT(0),
1068 .hw.init = &(struct clk_init_data){
1069 .name = "vcap_clk",
1070 .parent_names = (const char *[]){ "vcap_src" },
1071 .num_parents = 1,
1072 .ops = &clk_branch_ops,
1073 .flags = CLK_SET_RATE_PARENT,
1074 },
1075 },
1076};
1077
1078static struct clk_branch vcap_npl_clk = {
1079 .halt_reg = 0x0240,
1080 .halt_bit = 25,
1081 .clkr = {
1082 .enable_reg = 0x0178,
1083 .enable_mask = BIT(13),
1084 .hw.init = &(struct clk_init_data){
1085 .name = "vcap_npl_clk",
1086 .parent_names = (const char *[]){ "vcap_src" },
1087 .num_parents = 1,
1088 .ops = &clk_branch_ops,
1089 .flags = CLK_SET_RATE_PARENT,
1090 },
1091 },
1092};
1093
Stephen Boyd6d00b562014-01-15 10:47:29 -08001094static struct freq_tbl clk_tbl_ijpeg[] = {
1095 { 27000000, P_PXO, 1, 0, 0 },
1096 { 36570000, P_PLL8, 1, 2, 21 },
1097 { 54860000, P_PLL8, 7, 0, 0 },
1098 { 96000000, P_PLL8, 4, 0, 0 },
1099 { 109710000, P_PLL8, 1, 2, 7 },
1100 { 128000000, P_PLL8, 3, 0, 0 },
1101 { 153600000, P_PLL8, 1, 2, 5 },
1102 { 200000000, P_PLL2, 4, 0, 0 },
1103 { 228571000, P_PLL2, 1, 2, 7 },
1104 { 266667000, P_PLL2, 1, 1, 3 },
1105 { 320000000, P_PLL2, 1, 2, 5 },
1106 { }
1107};
1108
1109static struct clk_rcg ijpeg_src = {
1110 .ns_reg = 0x00a0,
1111 .md_reg = 0x009c,
1112 .mn = {
1113 .mnctr_en_bit = 5,
1114 .mnctr_reset_bit = 7,
1115 .mnctr_mode_shift = 6,
1116 .n_val_shift = 16,
1117 .m_val_shift = 8,
1118 .width = 8,
1119 },
1120 .p = {
1121 .pre_div_shift = 12,
1122 .pre_div_width = 2,
1123 },
1124 .s = {
1125 .src_sel_shift = 0,
1126 .parent_map = mmcc_pxo_pll8_pll2_map,
1127 },
1128 .freq_tbl = clk_tbl_ijpeg,
1129 .clkr = {
1130 .enable_reg = 0x0098,
1131 .enable_mask = BIT(2),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "ijpeg_src",
1134 .parent_names = mmcc_pxo_pll8_pll2,
1135 .num_parents = 3,
1136 .ops = &clk_rcg_ops,
1137 },
1138 },
1139};
1140
1141static struct clk_branch ijpeg_clk = {
1142 .halt_reg = 0x01c8,
1143 .halt_bit = 24,
1144 .clkr = {
1145 .enable_reg = 0x0098,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "ijpeg_clk",
1149 .parent_names = (const char *[]){ "ijpeg_src" },
1150 .num_parents = 1,
1151 .ops = &clk_branch_ops,
1152 .flags = CLK_SET_RATE_PARENT,
1153 },
1154 },
1155};
1156
1157static struct freq_tbl clk_tbl_jpegd[] = {
1158 { 64000000, P_PLL8, 6 },
1159 { 76800000, P_PLL8, 5 },
1160 { 96000000, P_PLL8, 4 },
1161 { 160000000, P_PLL2, 5 },
1162 { 200000000, P_PLL2, 4 },
1163 { }
1164};
1165
1166static struct clk_rcg jpegd_src = {
1167 .ns_reg = 0x00ac,
1168 .p = {
1169 .pre_div_shift = 12,
Stephen Boydff207832014-07-08 18:36:06 -07001170 .pre_div_width = 4,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001171 },
1172 .s = {
1173 .src_sel_shift = 0,
1174 .parent_map = mmcc_pxo_pll8_pll2_map,
1175 },
1176 .freq_tbl = clk_tbl_jpegd,
1177 .clkr = {
1178 .enable_reg = 0x00a4,
1179 .enable_mask = BIT(2),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "jpegd_src",
1182 .parent_names = mmcc_pxo_pll8_pll2,
1183 .num_parents = 3,
1184 .ops = &clk_rcg_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch jpegd_clk = {
1190 .halt_reg = 0x01c8,
1191 .halt_bit = 19,
1192 .clkr = {
1193 .enable_reg = 0x00a4,
1194 .enable_mask = BIT(0),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "jpegd_clk",
1197 .parent_names = (const char *[]){ "jpegd_src" },
1198 .num_parents = 1,
1199 .ops = &clk_branch_ops,
1200 .flags = CLK_SET_RATE_PARENT,
1201 },
1202 },
1203};
1204
1205static struct freq_tbl clk_tbl_mdp[] = {
1206 { 9600000, P_PLL8, 1, 1, 40 },
1207 { 13710000, P_PLL8, 1, 1, 28 },
1208 { 27000000, P_PXO, 1, 0, 0 },
1209 { 29540000, P_PLL8, 1, 1, 13 },
1210 { 34910000, P_PLL8, 1, 1, 11 },
1211 { 38400000, P_PLL8, 1, 1, 10 },
1212 { 59080000, P_PLL8, 1, 2, 13 },
1213 { 76800000, P_PLL8, 1, 1, 5 },
1214 { 85330000, P_PLL8, 1, 2, 9 },
1215 { 96000000, P_PLL8, 1, 1, 4 },
1216 { 128000000, P_PLL8, 1, 1, 3 },
1217 { 160000000, P_PLL2, 1, 1, 5 },
1218 { 177780000, P_PLL2, 1, 2, 9 },
1219 { 200000000, P_PLL2, 1, 1, 4 },
1220 { 228571000, P_PLL2, 1, 2, 7 },
1221 { 266667000, P_PLL2, 1, 1, 3 },
1222 { }
1223};
1224
1225static struct clk_dyn_rcg mdp_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001226 .ns_reg[0] = 0x00d0,
1227 .ns_reg[1] = 0x00d0,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001228 .md_reg[0] = 0x00c4,
1229 .md_reg[1] = 0x00c8,
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001230 .bank_reg = 0x00c0,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001231 .mn[0] = {
1232 .mnctr_en_bit = 8,
1233 .mnctr_reset_bit = 31,
1234 .mnctr_mode_shift = 9,
1235 .n_val_shift = 22,
1236 .m_val_shift = 8,
1237 .width = 8,
1238 },
1239 .mn[1] = {
1240 .mnctr_en_bit = 5,
1241 .mnctr_reset_bit = 30,
1242 .mnctr_mode_shift = 6,
1243 .n_val_shift = 14,
1244 .m_val_shift = 8,
1245 .width = 8,
1246 },
1247 .s[0] = {
1248 .src_sel_shift = 3,
1249 .parent_map = mmcc_pxo_pll8_pll2_map,
1250 },
1251 .s[1] = {
1252 .src_sel_shift = 0,
1253 .parent_map = mmcc_pxo_pll8_pll2_map,
1254 },
1255 .mux_sel_bit = 11,
1256 .freq_tbl = clk_tbl_mdp,
1257 .clkr = {
1258 .enable_reg = 0x00c0,
1259 .enable_mask = BIT(2),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "mdp_src",
1262 .parent_names = mmcc_pxo_pll8_pll2,
1263 .num_parents = 3,
1264 .ops = &clk_dyn_rcg_ops,
1265 },
1266 },
1267};
1268
1269static struct clk_branch mdp_clk = {
1270 .halt_reg = 0x01d0,
1271 .halt_bit = 10,
1272 .clkr = {
1273 .enable_reg = 0x00c0,
1274 .enable_mask = BIT(0),
1275 .hw.init = &(struct clk_init_data){
1276 .name = "mdp_clk",
1277 .parent_names = (const char *[]){ "mdp_src" },
1278 .num_parents = 1,
1279 .ops = &clk_branch_ops,
1280 .flags = CLK_SET_RATE_PARENT,
1281 },
1282 },
1283};
1284
1285static struct clk_branch mdp_lut_clk = {
1286 .halt_reg = 0x01e8,
1287 .halt_bit = 13,
1288 .clkr = {
1289 .enable_reg = 0x016c,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
Stephen Boydf87dfca2014-07-08 18:36:06 -07001292 .parent_names = (const char *[]){ "mdp_src" },
Stephen Boyd6d00b562014-01-15 10:47:29 -08001293 .num_parents = 1,
1294 .name = "mdp_lut_clk",
1295 .ops = &clk_branch_ops,
1296 .flags = CLK_SET_RATE_PARENT,
1297 },
1298 },
1299};
1300
1301static struct clk_branch mdp_vsync_clk = {
1302 .halt_reg = 0x01cc,
1303 .halt_bit = 22,
1304 .clkr = {
1305 .enable_reg = 0x0058,
1306 .enable_mask = BIT(6),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "mdp_vsync_clk",
1309 .parent_names = (const char *[]){ "pxo" },
1310 .num_parents = 1,
1311 .ops = &clk_branch_ops
1312 },
1313 },
1314};
1315
1316static struct freq_tbl clk_tbl_rot[] = {
1317 { 27000000, P_PXO, 1 },
1318 { 29540000, P_PLL8, 13 },
1319 { 32000000, P_PLL8, 12 },
1320 { 38400000, P_PLL8, 10 },
1321 { 48000000, P_PLL8, 8 },
1322 { 54860000, P_PLL8, 7 },
1323 { 64000000, P_PLL8, 6 },
1324 { 76800000, P_PLL8, 5 },
1325 { 96000000, P_PLL8, 4 },
1326 { 100000000, P_PLL2, 8 },
1327 { 114290000, P_PLL2, 7 },
1328 { 133330000, P_PLL2, 6 },
1329 { 160000000, P_PLL2, 5 },
1330 { 200000000, P_PLL2, 4 },
1331 { }
1332};
1333
1334static struct clk_dyn_rcg rot_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001335 .ns_reg[0] = 0x00e8,
1336 .ns_reg[1] = 0x00e8,
1337 .bank_reg = 0x00e8,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001338 .p[0] = {
1339 .pre_div_shift = 22,
1340 .pre_div_width = 4,
1341 },
1342 .p[1] = {
1343 .pre_div_shift = 26,
1344 .pre_div_width = 4,
1345 },
1346 .s[0] = {
1347 .src_sel_shift = 16,
1348 .parent_map = mmcc_pxo_pll8_pll2_map,
1349 },
1350 .s[1] = {
1351 .src_sel_shift = 19,
1352 .parent_map = mmcc_pxo_pll8_pll2_map,
1353 },
1354 .mux_sel_bit = 30,
1355 .freq_tbl = clk_tbl_rot,
1356 .clkr = {
1357 .enable_reg = 0x00e0,
1358 .enable_mask = BIT(2),
1359 .hw.init = &(struct clk_init_data){
1360 .name = "rot_src",
1361 .parent_names = mmcc_pxo_pll8_pll2,
1362 .num_parents = 3,
1363 .ops = &clk_dyn_rcg_ops,
1364 },
1365 },
1366};
1367
1368static struct clk_branch rot_clk = {
1369 .halt_reg = 0x01d0,
1370 .halt_bit = 15,
1371 .clkr = {
1372 .enable_reg = 0x00e0,
1373 .enable_mask = BIT(0),
1374 .hw.init = &(struct clk_init_data){
1375 .name = "rot_clk",
1376 .parent_names = (const char *[]){ "rot_src" },
1377 .num_parents = 1,
1378 .ops = &clk_branch_ops,
1379 .flags = CLK_SET_RATE_PARENT,
1380 },
1381 },
1382};
1383
Georgi Djakov293d2e972015-03-20 18:30:26 +02001384static const struct parent_map mmcc_pxo_hdmi_map[] = {
1385 { P_PXO, 0 },
1386 { P_HDMI_PLL, 3 }
Stephen Boyd6d00b562014-01-15 10:47:29 -08001387};
1388
Georgi Djakovadb11a42015-07-06 16:51:30 +03001389static const char * const mmcc_pxo_hdmi[] = {
Stephen Boyd6d00b562014-01-15 10:47:29 -08001390 "pxo",
1391 "hdmi_pll",
1392};
1393
1394static struct freq_tbl clk_tbl_tv[] = {
Stephen Boyd404c1ff2014-07-11 12:55:27 -07001395 { .src = P_HDMI_PLL, .pre_div = 1 },
Stephen Boyd6d00b562014-01-15 10:47:29 -08001396 { }
1397};
1398
1399static struct clk_rcg tv_src = {
1400 .ns_reg = 0x00f4,
1401 .md_reg = 0x00f0,
1402 .mn = {
1403 .mnctr_en_bit = 5,
1404 .mnctr_reset_bit = 7,
1405 .mnctr_mode_shift = 6,
1406 .n_val_shift = 16,
1407 .m_val_shift = 8,
1408 .width = 8,
1409 },
1410 .p = {
1411 .pre_div_shift = 14,
1412 .pre_div_width = 2,
1413 },
1414 .s = {
1415 .src_sel_shift = 0,
1416 .parent_map = mmcc_pxo_hdmi_map,
1417 },
1418 .freq_tbl = clk_tbl_tv,
1419 .clkr = {
1420 .enable_reg = 0x00ec,
1421 .enable_mask = BIT(2),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "tv_src",
1424 .parent_names = mmcc_pxo_hdmi,
1425 .num_parents = 2,
Stephen Boyd404c1ff2014-07-11 12:55:27 -07001426 .ops = &clk_rcg_bypass_ops,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001427 .flags = CLK_SET_RATE_PARENT,
1428 },
1429 },
1430};
1431
Georgi Djakovadb11a42015-07-06 16:51:30 +03001432static const char * const tv_src_name[] = { "tv_src" };
Stephen Boyd6d00b562014-01-15 10:47:29 -08001433
1434static struct clk_branch tv_enc_clk = {
1435 .halt_reg = 0x01d4,
1436 .halt_bit = 9,
1437 .clkr = {
1438 .enable_reg = 0x00ec,
1439 .enable_mask = BIT(8),
1440 .hw.init = &(struct clk_init_data){
1441 .parent_names = tv_src_name,
1442 .num_parents = 1,
1443 .name = "tv_enc_clk",
1444 .ops = &clk_branch_ops,
1445 .flags = CLK_SET_RATE_PARENT,
1446 },
1447 },
1448};
1449
1450static struct clk_branch tv_dac_clk = {
1451 .halt_reg = 0x01d4,
1452 .halt_bit = 10,
1453 .clkr = {
1454 .enable_reg = 0x00ec,
1455 .enable_mask = BIT(10),
1456 .hw.init = &(struct clk_init_data){
1457 .parent_names = tv_src_name,
1458 .num_parents = 1,
1459 .name = "tv_dac_clk",
1460 .ops = &clk_branch_ops,
1461 .flags = CLK_SET_RATE_PARENT,
1462 },
1463 },
1464};
1465
1466static struct clk_branch mdp_tv_clk = {
1467 .halt_reg = 0x01d4,
1468 .halt_bit = 12,
1469 .clkr = {
1470 .enable_reg = 0x00ec,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(struct clk_init_data){
1473 .parent_names = tv_src_name,
1474 .num_parents = 1,
1475 .name = "mdp_tv_clk",
1476 .ops = &clk_branch_ops,
1477 .flags = CLK_SET_RATE_PARENT,
1478 },
1479 },
1480};
1481
1482static struct clk_branch hdmi_tv_clk = {
1483 .halt_reg = 0x01d4,
1484 .halt_bit = 11,
1485 .clkr = {
1486 .enable_reg = 0x00ec,
1487 .enable_mask = BIT(12),
1488 .hw.init = &(struct clk_init_data){
1489 .parent_names = tv_src_name,
1490 .num_parents = 1,
1491 .name = "hdmi_tv_clk",
1492 .ops = &clk_branch_ops,
1493 .flags = CLK_SET_RATE_PARENT,
1494 },
1495 },
1496};
1497
Stephen Boyde216ce62014-07-15 14:52:22 -07001498static struct clk_branch rgb_tv_clk = {
1499 .halt_reg = 0x0240,
1500 .halt_bit = 27,
1501 .clkr = {
1502 .enable_reg = 0x0124,
1503 .enable_mask = BIT(14),
1504 .hw.init = &(struct clk_init_data){
1505 .parent_names = tv_src_name,
1506 .num_parents = 1,
1507 .name = "rgb_tv_clk",
1508 .ops = &clk_branch_ops,
1509 .flags = CLK_SET_RATE_PARENT,
1510 },
1511 },
1512};
1513
1514static struct clk_branch npl_tv_clk = {
1515 .halt_reg = 0x0240,
1516 .halt_bit = 26,
1517 .clkr = {
1518 .enable_reg = 0x0124,
1519 .enable_mask = BIT(16),
1520 .hw.init = &(struct clk_init_data){
1521 .parent_names = tv_src_name,
1522 .num_parents = 1,
1523 .name = "npl_tv_clk",
1524 .ops = &clk_branch_ops,
1525 .flags = CLK_SET_RATE_PARENT,
1526 },
1527 },
1528};
1529
Stephen Boyd6d00b562014-01-15 10:47:29 -08001530static struct clk_branch hdmi_app_clk = {
1531 .halt_reg = 0x01cc,
1532 .halt_bit = 25,
1533 .clkr = {
1534 .enable_reg = 0x005c,
1535 .enable_mask = BIT(11),
1536 .hw.init = &(struct clk_init_data){
1537 .parent_names = (const char *[]){ "pxo" },
1538 .num_parents = 1,
1539 .name = "hdmi_app_clk",
1540 .ops = &clk_branch_ops,
1541 },
1542 },
1543};
1544
1545static struct freq_tbl clk_tbl_vcodec[] = {
Stephen Boydff207832014-07-08 18:36:06 -07001546 F_MN( 27000000, P_PXO, 1, 0),
1547 F_MN( 32000000, P_PLL8, 1, 12),
1548 F_MN( 48000000, P_PLL8, 1, 8),
1549 F_MN( 54860000, P_PLL8, 1, 7),
1550 F_MN( 96000000, P_PLL8, 1, 4),
1551 F_MN(133330000, P_PLL2, 1, 6),
1552 F_MN(200000000, P_PLL2, 1, 4),
1553 F_MN(228570000, P_PLL2, 2, 7),
1554 F_MN(266670000, P_PLL2, 1, 3),
Stephen Boyd6d00b562014-01-15 10:47:29 -08001555 { }
1556};
1557
1558static struct clk_dyn_rcg vcodec_src = {
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001559 .ns_reg[0] = 0x0100,
1560 .ns_reg[1] = 0x0100,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001561 .md_reg[0] = 0x00fc,
1562 .md_reg[1] = 0x0128,
Stephen Boyd229fd4a2014-04-28 15:59:16 -07001563 .bank_reg = 0x00f8,
Stephen Boyd6d00b562014-01-15 10:47:29 -08001564 .mn[0] = {
1565 .mnctr_en_bit = 5,
1566 .mnctr_reset_bit = 31,
1567 .mnctr_mode_shift = 6,
1568 .n_val_shift = 11,
1569 .m_val_shift = 8,
1570 .width = 8,
1571 },
1572 .mn[1] = {
1573 .mnctr_en_bit = 10,
1574 .mnctr_reset_bit = 30,
1575 .mnctr_mode_shift = 11,
1576 .n_val_shift = 19,
1577 .m_val_shift = 8,
1578 .width = 8,
1579 },
1580 .s[0] = {
1581 .src_sel_shift = 27,
1582 .parent_map = mmcc_pxo_pll8_pll2_map,
1583 },
1584 .s[1] = {
1585 .src_sel_shift = 0,
1586 .parent_map = mmcc_pxo_pll8_pll2_map,
1587 },
1588 .mux_sel_bit = 13,
1589 .freq_tbl = clk_tbl_vcodec,
1590 .clkr = {
1591 .enable_reg = 0x00f8,
1592 .enable_mask = BIT(2),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "vcodec_src",
1595 .parent_names = mmcc_pxo_pll8_pll2,
1596 .num_parents = 3,
1597 .ops = &clk_dyn_rcg_ops,
1598 },
1599 },
1600};
1601
1602static struct clk_branch vcodec_clk = {
1603 .halt_reg = 0x01d0,
1604 .halt_bit = 29,
1605 .clkr = {
1606 .enable_reg = 0x00f8,
1607 .enable_mask = BIT(0),
1608 .hw.init = &(struct clk_init_data){
1609 .name = "vcodec_clk",
1610 .parent_names = (const char *[]){ "vcodec_src" },
1611 .num_parents = 1,
1612 .ops = &clk_branch_ops,
1613 .flags = CLK_SET_RATE_PARENT,
1614 },
1615 },
1616};
1617
1618static struct freq_tbl clk_tbl_vpe[] = {
1619 { 27000000, P_PXO, 1 },
1620 { 34909000, P_PLL8, 11 },
1621 { 38400000, P_PLL8, 10 },
1622 { 64000000, P_PLL8, 6 },
1623 { 76800000, P_PLL8, 5 },
1624 { 96000000, P_PLL8, 4 },
1625 { 100000000, P_PLL2, 8 },
1626 { 160000000, P_PLL2, 5 },
1627 { }
1628};
1629
1630static struct clk_rcg vpe_src = {
1631 .ns_reg = 0x0118,
1632 .p = {
1633 .pre_div_shift = 12,
1634 .pre_div_width = 4,
1635 },
1636 .s = {
1637 .src_sel_shift = 0,
1638 .parent_map = mmcc_pxo_pll8_pll2_map,
1639 },
1640 .freq_tbl = clk_tbl_vpe,
1641 .clkr = {
1642 .enable_reg = 0x0110,
1643 .enable_mask = BIT(2),
1644 .hw.init = &(struct clk_init_data){
1645 .name = "vpe_src",
1646 .parent_names = mmcc_pxo_pll8_pll2,
1647 .num_parents = 3,
1648 .ops = &clk_rcg_ops,
1649 },
1650 },
1651};
1652
1653static struct clk_branch vpe_clk = {
1654 .halt_reg = 0x01c8,
1655 .halt_bit = 28,
1656 .clkr = {
1657 .enable_reg = 0x0110,
1658 .enable_mask = BIT(0),
1659 .hw.init = &(struct clk_init_data){
1660 .name = "vpe_clk",
1661 .parent_names = (const char *[]){ "vpe_src" },
1662 .num_parents = 1,
1663 .ops = &clk_branch_ops,
1664 .flags = CLK_SET_RATE_PARENT,
1665 },
1666 },
1667};
1668
1669static struct freq_tbl clk_tbl_vfe[] = {
1670 { 13960000, P_PLL8, 1, 2, 55 },
1671 { 27000000, P_PXO, 1, 0, 0 },
1672 { 36570000, P_PLL8, 1, 2, 21 },
1673 { 38400000, P_PLL8, 2, 1, 5 },
1674 { 45180000, P_PLL8, 1, 2, 17 },
1675 { 48000000, P_PLL8, 2, 1, 4 },
1676 { 54860000, P_PLL8, 1, 1, 7 },
1677 { 64000000, P_PLL8, 2, 1, 3 },
1678 { 76800000, P_PLL8, 1, 1, 5 },
1679 { 96000000, P_PLL8, 2, 1, 2 },
1680 { 109710000, P_PLL8, 1, 2, 7 },
1681 { 128000000, P_PLL8, 1, 1, 3 },
1682 { 153600000, P_PLL8, 1, 2, 5 },
1683 { 200000000, P_PLL2, 2, 1, 2 },
1684 { 228570000, P_PLL2, 1, 2, 7 },
1685 { 266667000, P_PLL2, 1, 1, 3 },
1686 { 320000000, P_PLL2, 1, 2, 5 },
1687 { }
1688};
1689
1690static struct clk_rcg vfe_src = {
1691 .ns_reg = 0x0108,
1692 .mn = {
1693 .mnctr_en_bit = 5,
1694 .mnctr_reset_bit = 7,
1695 .mnctr_mode_shift = 6,
1696 .n_val_shift = 16,
1697 .m_val_shift = 8,
1698 .width = 8,
1699 },
1700 .p = {
1701 .pre_div_shift = 10,
1702 .pre_div_width = 1,
1703 },
1704 .s = {
1705 .src_sel_shift = 0,
1706 .parent_map = mmcc_pxo_pll8_pll2_map,
1707 },
1708 .freq_tbl = clk_tbl_vfe,
1709 .clkr = {
1710 .enable_reg = 0x0104,
1711 .enable_mask = BIT(2),
1712 .hw.init = &(struct clk_init_data){
1713 .name = "vfe_src",
1714 .parent_names = mmcc_pxo_pll8_pll2,
1715 .num_parents = 3,
1716 .ops = &clk_rcg_ops,
1717 },
1718 },
1719};
1720
1721static struct clk_branch vfe_clk = {
1722 .halt_reg = 0x01cc,
1723 .halt_bit = 6,
1724 .clkr = {
1725 .enable_reg = 0x0104,
1726 .enable_mask = BIT(0),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "vfe_clk",
1729 .parent_names = (const char *[]){ "vfe_src" },
1730 .num_parents = 1,
1731 .ops = &clk_branch_ops,
1732 .flags = CLK_SET_RATE_PARENT,
1733 },
1734 },
1735};
1736
1737static struct clk_branch vfe_csi_clk = {
1738 .halt_reg = 0x01cc,
1739 .halt_bit = 8,
1740 .clkr = {
1741 .enable_reg = 0x0104,
1742 .enable_mask = BIT(12),
1743 .hw.init = &(struct clk_init_data){
1744 .parent_names = (const char *[]){ "vfe_src" },
1745 .num_parents = 1,
1746 .name = "vfe_csi_clk",
1747 .ops = &clk_branch_ops,
1748 .flags = CLK_SET_RATE_PARENT,
1749 },
1750 },
1751};
1752
1753static struct clk_branch gmem_axi_clk = {
1754 .halt_reg = 0x01d8,
1755 .halt_bit = 6,
1756 .clkr = {
1757 .enable_reg = 0x0018,
1758 .enable_mask = BIT(24),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "gmem_axi_clk",
1761 .ops = &clk_branch_ops,
1762 .flags = CLK_IS_ROOT,
1763 },
1764 },
1765};
1766
1767static struct clk_branch ijpeg_axi_clk = {
1768 .hwcg_reg = 0x0018,
1769 .hwcg_bit = 11,
1770 .halt_reg = 0x01d8,
1771 .halt_bit = 4,
1772 .clkr = {
1773 .enable_reg = 0x0018,
1774 .enable_mask = BIT(21),
1775 .hw.init = &(struct clk_init_data){
1776 .name = "ijpeg_axi_clk",
1777 .ops = &clk_branch_ops,
1778 .flags = CLK_IS_ROOT,
1779 },
1780 },
1781};
1782
1783static struct clk_branch mmss_imem_axi_clk = {
1784 .hwcg_reg = 0x0018,
1785 .hwcg_bit = 15,
1786 .halt_reg = 0x01d8,
1787 .halt_bit = 7,
1788 .clkr = {
1789 .enable_reg = 0x0018,
1790 .enable_mask = BIT(22),
1791 .hw.init = &(struct clk_init_data){
1792 .name = "mmss_imem_axi_clk",
1793 .ops = &clk_branch_ops,
1794 .flags = CLK_IS_ROOT,
1795 },
1796 },
1797};
1798
1799static struct clk_branch jpegd_axi_clk = {
1800 .halt_reg = 0x01d8,
1801 .halt_bit = 5,
1802 .clkr = {
1803 .enable_reg = 0x0018,
1804 .enable_mask = BIT(25),
1805 .hw.init = &(struct clk_init_data){
1806 .name = "jpegd_axi_clk",
1807 .ops = &clk_branch_ops,
1808 .flags = CLK_IS_ROOT,
1809 },
1810 },
1811};
1812
1813static struct clk_branch vcodec_axi_b_clk = {
1814 .hwcg_reg = 0x0114,
1815 .hwcg_bit = 22,
1816 .halt_reg = 0x01e8,
1817 .halt_bit = 25,
1818 .clkr = {
1819 .enable_reg = 0x0114,
1820 .enable_mask = BIT(23),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "vcodec_axi_b_clk",
1823 .ops = &clk_branch_ops,
1824 .flags = CLK_IS_ROOT,
1825 },
1826 },
1827};
1828
1829static struct clk_branch vcodec_axi_a_clk = {
1830 .hwcg_reg = 0x0114,
1831 .hwcg_bit = 24,
1832 .halt_reg = 0x01e8,
1833 .halt_bit = 26,
1834 .clkr = {
1835 .enable_reg = 0x0114,
1836 .enable_mask = BIT(25),
1837 .hw.init = &(struct clk_init_data){
1838 .name = "vcodec_axi_a_clk",
1839 .ops = &clk_branch_ops,
1840 .flags = CLK_IS_ROOT,
1841 },
1842 },
1843};
1844
1845static struct clk_branch vcodec_axi_clk = {
1846 .hwcg_reg = 0x0018,
1847 .hwcg_bit = 13,
1848 .halt_reg = 0x01d8,
1849 .halt_bit = 3,
1850 .clkr = {
1851 .enable_reg = 0x0018,
1852 .enable_mask = BIT(19),
1853 .hw.init = &(struct clk_init_data){
1854 .name = "vcodec_axi_clk",
1855 .ops = &clk_branch_ops,
1856 .flags = CLK_IS_ROOT,
1857 },
1858 },
1859};
1860
1861static struct clk_branch vfe_axi_clk = {
1862 .halt_reg = 0x01d8,
1863 .halt_bit = 0,
1864 .clkr = {
1865 .enable_reg = 0x0018,
1866 .enable_mask = BIT(18),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "vfe_axi_clk",
1869 .ops = &clk_branch_ops,
1870 .flags = CLK_IS_ROOT,
1871 },
1872 },
1873};
1874
1875static struct clk_branch mdp_axi_clk = {
1876 .hwcg_reg = 0x0018,
1877 .hwcg_bit = 16,
1878 .halt_reg = 0x01d8,
1879 .halt_bit = 8,
1880 .clkr = {
1881 .enable_reg = 0x0018,
1882 .enable_mask = BIT(23),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "mdp_axi_clk",
1885 .ops = &clk_branch_ops,
1886 .flags = CLK_IS_ROOT,
1887 },
1888 },
1889};
1890
1891static struct clk_branch rot_axi_clk = {
1892 .hwcg_reg = 0x0020,
1893 .hwcg_bit = 25,
1894 .halt_reg = 0x01d8,
1895 .halt_bit = 2,
1896 .clkr = {
1897 .enable_reg = 0x0020,
1898 .enable_mask = BIT(24),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "rot_axi_clk",
1901 .ops = &clk_branch_ops,
1902 .flags = CLK_IS_ROOT,
1903 },
1904 },
1905};
1906
Stephen Boyde216ce62014-07-15 14:52:22 -07001907static struct clk_branch vcap_axi_clk = {
1908 .halt_reg = 0x0240,
1909 .halt_bit = 20,
1910 .hwcg_reg = 0x0244,
1911 .hwcg_bit = 11,
1912 .clkr = {
1913 .enable_reg = 0x0244,
1914 .enable_mask = BIT(12),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "vcap_axi_clk",
1917 .ops = &clk_branch_ops,
1918 .flags = CLK_IS_ROOT,
1919 },
1920 },
1921};
1922
Stephen Boyd6d00b562014-01-15 10:47:29 -08001923static struct clk_branch vpe_axi_clk = {
1924 .hwcg_reg = 0x0020,
1925 .hwcg_bit = 27,
1926 .halt_reg = 0x01d8,
1927 .halt_bit = 1,
1928 .clkr = {
1929 .enable_reg = 0x0020,
1930 .enable_mask = BIT(26),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "vpe_axi_clk",
1933 .ops = &clk_branch_ops,
1934 .flags = CLK_IS_ROOT,
1935 },
1936 },
1937};
1938
1939static struct clk_branch gfx3d_axi_clk = {
1940 .hwcg_reg = 0x0244,
1941 .hwcg_bit = 24,
1942 .halt_reg = 0x0240,
1943 .halt_bit = 30,
1944 .clkr = {
1945 .enable_reg = 0x0244,
1946 .enable_mask = BIT(25),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "gfx3d_axi_clk",
1949 .ops = &clk_branch_ops,
1950 .flags = CLK_IS_ROOT,
1951 },
1952 },
1953};
1954
1955static struct clk_branch amp_ahb_clk = {
1956 .halt_reg = 0x01dc,
1957 .halt_bit = 18,
1958 .clkr = {
1959 .enable_reg = 0x0008,
1960 .enable_mask = BIT(24),
1961 .hw.init = &(struct clk_init_data){
1962 .name = "amp_ahb_clk",
1963 .ops = &clk_branch_ops,
1964 .flags = CLK_IS_ROOT,
1965 },
1966 },
1967};
1968
1969static struct clk_branch csi_ahb_clk = {
1970 .halt_reg = 0x01dc,
1971 .halt_bit = 16,
1972 .clkr = {
1973 .enable_reg = 0x0008,
1974 .enable_mask = BIT(7),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "csi_ahb_clk",
1977 .ops = &clk_branch_ops,
1978 .flags = CLK_IS_ROOT
1979 },
1980 },
1981};
1982
1983static struct clk_branch dsi_m_ahb_clk = {
1984 .halt_reg = 0x01dc,
1985 .halt_bit = 19,
1986 .clkr = {
1987 .enable_reg = 0x0008,
1988 .enable_mask = BIT(9),
1989 .hw.init = &(struct clk_init_data){
1990 .name = "dsi_m_ahb_clk",
1991 .ops = &clk_branch_ops,
1992 .flags = CLK_IS_ROOT,
1993 },
1994 },
1995};
1996
1997static struct clk_branch dsi_s_ahb_clk = {
1998 .hwcg_reg = 0x0038,
1999 .hwcg_bit = 20,
2000 .halt_reg = 0x01dc,
2001 .halt_bit = 21,
2002 .clkr = {
2003 .enable_reg = 0x0008,
2004 .enable_mask = BIT(18),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "dsi_s_ahb_clk",
2007 .ops = &clk_branch_ops,
2008 .flags = CLK_IS_ROOT,
2009 },
2010 },
2011};
2012
2013static struct clk_branch dsi2_m_ahb_clk = {
2014 .halt_reg = 0x01d8,
2015 .halt_bit = 18,
2016 .clkr = {
2017 .enable_reg = 0x0008,
2018 .enable_mask = BIT(17),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "dsi2_m_ahb_clk",
2021 .ops = &clk_branch_ops,
2022 .flags = CLK_IS_ROOT
2023 },
2024 },
2025};
2026
2027static struct clk_branch dsi2_s_ahb_clk = {
2028 .hwcg_reg = 0x0038,
2029 .hwcg_bit = 15,
2030 .halt_reg = 0x01dc,
2031 .halt_bit = 20,
2032 .clkr = {
2033 .enable_reg = 0x0008,
2034 .enable_mask = BIT(22),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "dsi2_s_ahb_clk",
2037 .ops = &clk_branch_ops,
2038 .flags = CLK_IS_ROOT,
2039 },
2040 },
2041};
2042
2043static struct clk_branch gfx2d0_ahb_clk = {
2044 .hwcg_reg = 0x0038,
2045 .hwcg_bit = 28,
2046 .halt_reg = 0x01dc,
2047 .halt_bit = 2,
2048 .clkr = {
2049 .enable_reg = 0x0008,
2050 .enable_mask = BIT(19),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gfx2d0_ahb_clk",
2053 .ops = &clk_branch_ops,
2054 .flags = CLK_IS_ROOT,
2055 },
2056 },
2057};
2058
2059static struct clk_branch gfx2d1_ahb_clk = {
2060 .hwcg_reg = 0x0038,
2061 .hwcg_bit = 29,
2062 .halt_reg = 0x01dc,
2063 .halt_bit = 3,
2064 .clkr = {
2065 .enable_reg = 0x0008,
2066 .enable_mask = BIT(2),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "gfx2d1_ahb_clk",
2069 .ops = &clk_branch_ops,
2070 .flags = CLK_IS_ROOT,
2071 },
2072 },
2073};
2074
2075static struct clk_branch gfx3d_ahb_clk = {
2076 .hwcg_reg = 0x0038,
2077 .hwcg_bit = 27,
2078 .halt_reg = 0x01dc,
2079 .halt_bit = 4,
2080 .clkr = {
2081 .enable_reg = 0x0008,
2082 .enable_mask = BIT(3),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gfx3d_ahb_clk",
2085 .ops = &clk_branch_ops,
2086 .flags = CLK_IS_ROOT,
2087 },
2088 },
2089};
2090
2091static struct clk_branch hdmi_m_ahb_clk = {
2092 .hwcg_reg = 0x0038,
2093 .hwcg_bit = 21,
2094 .halt_reg = 0x01dc,
2095 .halt_bit = 5,
2096 .clkr = {
2097 .enable_reg = 0x0008,
2098 .enable_mask = BIT(14),
2099 .hw.init = &(struct clk_init_data){
2100 .name = "hdmi_m_ahb_clk",
2101 .ops = &clk_branch_ops,
2102 .flags = CLK_IS_ROOT,
2103 },
2104 },
2105};
2106
2107static struct clk_branch hdmi_s_ahb_clk = {
2108 .hwcg_reg = 0x0038,
2109 .hwcg_bit = 22,
2110 .halt_reg = 0x01dc,
2111 .halt_bit = 6,
2112 .clkr = {
2113 .enable_reg = 0x0008,
2114 .enable_mask = BIT(4),
2115 .hw.init = &(struct clk_init_data){
2116 .name = "hdmi_s_ahb_clk",
2117 .ops = &clk_branch_ops,
2118 .flags = CLK_IS_ROOT,
2119 },
2120 },
2121};
2122
2123static struct clk_branch ijpeg_ahb_clk = {
2124 .halt_reg = 0x01dc,
2125 .halt_bit = 9,
2126 .clkr = {
2127 .enable_reg = 0x0008,
2128 .enable_mask = BIT(5),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "ijpeg_ahb_clk",
2131 .ops = &clk_branch_ops,
2132 .flags = CLK_IS_ROOT
2133 },
2134 },
2135};
2136
2137static struct clk_branch mmss_imem_ahb_clk = {
2138 .hwcg_reg = 0x0038,
2139 .hwcg_bit = 12,
2140 .halt_reg = 0x01dc,
2141 .halt_bit = 10,
2142 .clkr = {
2143 .enable_reg = 0x0008,
2144 .enable_mask = BIT(6),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "mmss_imem_ahb_clk",
2147 .ops = &clk_branch_ops,
2148 .flags = CLK_IS_ROOT
2149 },
2150 },
2151};
2152
2153static struct clk_branch jpegd_ahb_clk = {
2154 .halt_reg = 0x01dc,
2155 .halt_bit = 7,
2156 .clkr = {
2157 .enable_reg = 0x0008,
2158 .enable_mask = BIT(21),
2159 .hw.init = &(struct clk_init_data){
2160 .name = "jpegd_ahb_clk",
2161 .ops = &clk_branch_ops,
2162 .flags = CLK_IS_ROOT,
2163 },
2164 },
2165};
2166
2167static struct clk_branch mdp_ahb_clk = {
2168 .halt_reg = 0x01dc,
2169 .halt_bit = 11,
2170 .clkr = {
2171 .enable_reg = 0x0008,
2172 .enable_mask = BIT(10),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "mdp_ahb_clk",
2175 .ops = &clk_branch_ops,
2176 .flags = CLK_IS_ROOT,
2177 },
2178 },
2179};
2180
2181static struct clk_branch rot_ahb_clk = {
2182 .halt_reg = 0x01dc,
2183 .halt_bit = 13,
2184 .clkr = {
2185 .enable_reg = 0x0008,
2186 .enable_mask = BIT(12),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "rot_ahb_clk",
2189 .ops = &clk_branch_ops,
2190 .flags = CLK_IS_ROOT
2191 },
2192 },
2193};
2194
2195static struct clk_branch smmu_ahb_clk = {
2196 .hwcg_reg = 0x0008,
2197 .hwcg_bit = 26,
2198 .halt_reg = 0x01dc,
2199 .halt_bit = 22,
2200 .clkr = {
2201 .enable_reg = 0x0008,
2202 .enable_mask = BIT(15),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "smmu_ahb_clk",
2205 .ops = &clk_branch_ops,
2206 .flags = CLK_IS_ROOT,
2207 },
2208 },
2209};
2210
2211static struct clk_branch tv_enc_ahb_clk = {
2212 .halt_reg = 0x01dc,
2213 .halt_bit = 23,
2214 .clkr = {
2215 .enable_reg = 0x0008,
2216 .enable_mask = BIT(25),
2217 .hw.init = &(struct clk_init_data){
2218 .name = "tv_enc_ahb_clk",
2219 .ops = &clk_branch_ops,
2220 .flags = CLK_IS_ROOT,
2221 },
2222 },
2223};
2224
Stephen Boyde216ce62014-07-15 14:52:22 -07002225static struct clk_branch vcap_ahb_clk = {
2226 .halt_reg = 0x0240,
2227 .halt_bit = 23,
2228 .clkr = {
2229 .enable_reg = 0x0248,
2230 .enable_mask = BIT(1),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "vcap_ahb_clk",
2233 .ops = &clk_branch_ops,
2234 .flags = CLK_IS_ROOT,
2235 },
2236 },
2237};
2238
Stephen Boyd6d00b562014-01-15 10:47:29 -08002239static struct clk_branch vcodec_ahb_clk = {
2240 .hwcg_reg = 0x0038,
2241 .hwcg_bit = 26,
2242 .halt_reg = 0x01dc,
2243 .halt_bit = 12,
2244 .clkr = {
2245 .enable_reg = 0x0008,
2246 .enable_mask = BIT(11),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "vcodec_ahb_clk",
2249 .ops = &clk_branch_ops,
2250 .flags = CLK_IS_ROOT,
2251 },
2252 },
2253};
2254
2255static struct clk_branch vfe_ahb_clk = {
2256 .halt_reg = 0x01dc,
2257 .halt_bit = 14,
2258 .clkr = {
2259 .enable_reg = 0x0008,
2260 .enable_mask = BIT(13),
2261 .hw.init = &(struct clk_init_data){
2262 .name = "vfe_ahb_clk",
2263 .ops = &clk_branch_ops,
2264 .flags = CLK_IS_ROOT,
2265 },
2266 },
2267};
2268
2269static struct clk_branch vpe_ahb_clk = {
2270 .halt_reg = 0x01dc,
2271 .halt_bit = 15,
2272 .clkr = {
2273 .enable_reg = 0x0008,
2274 .enable_mask = BIT(16),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "vpe_ahb_clk",
2277 .ops = &clk_branch_ops,
2278 .flags = CLK_IS_ROOT,
2279 },
2280 },
2281};
2282
2283static struct clk_regmap *mmcc_msm8960_clks[] = {
2284 [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2285 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2286 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2287 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2288 [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2289 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2290 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2291 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2292 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2293 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2294 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2295 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2296 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2297 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2298 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2299 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2300 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2301 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2302 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2303 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2304 [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2305 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2306 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2307 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2308 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2309 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2310 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2311 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2312 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2313 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2314 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2315 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2316 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2317 [CSI0_SRC] = &csi0_src.clkr,
2318 [CSI0_CLK] = &csi0_clk.clkr,
2319 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2320 [CSI1_SRC] = &csi1_src.clkr,
2321 [CSI1_CLK] = &csi1_clk.clkr,
2322 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2323 [CSI2_SRC] = &csi2_src.clkr,
2324 [CSI2_CLK] = &csi2_clk.clkr,
2325 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2326 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2327 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2328 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2329 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2330 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2331 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2332 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2333 [GFX2D0_SRC] = &gfx2d0_src.clkr,
2334 [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2335 [GFX2D1_SRC] = &gfx2d1_src.clkr,
2336 [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2337 [GFX3D_SRC] = &gfx3d_src.clkr,
2338 [GFX3D_CLK] = &gfx3d_clk.clkr,
2339 [IJPEG_SRC] = &ijpeg_src.clkr,
2340 [IJPEG_CLK] = &ijpeg_clk.clkr,
2341 [JPEGD_SRC] = &jpegd_src.clkr,
2342 [JPEGD_CLK] = &jpegd_clk.clkr,
2343 [MDP_SRC] = &mdp_src.clkr,
2344 [MDP_CLK] = &mdp_clk.clkr,
2345 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2346 [ROT_SRC] = &rot_src.clkr,
2347 [ROT_CLK] = &rot_clk.clkr,
2348 [TV_ENC_CLK] = &tv_enc_clk.clkr,
2349 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2350 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2351 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2352 [TV_SRC] = &tv_src.clkr,
2353 [VCODEC_SRC] = &vcodec_src.clkr,
2354 [VCODEC_CLK] = &vcodec_clk.clkr,
2355 [VFE_SRC] = &vfe_src.clkr,
2356 [VFE_CLK] = &vfe_clk.clkr,
2357 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2358 [VPE_SRC] = &vpe_src.clkr,
2359 [VPE_CLK] = &vpe_clk.clkr,
2360 [CAMCLK0_SRC] = &camclk0_src.clkr,
2361 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2362 [CAMCLK1_SRC] = &camclk1_src.clkr,
2363 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2364 [CAMCLK2_SRC] = &camclk2_src.clkr,
2365 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2366 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2367 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2368 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2369 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2370 [PLL2] = &pll2.clkr,
2371};
2372
2373static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2374 [VPE_AXI_RESET] = { 0x0208, 15 },
2375 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2376 [MPD_AXI_RESET] = { 0x0208, 13 },
2377 [VFE_AXI_RESET] = { 0x0208, 9 },
2378 [SP_AXI_RESET] = { 0x0208, 8 },
2379 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2380 [ROT_AXI_RESET] = { 0x0208, 6 },
2381 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2382 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2383 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2384 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2385 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2386 [FAB_S0_AXI_RESET] = { 0x0208 },
2387 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2388 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2389 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2390 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2391 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2392 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2393 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2394 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2395 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2396 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2397 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2398 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2399 [APU_AHB_RESET] = { 0x020c, 18 },
2400 [CSI_AHB_RESET] = { 0x020c, 17 },
2401 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2402 [VPE_AHB_RESET] = { 0x020c, 14 },
2403 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2404 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2405 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2406 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2407 [HDMI_AHB_RESET] = { 0x020c, 9 },
2408 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2409 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2410 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2411 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2412 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2413 [MDP_AHB_RESET] = { 0x020c, 3 },
2414 [ROT_AHB_RESET] = { 0x020c, 2 },
2415 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2416 [VFE_AHB_RESET] = { 0x020c, 0 },
2417 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2418 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2419 [CSIPHY2_RESET] = { 0x0210, 29 },
2420 [CSI_PIX1_RESET] = { 0x0210, 28 },
2421 [CSIPHY0_RESET] = { 0x0210, 27 },
2422 [CSIPHY1_RESET] = { 0x0210, 26 },
2423 [DSI2_RESET] = { 0x0210, 25 },
2424 [VFE_CSI_RESET] = { 0x0210, 24 },
2425 [MDP_RESET] = { 0x0210, 21 },
2426 [AMP_RESET] = { 0x0210, 20 },
2427 [JPEGD_RESET] = { 0x0210, 19 },
2428 [CSI1_RESET] = { 0x0210, 18 },
2429 [VPE_RESET] = { 0x0210, 17 },
2430 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2431 [VFE_RESET] = { 0x0210, 15 },
2432 [GFX2D0_RESET] = { 0x0210, 14 },
2433 [GFX2D1_RESET] = { 0x0210, 13 },
2434 [GFX3D_RESET] = { 0x0210, 12 },
2435 [HDMI_RESET] = { 0x0210, 11 },
2436 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2437 [IJPEG_RESET] = { 0x0210, 9 },
2438 [CSI0_RESET] = { 0x0210, 8 },
2439 [DSI_RESET] = { 0x0210, 7 },
2440 [VCODEC_RESET] = { 0x0210, 6 },
2441 [MDP_TV_RESET] = { 0x0210, 4 },
2442 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2443 [ROT_RESET] = { 0x0210, 2 },
2444 [TV_HDMI_RESET] = { 0x0210, 1 },
2445 [TV_ENC_RESET] = { 0x0210 },
2446 [CSI2_RESET] = { 0x0214, 2 },
2447 [CSI_RDI1_RESET] = { 0x0214, 1 },
2448 [CSI_RDI2_RESET] = { 0x0214 },
2449};
2450
Stephen Boyde216ce62014-07-15 14:52:22 -07002451static struct clk_regmap *mmcc_apq8064_clks[] = {
2452 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2453 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2454 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2455 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2456 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2457 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2458 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2459 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2460 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2461 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2462 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2463 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2464 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2465 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2466 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2467 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2468 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2469 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2470 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2471 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2472 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2473 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2474 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2475 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2476 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2477 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2478 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2479 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2480 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2481 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2482 [CSI0_SRC] = &csi0_src.clkr,
2483 [CSI0_CLK] = &csi0_clk.clkr,
2484 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2485 [CSI1_SRC] = &csi1_src.clkr,
2486 [CSI1_CLK] = &csi1_clk.clkr,
2487 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2488 [CSI2_SRC] = &csi2_src.clkr,
2489 [CSI2_CLK] = &csi2_clk.clkr,
2490 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2491 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2492 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2493 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2494 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2495 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2496 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2497 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2498 [GFX3D_SRC] = &gfx3d_src.clkr,
2499 [GFX3D_CLK] = &gfx3d_clk.clkr,
2500 [IJPEG_SRC] = &ijpeg_src.clkr,
2501 [IJPEG_CLK] = &ijpeg_clk.clkr,
2502 [JPEGD_SRC] = &jpegd_src.clkr,
2503 [JPEGD_CLK] = &jpegd_clk.clkr,
2504 [MDP_SRC] = &mdp_src.clkr,
2505 [MDP_CLK] = &mdp_clk.clkr,
2506 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2507 [ROT_SRC] = &rot_src.clkr,
2508 [ROT_CLK] = &rot_clk.clkr,
2509 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2510 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2511 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2512 [TV_SRC] = &tv_src.clkr,
2513 [VCODEC_SRC] = &vcodec_src.clkr,
2514 [VCODEC_CLK] = &vcodec_clk.clkr,
2515 [VFE_SRC] = &vfe_src.clkr,
2516 [VFE_CLK] = &vfe_clk.clkr,
2517 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2518 [VPE_SRC] = &vpe_src.clkr,
2519 [VPE_CLK] = &vpe_clk.clkr,
2520 [CAMCLK0_SRC] = &camclk0_src.clkr,
2521 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2522 [CAMCLK1_SRC] = &camclk1_src.clkr,
2523 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2524 [CAMCLK2_SRC] = &camclk2_src.clkr,
2525 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2526 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2527 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2528 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2529 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2530 [PLL2] = &pll2.clkr,
2531 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2532 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2533 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2534 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2535 [VCAP_SRC] = &vcap_src.clkr,
2536 [VCAP_CLK] = &vcap_clk.clkr,
2537 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2538 [PLL15] = &pll15.clkr,
2539};
2540
2541static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2542 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2543 [VCAP_AXI_RESET] = { 0x0208, 16 },
2544 [VPE_AXI_RESET] = { 0x0208, 15 },
2545 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2546 [MPD_AXI_RESET] = { 0x0208, 13 },
2547 [VFE_AXI_RESET] = { 0x0208, 9 },
2548 [SP_AXI_RESET] = { 0x0208, 8 },
2549 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2550 [ROT_AXI_RESET] = { 0x0208, 6 },
2551 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2552 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2553 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2554 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2555 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2556 [FAB_S0_AXI_RESET] = { 0x0208 },
2557 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2558 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2559 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2560 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2561 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2562 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2563 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2564 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2565 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2566 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2567 [APU_AHB_RESET] = { 0x020c, 18 },
2568 [CSI_AHB_RESET] = { 0x020c, 17 },
2569 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2570 [VPE_AHB_RESET] = { 0x020c, 14 },
2571 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2572 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2573 [HDMI_AHB_RESET] = { 0x020c, 9 },
2574 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2575 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2576 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2577 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2578 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2579 [MDP_AHB_RESET] = { 0x020c, 3 },
2580 [ROT_AHB_RESET] = { 0x020c, 2 },
2581 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2582 [VFE_AHB_RESET] = { 0x020c, 0 },
2583 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2584 [VCAP_AHB_RESET] = { 0x0200, 2 },
2585 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2586 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2587 [CSIPHY2_RESET] = { 0x0210, 31 },
2588 [CSI_PIX1_RESET] = { 0x0210, 30 },
2589 [CSIPHY0_RESET] = { 0x0210, 29 },
2590 [CSIPHY1_RESET] = { 0x0210, 28 },
2591 [CSI_RDI_RESET] = { 0x0210, 27 },
2592 [CSI_PIX_RESET] = { 0x0210, 26 },
2593 [DSI2_RESET] = { 0x0210, 25 },
2594 [VFE_CSI_RESET] = { 0x0210, 24 },
2595 [MDP_RESET] = { 0x0210, 21 },
2596 [AMP_RESET] = { 0x0210, 20 },
2597 [JPEGD_RESET] = { 0x0210, 19 },
2598 [CSI1_RESET] = { 0x0210, 18 },
2599 [VPE_RESET] = { 0x0210, 17 },
2600 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2601 [VFE_RESET] = { 0x0210, 15 },
2602 [GFX3D_RESET] = { 0x0210, 12 },
2603 [HDMI_RESET] = { 0x0210, 11 },
2604 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2605 [IJPEG_RESET] = { 0x0210, 9 },
2606 [CSI0_RESET] = { 0x0210, 8 },
2607 [DSI_RESET] = { 0x0210, 7 },
2608 [VCODEC_RESET] = { 0x0210, 6 },
2609 [MDP_TV_RESET] = { 0x0210, 4 },
2610 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2611 [ROT_RESET] = { 0x0210, 2 },
2612 [TV_HDMI_RESET] = { 0x0210, 1 },
2613 [VCAP_NPL_RESET] = { 0x0214, 4 },
2614 [VCAP_RESET] = { 0x0214, 3 },
2615 [CSI2_RESET] = { 0x0214, 2 },
2616 [CSI_RDI1_RESET] = { 0x0214, 1 },
2617 [CSI_RDI2_RESET] = { 0x0214 },
2618};
2619
Stephen Boyd6d00b562014-01-15 10:47:29 -08002620static const struct regmap_config mmcc_msm8960_regmap_config = {
2621 .reg_bits = 32,
2622 .reg_stride = 4,
2623 .val_bits = 32,
2624 .max_register = 0x334,
2625 .fast_io = true,
2626};
2627
Stephen Boyde216ce62014-07-15 14:52:22 -07002628static const struct regmap_config mmcc_apq8064_regmap_config = {
2629 .reg_bits = 32,
2630 .reg_stride = 4,
2631 .val_bits = 32,
2632 .max_register = 0x350,
2633 .fast_io = true,
2634};
2635
Stephen Boyd49fc8252014-03-21 17:59:37 -07002636static const struct qcom_cc_desc mmcc_msm8960_desc = {
2637 .config = &mmcc_msm8960_regmap_config,
2638 .clks = mmcc_msm8960_clks,
2639 .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2640 .resets = mmcc_msm8960_resets,
2641 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2642};
2643
Stephen Boyde216ce62014-07-15 14:52:22 -07002644static const struct qcom_cc_desc mmcc_apq8064_desc = {
2645 .config = &mmcc_apq8064_regmap_config,
2646 .clks = mmcc_apq8064_clks,
2647 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2648 .resets = mmcc_apq8064_resets,
2649 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2650};
2651
Stephen Boyd6d00b562014-01-15 10:47:29 -08002652static const struct of_device_id mmcc_msm8960_match_table[] = {
Stephen Boyde216ce62014-07-15 14:52:22 -07002653 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2654 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
Stephen Boyd6d00b562014-01-15 10:47:29 -08002655 { }
2656};
2657MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2658
Stephen Boyd6d00b562014-01-15 10:47:29 -08002659static int mmcc_msm8960_probe(struct platform_device *pdev)
2660{
Stephen Boyde216ce62014-07-15 14:52:22 -07002661 const struct of_device_id *match;
2662 struct regmap *regmap;
2663 bool is_8064;
2664 struct device *dev = &pdev->dev;
2665
2666 match = of_match_device(mmcc_msm8960_match_table, dev);
2667 if (!match)
2668 return -EINVAL;
2669
2670 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2671 if (is_8064) {
2672 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2673 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2674 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2675 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2676 }
2677
2678 regmap = qcom_cc_map(pdev, match->data);
2679 if (IS_ERR(regmap))
2680 return PTR_ERR(regmap);
2681
2682 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2683
2684 return qcom_cc_really_probe(pdev, match->data, regmap);
Stephen Boyd6d00b562014-01-15 10:47:29 -08002685}
2686
2687static int mmcc_msm8960_remove(struct platform_device *pdev)
2688{
Stephen Boyd49fc8252014-03-21 17:59:37 -07002689 qcom_cc_remove(pdev);
Stephen Boyd6d00b562014-01-15 10:47:29 -08002690 return 0;
2691}
2692
2693static struct platform_driver mmcc_msm8960_driver = {
2694 .probe = mmcc_msm8960_probe,
2695 .remove = mmcc_msm8960_remove,
2696 .driver = {
2697 .name = "mmcc-msm8960",
Stephen Boyd6d00b562014-01-15 10:47:29 -08002698 .of_match_table = mmcc_msm8960_match_table,
2699 },
2700};
2701
2702module_platform_driver(mmcc_msm8960_driver);
2703
2704MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2705MODULE_LICENSE("GPL v2");
2706MODULE_ALIAS("platform:mmcc-msm8960");