Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 1 | /* |
| 2 | * EHRPWM PWM driver |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/pwm.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/pm_runtime.h> |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 28 | #include <linux/of_device.h> |
| 29 | |
| 30 | #include "pwm-tipwmss.h" |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 31 | |
| 32 | /* EHRPWM registers and bits definitions */ |
| 33 | |
| 34 | /* Time base module registers */ |
| 35 | #define TBCTL 0x00 |
| 36 | #define TBPRD 0x0A |
| 37 | |
| 38 | #define TBCTL_RUN_MASK (BIT(15) | BIT(14)) |
| 39 | #define TBCTL_STOP_NEXT 0 |
| 40 | #define TBCTL_STOP_ON_CYCLE BIT(14) |
| 41 | #define TBCTL_FREE_RUN (BIT(15) | BIT(14)) |
| 42 | #define TBCTL_PRDLD_MASK BIT(3) |
| 43 | #define TBCTL_PRDLD_SHDW 0 |
| 44 | #define TBCTL_PRDLD_IMDT BIT(3) |
| 45 | #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ |
| 46 | BIT(8) | BIT(7)) |
| 47 | #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) |
| 48 | #define TBCTL_CTRMODE_UP 0 |
| 49 | #define TBCTL_CTRMODE_DOWN BIT(0) |
| 50 | #define TBCTL_CTRMODE_UPDOWN BIT(1) |
| 51 | #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) |
| 52 | |
| 53 | #define TBCTL_HSPCLKDIV_SHIFT 7 |
| 54 | #define TBCTL_CLKDIV_SHIFT 10 |
| 55 | |
| 56 | #define CLKDIV_MAX 7 |
| 57 | #define HSPCLKDIV_MAX 7 |
| 58 | #define PERIOD_MAX 0xFFFF |
| 59 | |
| 60 | /* compare module registers */ |
| 61 | #define CMPA 0x12 |
| 62 | #define CMPB 0x14 |
| 63 | |
| 64 | /* Action qualifier module registers */ |
| 65 | #define AQCTLA 0x16 |
| 66 | #define AQCTLB 0x18 |
| 67 | #define AQSFRC 0x1A |
| 68 | #define AQCSFRC 0x1C |
| 69 | |
| 70 | #define AQCTL_CBU_MASK (BIT(9) | BIT(8)) |
| 71 | #define AQCTL_CBU_FRCLOW BIT(8) |
| 72 | #define AQCTL_CBU_FRCHIGH BIT(9) |
| 73 | #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) |
| 74 | #define AQCTL_CAU_MASK (BIT(5) | BIT(4)) |
| 75 | #define AQCTL_CAU_FRCLOW BIT(4) |
| 76 | #define AQCTL_CAU_FRCHIGH BIT(5) |
| 77 | #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) |
| 78 | #define AQCTL_PRD_MASK (BIT(3) | BIT(2)) |
| 79 | #define AQCTL_PRD_FRCLOW BIT(2) |
| 80 | #define AQCTL_PRD_FRCHIGH BIT(3) |
| 81 | #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) |
| 82 | #define AQCTL_ZRO_MASK (BIT(1) | BIT(0)) |
| 83 | #define AQCTL_ZRO_FRCLOW BIT(0) |
| 84 | #define AQCTL_ZRO_FRCHIGH BIT(1) |
| 85 | #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) |
| 86 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 87 | #define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \ |
| 88 | AQCTL_ZRO_FRCHIGH) |
| 89 | #define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \ |
| 90 | AQCTL_ZRO_FRCLOW) |
| 91 | #define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \ |
| 92 | AQCTL_ZRO_FRCHIGH) |
| 93 | #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \ |
| 94 | AQCTL_ZRO_FRCLOW) |
| 95 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 96 | #define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) |
| 97 | #define AQSFRC_RLDCSF_ZRO 0 |
| 98 | #define AQSFRC_RLDCSF_PRD BIT(6) |
| 99 | #define AQSFRC_RLDCSF_ZROPRD BIT(7) |
| 100 | #define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) |
| 101 | |
| 102 | #define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) |
| 103 | #define AQCSFRC_CSFB_FRCDIS 0 |
| 104 | #define AQCSFRC_CSFB_FRCLOW BIT(2) |
| 105 | #define AQCSFRC_CSFB_FRCHIGH BIT(3) |
| 106 | #define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) |
| 107 | #define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) |
| 108 | #define AQCSFRC_CSFA_FRCDIS 0 |
| 109 | #define AQCSFRC_CSFA_FRCLOW BIT(0) |
| 110 | #define AQCSFRC_CSFA_FRCHIGH BIT(1) |
| 111 | #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) |
| 112 | |
| 113 | #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ |
| 114 | |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 115 | struct ehrpwm_context { |
| 116 | u16 tbctl; |
| 117 | u16 tbprd; |
| 118 | u16 cmpa; |
| 119 | u16 cmpb; |
| 120 | u16 aqctla; |
| 121 | u16 aqctlb; |
| 122 | u16 aqsfrc; |
| 123 | u16 aqcsfrc; |
| 124 | }; |
| 125 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 126 | struct ehrpwm_pwm_chip { |
| 127 | struct pwm_chip chip; |
| 128 | unsigned int clk_rate; |
| 129 | void __iomem *mmio_base; |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 130 | unsigned long period_cycles[NUM_PWM_CHANNEL]; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 131 | enum pwm_polarity polarity[NUM_PWM_CHANNEL]; |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame] | 132 | struct clk *tbclk; |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 133 | struct ehrpwm_context ctx; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) |
| 137 | { |
| 138 | return container_of(chip, struct ehrpwm_pwm_chip, chip); |
| 139 | } |
| 140 | |
Wolfram Sang | 3ea57ea | 2014-04-02 13:56:22 +0200 | [diff] [blame] | 141 | static inline u16 ehrpwm_read(void __iomem *base, int offset) |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 142 | { |
| 143 | return readw(base + offset); |
| 144 | } |
| 145 | |
Wolfram Sang | 3ea57ea | 2014-04-02 13:56:22 +0200 | [diff] [blame] | 146 | static inline void ehrpwm_write(void __iomem *base, int offset, unsigned int val) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 147 | { |
| 148 | writew(val & 0xFFFF, base + offset); |
| 149 | } |
| 150 | |
Jingoo Han | ac872bc | 2013-08-02 15:22:03 +0900 | [diff] [blame] | 151 | static void ehrpwm_modify(void __iomem *base, int offset, |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 152 | unsigned short mask, unsigned short val) |
| 153 | { |
| 154 | unsigned short regval; |
| 155 | |
| 156 | regval = readw(base + offset); |
| 157 | regval &= ~mask; |
| 158 | regval |= val & mask; |
| 159 | writew(regval, base + offset); |
| 160 | } |
| 161 | |
| 162 | /** |
| 163 | * set_prescale_div - Set up the prescaler divider function |
| 164 | * @rqst_prescaler: prescaler value min |
| 165 | * @prescale_div: prescaler value set |
| 166 | * @tb_clk_div: Time Base Control prescaler bits |
| 167 | */ |
| 168 | static int set_prescale_div(unsigned long rqst_prescaler, |
| 169 | unsigned short *prescale_div, unsigned short *tb_clk_div) |
| 170 | { |
| 171 | unsigned int clkdiv, hspclkdiv; |
| 172 | |
| 173 | for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { |
| 174 | for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) { |
| 175 | |
| 176 | /* |
| 177 | * calculations for prescaler value : |
| 178 | * prescale_div = HSPCLKDIVIDER * CLKDIVIDER. |
| 179 | * HSPCLKDIVIDER = 2 ** hspclkdiv |
| 180 | * CLKDIVIDER = (1), if clkdiv == 0 *OR* |
| 181 | * (2 * clkdiv), if clkdiv != 0 |
| 182 | * |
| 183 | * Configure prescale_div value such that period |
| 184 | * register value is less than 65535. |
| 185 | */ |
| 186 | |
| 187 | *prescale_div = (1 << clkdiv) * |
| 188 | (hspclkdiv ? (hspclkdiv * 2) : 1); |
| 189 | if (*prescale_div > rqst_prescaler) { |
| 190 | *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | |
| 191 | (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT); |
| 192 | return 0; |
| 193 | } |
| 194 | } |
| 195 | } |
| 196 | return 1; |
| 197 | } |
| 198 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 199 | static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 200 | { |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 201 | int aqctl_reg; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 202 | unsigned short aqctl_val, aqctl_mask; |
| 203 | |
| 204 | /* |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 205 | * Configure PWM output to HIGH/LOW level on counter |
| 206 | * reaches compare register value and LOW/HIGH level |
| 207 | * on counter value reaches period register value and |
| 208 | * zero value on counter |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 209 | */ |
| 210 | if (chan == 1) { |
| 211 | aqctl_reg = AQCTLB; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 212 | aqctl_mask = AQCTL_CBU_MASK; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 213 | |
| 214 | if (pc->polarity[chan] == PWM_POLARITY_INVERSED) |
| 215 | aqctl_val = AQCTL_CHANB_POLINVERSED; |
| 216 | else |
| 217 | aqctl_val = AQCTL_CHANB_POLNORMAL; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 218 | } else { |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 219 | aqctl_reg = AQCTLA; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 220 | aqctl_mask = AQCTL_CAU_MASK; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 221 | |
| 222 | if (pc->polarity[chan] == PWM_POLARITY_INVERSED) |
| 223 | aqctl_val = AQCTL_CHANA_POLINVERSED; |
| 224 | else |
| 225 | aqctl_val = AQCTL_CHANA_POLNORMAL; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 226 | } |
| 227 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 228 | aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 229 | ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | /* |
| 233 | * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE |
| 234 | * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE |
| 235 | */ |
| 236 | static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 237 | int duty_ns, int period_ns) |
| 238 | { |
| 239 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 240 | unsigned long long c; |
| 241 | unsigned long period_cycles, duty_cycles; |
| 242 | unsigned short ps_divval, tb_divval; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 243 | int i, cmp_reg; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 244 | |
Thierry Reding | c2d476a | 2012-09-02 22:13:40 +0200 | [diff] [blame] | 245 | if (period_ns > NSEC_PER_SEC) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 246 | return -ERANGE; |
| 247 | |
| 248 | c = pc->clk_rate; |
| 249 | c = c * period_ns; |
| 250 | do_div(c, NSEC_PER_SEC); |
| 251 | period_cycles = (unsigned long)c; |
| 252 | |
| 253 | if (period_cycles < 1) { |
| 254 | period_cycles = 1; |
| 255 | duty_cycles = 1; |
| 256 | } else { |
| 257 | c = pc->clk_rate; |
| 258 | c = c * duty_ns; |
| 259 | do_div(c, NSEC_PER_SEC); |
| 260 | duty_cycles = (unsigned long)c; |
| 261 | } |
| 262 | |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 263 | /* |
| 264 | * Period values should be same for multiple PWM channels as IP uses |
| 265 | * same period register for multiple channels. |
| 266 | */ |
| 267 | for (i = 0; i < NUM_PWM_CHANNEL; i++) { |
| 268 | if (pc->period_cycles[i] && |
| 269 | (pc->period_cycles[i] != period_cycles)) { |
| 270 | /* |
| 271 | * Allow channel to reconfigure period if no other |
| 272 | * channels being configured. |
| 273 | */ |
| 274 | if (i == pwm->hwpwm) |
| 275 | continue; |
| 276 | |
| 277 | dev_err(chip->dev, "Period value conflicts with channel %d\n", |
| 278 | i); |
| 279 | return -EINVAL; |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | pc->period_cycles[pwm->hwpwm] = period_cycles; |
| 284 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 285 | /* Configure clock prescaler to support Low frequency PWM wave */ |
| 286 | if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval, |
| 287 | &tb_divval)) { |
| 288 | dev_err(chip->dev, "Unsupported values\n"); |
| 289 | return -EINVAL; |
| 290 | } |
| 291 | |
| 292 | pm_runtime_get_sync(chip->dev); |
| 293 | |
| 294 | /* Update clock prescaler values */ |
| 295 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); |
| 296 | |
| 297 | /* Update period & duty cycle with presacler division */ |
| 298 | period_cycles = period_cycles / ps_divval; |
| 299 | duty_cycles = duty_cycles / ps_divval; |
| 300 | |
| 301 | /* Configure shadow loading on Period register */ |
| 302 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); |
| 303 | |
| 304 | ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); |
| 305 | |
| 306 | /* Configure ehrpwm counter for up-count mode */ |
| 307 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, |
| 308 | TBCTL_CTRMODE_UP); |
| 309 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 310 | if (pwm->hwpwm == 1) |
| 311 | /* Channel 1 configured with compare B register */ |
| 312 | cmp_reg = CMPB; |
| 313 | else |
| 314 | /* Channel 0 configured with compare A register */ |
| 315 | cmp_reg = CMPA; |
| 316 | |
| 317 | ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); |
| 318 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 319 | pm_runtime_put_sync(chip->dev); |
| 320 | return 0; |
| 321 | } |
| 322 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 323 | static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip, |
| 324 | struct pwm_device *pwm, enum pwm_polarity polarity) |
| 325 | { |
| 326 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 327 | |
| 328 | /* Configuration of polarity in hardware delayed, do at enable */ |
| 329 | pc->polarity[pwm->hwpwm] = polarity; |
| 330 | return 0; |
| 331 | } |
| 332 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 333 | static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 334 | { |
| 335 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 336 | unsigned short aqcsfrc_val, aqcsfrc_mask; |
Philip, Avinash | 0074b49 | 2013-01-10 18:35:26 +0530 | [diff] [blame] | 337 | int ret; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 338 | |
| 339 | /* Leave clock enabled on enabling PWM */ |
| 340 | pm_runtime_get_sync(chip->dev); |
| 341 | |
| 342 | /* Disabling Action Qualifier on PWM output */ |
| 343 | if (pwm->hwpwm) { |
| 344 | aqcsfrc_val = AQCSFRC_CSFB_FRCDIS; |
| 345 | aqcsfrc_mask = AQCSFRC_CSFB_MASK; |
| 346 | } else { |
| 347 | aqcsfrc_val = AQCSFRC_CSFA_FRCDIS; |
| 348 | aqcsfrc_mask = AQCSFRC_CSFA_MASK; |
| 349 | } |
| 350 | |
| 351 | /* Changes to shadow mode */ |
| 352 | ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
| 353 | AQSFRC_RLDCSF_ZRO); |
| 354 | |
| 355 | ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
| 356 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 357 | /* Channels polarity can be configured from action qualifier module */ |
| 358 | configure_polarity(pc, pwm->hwpwm); |
| 359 | |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame] | 360 | /* Enable TBCLK before enabling PWM device */ |
Marek Belisko | b388f15 | 2013-06-26 14:38:04 +0200 | [diff] [blame] | 361 | ret = clk_enable(pc->tbclk); |
Philip, Avinash | 0074b49 | 2013-01-10 18:35:26 +0530 | [diff] [blame] | 362 | if (ret) { |
Jingoo Han | 82569e5 | 2013-12-19 14:12:05 +0900 | [diff] [blame] | 363 | dev_err(chip->dev, "Failed to enable TBCLK for %s\n", |
| 364 | dev_name(pc->chip.dev)); |
Philip, Avinash | 0074b49 | 2013-01-10 18:35:26 +0530 | [diff] [blame] | 365 | return ret; |
| 366 | } |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame] | 367 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 368 | /* Enable time counter for free_run */ |
| 369 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 374 | { |
| 375 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 376 | unsigned short aqcsfrc_val, aqcsfrc_mask; |
| 377 | |
| 378 | /* Action Qualifier puts PWM output low forcefully */ |
| 379 | if (pwm->hwpwm) { |
| 380 | aqcsfrc_val = AQCSFRC_CSFB_FRCLOW; |
| 381 | aqcsfrc_mask = AQCSFRC_CSFB_MASK; |
| 382 | } else { |
| 383 | aqcsfrc_val = AQCSFRC_CSFA_FRCLOW; |
| 384 | aqcsfrc_mask = AQCSFRC_CSFA_MASK; |
| 385 | } |
| 386 | |
| 387 | /* |
| 388 | * Changes to immediate action on Action Qualifier. This puts |
| 389 | * Action Qualifier control on PWM output from next TBCLK |
| 390 | */ |
| 391 | ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
| 392 | AQSFRC_RLDCSF_IMDT); |
| 393 | |
| 394 | ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
| 395 | |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame] | 396 | /* Disabling TBCLK on PWM disable */ |
Marek Belisko | b388f15 | 2013-06-26 14:38:04 +0200 | [diff] [blame] | 397 | clk_disable(pc->tbclk); |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame] | 398 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 399 | /* Stop Time base counter */ |
| 400 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); |
| 401 | |
| 402 | /* Disable clock on PWM disable */ |
| 403 | pm_runtime_put_sync(chip->dev); |
| 404 | } |
| 405 | |
| 406 | static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
| 407 | { |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 408 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 409 | |
Boris Brezillon | 5c31252 | 2015-07-01 10:21:47 +0200 | [diff] [blame] | 410 | if (pwm_is_enabled(pwm)) { |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 411 | dev_warn(chip->dev, "Removing PWM device without disabling\n"); |
| 412 | pm_runtime_put_sync(chip->dev); |
| 413 | } |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 414 | |
| 415 | /* set period value to zero on free */ |
| 416 | pc->period_cycles[pwm->hwpwm] = 0; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 417 | } |
| 418 | |
| 419 | static const struct pwm_ops ehrpwm_pwm_ops = { |
| 420 | .free = ehrpwm_pwm_free, |
| 421 | .config = ehrpwm_pwm_config, |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 422 | .set_polarity = ehrpwm_pwm_set_polarity, |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 423 | .enable = ehrpwm_pwm_enable, |
| 424 | .disable = ehrpwm_pwm_disable, |
| 425 | .owner = THIS_MODULE, |
| 426 | }; |
| 427 | |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 428 | static const struct of_device_id ehrpwm_of_match[] = { |
Cooper Jr., Franklin | ae5200d | 2016-05-03 10:56:52 -0500 | [diff] [blame^] | 429 | { .compatible = "ti,am3352-ehrpwm" }, |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 430 | { .compatible = "ti,am33xx-ehrpwm" }, |
| 431 | {}, |
| 432 | }; |
| 433 | MODULE_DEVICE_TABLE(of, ehrpwm_of_match); |
| 434 | |
Bill Pemberton | 3e9fe83 | 2012-11-19 13:23:14 -0500 | [diff] [blame] | 435 | static int ehrpwm_pwm_probe(struct platform_device *pdev) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 436 | { |
Cooper Jr., Franklin | ae5200d | 2016-05-03 10:56:52 -0500 | [diff] [blame^] | 437 | struct device_node *np = pdev->dev.of_node; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 438 | int ret; |
| 439 | struct resource *r; |
| 440 | struct clk *clk; |
| 441 | struct ehrpwm_pwm_chip *pc; |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 442 | u16 status; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 443 | |
| 444 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
Jingoo Han | 5e34895 | 2014-04-23 18:41:48 +0900 | [diff] [blame] | 445 | if (!pc) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 446 | return -ENOMEM; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 447 | |
| 448 | clk = devm_clk_get(&pdev->dev, "fck"); |
| 449 | if (IS_ERR(clk)) { |
Cooper Jr., Franklin | ae5200d | 2016-05-03 10:56:52 -0500 | [diff] [blame^] | 450 | if (of_device_is_compatible(np, "ti,am33xx-ecap")) { |
| 451 | dev_warn(&pdev->dev, "Binding is obsolete.\n"); |
| 452 | clk = devm_clk_get(pdev->dev.parent, "fck"); |
| 453 | } |
| 454 | } |
| 455 | |
| 456 | if (IS_ERR(clk)) { |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 457 | dev_err(&pdev->dev, "failed to get clock\n"); |
| 458 | return PTR_ERR(clk); |
| 459 | } |
| 460 | |
| 461 | pc->clk_rate = clk_get_rate(clk); |
| 462 | if (!pc->clk_rate) { |
| 463 | dev_err(&pdev->dev, "failed to get clock rate\n"); |
| 464 | return -EINVAL; |
| 465 | } |
| 466 | |
| 467 | pc->chip.dev = &pdev->dev; |
| 468 | pc->chip.ops = &ehrpwm_pwm_ops; |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 469 | pc->chip.of_xlate = of_pwm_xlate_with_flags; |
| 470 | pc->chip.of_pwm_n_cells = 3; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 471 | pc->chip.base = -1; |
| 472 | pc->chip.npwm = NUM_PWM_CHANNEL; |
| 473 | |
| 474 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | 6d4294d | 2013-01-21 11:09:16 +0100 | [diff] [blame] | 475 | pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
| 476 | if (IS_ERR(pc->mmio_base)) |
| 477 | return PTR_ERR(pc->mmio_base); |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 478 | |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame] | 479 | /* Acquire tbclk for Time Base EHRPWM submodule */ |
| 480 | pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); |
| 481 | if (IS_ERR(pc->tbclk)) { |
| 482 | dev_err(&pdev->dev, "Failed to get tbclk\n"); |
| 483 | return PTR_ERR(pc->tbclk); |
| 484 | } |
| 485 | |
Marek Belisko | b388f15 | 2013-06-26 14:38:04 +0200 | [diff] [blame] | 486 | ret = clk_prepare(pc->tbclk); |
| 487 | if (ret < 0) { |
| 488 | dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret); |
| 489 | return ret; |
| 490 | } |
| 491 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 492 | ret = pwmchip_add(&pc->chip); |
| 493 | if (ret < 0) { |
| 494 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
| 495 | return ret; |
| 496 | } |
| 497 | |
| 498 | pm_runtime_enable(&pdev->dev); |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 499 | pm_runtime_get_sync(&pdev->dev); |
| 500 | |
| 501 | status = pwmss_submodule_state_change(pdev->dev.parent, |
| 502 | PWMSS_EPWMCLK_EN); |
| 503 | if (!(status & PWMSS_EPWMCLK_EN_ACK)) { |
| 504 | dev_err(&pdev->dev, "PWMSS config space clock enable failed\n"); |
| 505 | ret = -EINVAL; |
| 506 | goto pwmss_clk_failure; |
| 507 | } |
| 508 | |
| 509 | pm_runtime_put_sync(&pdev->dev); |
| 510 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 511 | platform_set_drvdata(pdev, pc); |
| 512 | return 0; |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 513 | |
| 514 | pwmss_clk_failure: |
| 515 | pm_runtime_put_sync(&pdev->dev); |
| 516 | pm_runtime_disable(&pdev->dev); |
| 517 | pwmchip_remove(&pc->chip); |
Marek Belisko | b388f15 | 2013-06-26 14:38:04 +0200 | [diff] [blame] | 518 | clk_unprepare(pc->tbclk); |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 519 | return ret; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 520 | } |
| 521 | |
Bill Pemberton | 77f3791 | 2012-11-19 13:26:09 -0500 | [diff] [blame] | 522 | static int ehrpwm_pwm_remove(struct platform_device *pdev) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 523 | { |
| 524 | struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); |
| 525 | |
Marek Belisko | b388f15 | 2013-06-26 14:38:04 +0200 | [diff] [blame] | 526 | clk_unprepare(pc->tbclk); |
| 527 | |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 528 | pm_runtime_get_sync(&pdev->dev); |
| 529 | /* |
| 530 | * Due to hardware misbehaviour, acknowledge of the stop_req |
| 531 | * is missing. Hence checking of the status bit skipped. |
| 532 | */ |
| 533 | pwmss_submodule_state_change(pdev->dev.parent, PWMSS_EPWMCLK_STOP_REQ); |
| 534 | pm_runtime_put_sync(&pdev->dev); |
| 535 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 536 | pm_runtime_put_sync(&pdev->dev); |
| 537 | pm_runtime_disable(&pdev->dev); |
| 538 | return pwmchip_remove(&pc->chip); |
| 539 | } |
| 540 | |
Wolfram Sang | af5935e | 2014-04-02 13:56:21 +0200 | [diff] [blame] | 541 | #ifdef CONFIG_PM_SLEEP |
Axel Lin | b343a18 | 2013-03-26 22:55:57 +0800 | [diff] [blame] | 542 | static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc) |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 543 | { |
| 544 | pm_runtime_get_sync(pc->chip.dev); |
| 545 | pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL); |
| 546 | pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD); |
| 547 | pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA); |
| 548 | pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB); |
| 549 | pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA); |
| 550 | pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB); |
| 551 | pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC); |
| 552 | pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC); |
| 553 | pm_runtime_put_sync(pc->chip.dev); |
| 554 | } |
| 555 | |
Axel Lin | b343a18 | 2013-03-26 22:55:57 +0800 | [diff] [blame] | 556 | static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc) |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 557 | { |
| 558 | ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd); |
| 559 | ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa); |
| 560 | ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb); |
| 561 | ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla); |
| 562 | ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb); |
| 563 | ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc); |
| 564 | ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc); |
| 565 | ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl); |
| 566 | } |
| 567 | |
| 568 | static int ehrpwm_pwm_suspend(struct device *dev) |
| 569 | { |
| 570 | struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); |
| 571 | int i; |
| 572 | |
| 573 | ehrpwm_pwm_save_context(pc); |
| 574 | for (i = 0; i < pc->chip.npwm; i++) { |
| 575 | struct pwm_device *pwm = &pc->chip.pwms[i]; |
| 576 | |
Boris Brezillon | 5c31252 | 2015-07-01 10:21:47 +0200 | [diff] [blame] | 577 | if (!pwm_is_enabled(pwm)) |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 578 | continue; |
| 579 | |
| 580 | /* Disable explicitly if PWM is running */ |
| 581 | pm_runtime_put_sync(dev); |
| 582 | } |
| 583 | return 0; |
| 584 | } |
| 585 | |
| 586 | static int ehrpwm_pwm_resume(struct device *dev) |
| 587 | { |
| 588 | struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev); |
| 589 | int i; |
| 590 | |
| 591 | for (i = 0; i < pc->chip.npwm; i++) { |
| 592 | struct pwm_device *pwm = &pc->chip.pwms[i]; |
| 593 | |
Boris Brezillon | 5c31252 | 2015-07-01 10:21:47 +0200 | [diff] [blame] | 594 | if (!pwm_is_enabled(pwm)) |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 595 | continue; |
| 596 | |
| 597 | /* Enable explicitly if PWM was running */ |
| 598 | pm_runtime_get_sync(dev); |
| 599 | } |
| 600 | ehrpwm_pwm_restore_context(pc); |
| 601 | return 0; |
| 602 | } |
Jingoo Han | 29258b2 | 2013-03-11 11:14:41 +0900 | [diff] [blame] | 603 | #endif |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 604 | |
| 605 | static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend, |
| 606 | ehrpwm_pwm_resume); |
| 607 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 608 | static struct platform_driver ehrpwm_pwm_driver = { |
| 609 | .driver = { |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 610 | .name = "ehrpwm", |
Philip, Avinash | 53ad9e8 | 2012-11-27 14:18:13 +0530 | [diff] [blame] | 611 | .of_match_table = ehrpwm_of_match, |
Philip Avinash | 0e2feb1 | 2013-01-17 14:50:02 +0530 | [diff] [blame] | 612 | .pm = &ehrpwm_pwm_pm_ops, |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 613 | }, |
| 614 | .probe = ehrpwm_pwm_probe, |
Bill Pemberton | fd10911 | 2012-11-19 13:21:28 -0500 | [diff] [blame] | 615 | .remove = ehrpwm_pwm_remove, |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 616 | }; |
| 617 | |
| 618 | module_platform_driver(ehrpwm_pwm_driver); |
| 619 | |
| 620 | MODULE_DESCRIPTION("EHRPWM PWM driver"); |
| 621 | MODULE_AUTHOR("Texas Instruments"); |
| 622 | MODULE_LICENSE("GPL"); |