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Magnus Dammd5ed4c22009-04-30 07:02:49 +00001/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Magnus Dammd5ed4c22009-04-30 07:02:49 +000014 */
15
Magnus Dammd5ed4c22009-04-30 07:02:49 +000016#include <linux/clk.h>
Magnus Dammd5ed4c22009-04-30 07:02:49 +000017#include <linux/clockchips.h>
Laurent Pinchart346f5e72014-03-04 14:11:47 +010018#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/irq.h>
Paul Gortmaker7deeab52011-07-03 13:36:22 -040025#include <linux/module.h>
Laurent Pinchart346f5e72014-03-04 14:11:47 +010026#include <linux/platform_device.h>
Rafael J. Wysocki57d13372012-03-13 22:40:14 +010027#include <linux/pm_domain.h>
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +020028#include <linux/pm_runtime.h>
Laurent Pinchart346f5e72014-03-04 14:11:47 +010029#include <linux/sh_timer.h>
30#include <linux/slab.h>
31#include <linux/spinlock.h>
Magnus Dammd5ed4c22009-04-30 07:02:49 +000032
Laurent Pinchart7dad72d2014-03-04 13:04:48 +010033struct sh_mtu2_device;
Laurent Pinchart42752cc2014-03-04 12:58:30 +010034
35struct sh_mtu2_channel {
Laurent Pinchart7dad72d2014-03-04 13:04:48 +010036 struct sh_mtu2_device *mtu;
Laurent Pinchartd2b93172014-03-04 14:17:26 +010037 unsigned int index;
Laurent Pinchartda90a1c2014-03-04 14:04:24 +010038
39 void __iomem *base;
Laurent Pinchart42752cc2014-03-04 12:58:30 +010040 int irq;
Laurent Pinchartda90a1c2014-03-04 14:04:24 +010041
Laurent Pinchart42752cc2014-03-04 12:58:30 +010042 struct clock_event_device ced;
43};
44
Laurent Pinchart7dad72d2014-03-04 13:04:48 +010045struct sh_mtu2_device {
Laurent Pinchart42752cc2014-03-04 12:58:30 +010046 struct platform_device *pdev;
47
Magnus Dammd5ed4c22009-04-30 07:02:49 +000048 void __iomem *mapbase;
49 struct clk *clk;
Laurent Pinchart42752cc2014-03-04 12:58:30 +010050
Laurent Pinchartc54ccb42014-03-04 14:23:00 +010051 struct sh_mtu2_channel *channels;
52 unsigned int num_channels;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +010053
54 bool legacy;
55 bool has_clockevent;
Magnus Dammd5ed4c22009-04-30 07:02:49 +000056};
57
Paul Mundt50393a92012-05-25 13:38:54 +090058static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
Magnus Dammd5ed4c22009-04-30 07:02:49 +000059
60#define TSTR -1 /* shared register */
61#define TCR 0 /* channel register */
62#define TMDR 1 /* channel register */
63#define TIOR 2 /* channel register */
64#define TIER 3 /* channel register */
65#define TSR 4 /* channel register */
66#define TCNT 5 /* channel register */
67#define TGR 6 /* channel register */
68
Laurent Pinchartf992c242014-03-04 15:16:25 +010069#define TCR_CCLR_NONE (0 << 5)
70#define TCR_CCLR_TGRA (1 << 5)
71#define TCR_CCLR_TGRB (2 << 5)
72#define TCR_CCLR_SYNC (3 << 5)
73#define TCR_CCLR_TGRC (5 << 5)
74#define TCR_CCLR_TGRD (6 << 5)
75#define TCR_CCLR_MASK (7 << 5)
76#define TCR_CKEG_RISING (0 << 3)
77#define TCR_CKEG_FALLING (1 << 3)
78#define TCR_CKEG_BOTH (2 << 3)
79#define TCR_CKEG_MASK (3 << 3)
80/* Values 4 to 7 are channel-dependent */
81#define TCR_TPSC_P1 (0 << 0)
82#define TCR_TPSC_P4 (1 << 0)
83#define TCR_TPSC_P16 (2 << 0)
84#define TCR_TPSC_P64 (3 << 0)
85#define TCR_TPSC_CH0_TCLKA (4 << 0)
86#define TCR_TPSC_CH0_TCLKB (5 << 0)
87#define TCR_TPSC_CH0_TCLKC (6 << 0)
88#define TCR_TPSC_CH0_TCLKD (7 << 0)
89#define TCR_TPSC_CH1_TCLKA (4 << 0)
90#define TCR_TPSC_CH1_TCLKB (5 << 0)
91#define TCR_TPSC_CH1_P256 (6 << 0)
92#define TCR_TPSC_CH1_TCNT2 (7 << 0)
93#define TCR_TPSC_CH2_TCLKA (4 << 0)
94#define TCR_TPSC_CH2_TCLKB (5 << 0)
95#define TCR_TPSC_CH2_TCLKC (6 << 0)
96#define TCR_TPSC_CH2_P1024 (7 << 0)
97#define TCR_TPSC_CH34_P256 (4 << 0)
98#define TCR_TPSC_CH34_P1024 (5 << 0)
99#define TCR_TPSC_CH34_TCLKA (6 << 0)
100#define TCR_TPSC_CH34_TCLKB (7 << 0)
101#define TCR_TPSC_MASK (7 << 0)
102
103#define TMDR_BFE (1 << 6)
104#define TMDR_BFB (1 << 5)
105#define TMDR_BFA (1 << 4)
106#define TMDR_MD_NORMAL (0 << 0)
107#define TMDR_MD_PWM_1 (2 << 0)
108#define TMDR_MD_PWM_2 (3 << 0)
109#define TMDR_MD_PHASE_1 (4 << 0)
110#define TMDR_MD_PHASE_2 (5 << 0)
111#define TMDR_MD_PHASE_3 (6 << 0)
112#define TMDR_MD_PHASE_4 (7 << 0)
113#define TMDR_MD_PWM_SYNC (8 << 0)
114#define TMDR_MD_PWM_COMP_CREST (13 << 0)
115#define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
116#define TMDR_MD_PWM_COMP_BOTH (15 << 0)
117#define TMDR_MD_MASK (15 << 0)
118
119#define TIOC_IOCH(n) ((n) << 4)
120#define TIOC_IOCL(n) ((n) << 0)
121#define TIOR_OC_RETAIN (0 << 0)
122#define TIOR_OC_0_CLEAR (1 << 0)
123#define TIOR_OC_0_SET (2 << 0)
124#define TIOR_OC_0_TOGGLE (3 << 0)
125#define TIOR_OC_1_CLEAR (5 << 0)
126#define TIOR_OC_1_SET (6 << 0)
127#define TIOR_OC_1_TOGGLE (7 << 0)
128#define TIOR_IC_RISING (8 << 0)
129#define TIOR_IC_FALLING (9 << 0)
130#define TIOR_IC_BOTH (10 << 0)
131#define TIOR_IC_TCNT (12 << 0)
132#define TIOR_MASK (15 << 0)
133
134#define TIER_TTGE (1 << 7)
135#define TIER_TTGE2 (1 << 6)
136#define TIER_TCIEU (1 << 5)
137#define TIER_TCIEV (1 << 4)
138#define TIER_TGIED (1 << 3)
139#define TIER_TGIEC (1 << 2)
140#define TIER_TGIEB (1 << 1)
141#define TIER_TGIEA (1 << 0)
142
143#define TSR_TCFD (1 << 7)
144#define TSR_TCFU (1 << 5)
145#define TSR_TCFV (1 << 4)
146#define TSR_TGFD (1 << 3)
147#define TSR_TGFC (1 << 2)
148#define TSR_TGFB (1 << 1)
149#define TSR_TGFA (1 << 0)
150
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000151static unsigned long mtu2_reg_offs[] = {
152 [TCR] = 0,
153 [TMDR] = 1,
154 [TIOR] = 2,
155 [TIER] = 4,
156 [TSR] = 5,
157 [TCNT] = 6,
158 [TGR] = 8,
159};
160
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100161static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000162{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000163 unsigned long offs;
164
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100165 if (reg_nr == TSTR) {
166 if (ch->mtu->legacy)
167 return ioread8(ch->mtu->mapbase);
168 else
169 return ioread8(ch->mtu->mapbase + 0x280);
170 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000171
172 offs = mtu2_reg_offs[reg_nr];
173
174 if ((reg_nr == TCNT) || (reg_nr == TGR))
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100175 return ioread16(ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000176 else
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100177 return ioread8(ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000178}
179
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100180static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000181 unsigned long value)
182{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000183 unsigned long offs;
184
185 if (reg_nr == TSTR) {
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100186 if (ch->mtu->legacy)
187 return iowrite8(value, ch->mtu->mapbase);
188 else
189 return iowrite8(value, ch->mtu->mapbase + 0x280);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000190 }
191
192 offs = mtu2_reg_offs[reg_nr];
193
194 if ((reg_nr == TCNT) || (reg_nr == TGR))
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100195 iowrite16(value, ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000196 else
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100197 iowrite8(value, ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000198}
199
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100200static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000201{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000202 unsigned long flags, value;
203
204 /* start stop register shared by multiple timer channels */
Paul Mundt50393a92012-05-25 13:38:54 +0900205 raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100206 value = sh_mtu2_read(ch, TSTR);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000207
208 if (start)
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100209 value |= 1 << ch->index;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000210 else
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100211 value &= ~(1 << ch->index);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000212
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100213 sh_mtu2_write(ch, TSTR, value);
Paul Mundt50393a92012-05-25 13:38:54 +0900214 raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000215}
216
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100217static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000218{
Laurent Pinchartf92d62f52014-03-04 12:59:54 +0100219 unsigned long periodic;
220 unsigned long rate;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000221 int ret;
222
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100223 pm_runtime_get_sync(&ch->mtu->pdev->dev);
224 dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200225
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000226 /* enable clock */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100227 ret = clk_enable(ch->mtu->clk);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000228 if (ret) {
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100229 dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
230 ch->index);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000231 return ret;
232 }
233
234 /* make sure channel is disabled */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100235 sh_mtu2_start_stop_ch(ch, 0);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000236
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100237 rate = clk_get_rate(ch->mtu->clk) / 64;
Laurent Pinchartf92d62f52014-03-04 12:59:54 +0100238 periodic = (rate + HZ/2) / HZ;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000239
Laurent Pinchartf992c242014-03-04 15:16:25 +0100240 /*
241 * "Periodic Counter Operation"
242 * Clear on TGRA compare match, divide clock by 64.
243 */
244 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
245 sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
246 TIOC_IOCL(TIOR_OC_0_CLEAR));
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100247 sh_mtu2_write(ch, TGR, periodic);
248 sh_mtu2_write(ch, TCNT, 0);
Laurent Pinchartf992c242014-03-04 15:16:25 +0100249 sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
250 sh_mtu2_write(ch, TIER, TIER_TGIEA);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000251
252 /* enable channel */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100253 sh_mtu2_start_stop_ch(ch, 1);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000254
255 return 0;
256}
257
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100258static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000259{
260 /* disable channel */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100261 sh_mtu2_start_stop_ch(ch, 0);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000262
263 /* stop clock */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100264 clk_disable(ch->mtu->clk);
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200265
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100266 dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
267 pm_runtime_put(&ch->mtu->pdev->dev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000268}
269
270static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
271{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100272 struct sh_mtu2_channel *ch = dev_id;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000273
274 /* acknowledge interrupt */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100275 sh_mtu2_read(ch, TSR);
Laurent Pinchartf992c242014-03-04 15:16:25 +0100276 sh_mtu2_write(ch, TSR, ~TSR_TGFA);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000277
278 /* notify clockevent layer */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100279 ch->ced.event_handler(&ch->ced);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000280 return IRQ_HANDLED;
281}
282
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100283static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000284{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100285 return container_of(ced, struct sh_mtu2_channel, ced);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000286}
287
288static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
289 struct clock_event_device *ced)
290{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100291 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000292 int disabled = 0;
293
294 /* deal with old setting first */
295 switch (ced->mode) {
296 case CLOCK_EVT_MODE_PERIODIC:
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100297 sh_mtu2_disable(ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000298 disabled = 1;
299 break;
300 default:
301 break;
302 }
303
304 switch (mode) {
305 case CLOCK_EVT_MODE_PERIODIC:
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100306 dev_info(&ch->mtu->pdev->dev,
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100307 "ch%u: used for periodic clock events\n", ch->index);
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100308 sh_mtu2_enable(ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000309 break;
310 case CLOCK_EVT_MODE_UNUSED:
311 if (!disabled)
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100312 sh_mtu2_disable(ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000313 break;
314 case CLOCK_EVT_MODE_SHUTDOWN:
315 default:
316 break;
317 }
318}
319
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200320static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
321{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100322 pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200323}
324
325static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
326{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100327 pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200328}
329
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100330static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100331 const char *name)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000332{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100333 struct clock_event_device *ced = &ch->ced;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000334 int ret;
335
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000336 ced->name = name;
337 ced->features = CLOCK_EVT_FEAT_PERIODIC;
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100338 ced->rating = 200;
Laurent Pinchart3cc95042014-03-04 15:22:19 +0100339 ced->cpumask = cpu_possible_mask;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000340 ced->set_mode = sh_mtu2_clock_event_mode;
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200341 ced->suspend = sh_mtu2_clock_event_suspend;
342 ced->resume = sh_mtu2_clock_event_resume;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000343
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100344 dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
345 ch->index);
Paul Mundtda64c2a2010-02-25 16:37:46 +0900346 clockevents_register_device(ced);
347
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100348 ret = request_irq(ch->irq, sh_mtu2_interrupt,
Laurent Pinchart276bee02014-02-17 11:27:49 +0100349 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100350 dev_name(&ch->mtu->pdev->dev), ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000351 if (ret) {
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100352 dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
353 ch->index, ch->irq);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000354 return;
355 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000356}
357
Laurent Pinchartaa838042014-03-04 13:57:14 +0100358static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name,
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100359 bool clockevent)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000360{
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100361 if (clockevent) {
362 ch->mtu->has_clockevent = true;
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100363 sh_mtu2_register_clockevent(ch, name);
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100364 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000365
366 return 0;
367}
368
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100369static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
Laurent Pinchart2e1a53262014-03-04 13:11:23 +0100370 struct sh_mtu2_device *mtu)
371{
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100372 static const unsigned int channel_offsets[] = {
373 0x300, 0x380, 0x000,
374 };
375 bool clockevent;
Laurent Pinchart2e1a53262014-03-04 13:11:23 +0100376
Laurent Pinchart2e1a53262014-03-04 13:11:23 +0100377 ch->mtu = mtu;
378
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100379 if (mtu->legacy) {
380 struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
381
382 clockevent = cfg->clockevent_rating != 0;
383
384 ch->irq = platform_get_irq(mtu->pdev, 0);
385 ch->base = mtu->mapbase - cfg->channel_offset;
386 ch->index = cfg->timer_bit;
387 } else {
388 char name[6];
389
390 clockevent = true;
391
392 sprintf(name, "tgi%ua", index);
393 ch->irq = platform_get_irq_byname(mtu->pdev, name);
394 ch->base = mtu->mapbase + channel_offsets[index];
395 ch->index = index;
396 }
397
Laurent Pinchart2e1a53262014-03-04 13:11:23 +0100398 if (ch->irq < 0) {
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100399 /* Skip channels with no declared interrupt. */
400 if (!mtu->legacy)
401 return 0;
402
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100403 dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n",
404 ch->index);
Laurent Pinchart2e1a53262014-03-04 13:11:23 +0100405 return ch->irq;
406 }
407
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100408 return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev), clockevent);
409}
410
411static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
412{
413 struct resource *res;
414
415 res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
416 if (!res) {
417 dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
418 return -ENXIO;
419 }
420
421 mtu->mapbase = ioremap_nocache(res->start, resource_size(res));
422 if (mtu->mapbase == NULL)
423 return -ENXIO;
424
425 /*
426 * In legacy platform device configuration (with one device per channel)
427 * the resource points to the channel base address.
428 */
429 if (mtu->legacy) {
430 struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
431 mtu->mapbase += cfg->channel_offset;
432 }
433
434 return 0;
435}
436
437static void sh_mtu2_unmap_memory(struct sh_mtu2_device *mtu)
438{
439 if (mtu->legacy) {
440 struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
441 mtu->mapbase -= cfg->channel_offset;
442 }
443
444 iounmap(mtu->mapbase);
Laurent Pinchart2e1a53262014-03-04 13:11:23 +0100445}
446
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100447static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
448 struct platform_device *pdev)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000449{
Paul Mundt46a12f72009-05-03 17:57:17 +0900450 struct sh_timer_config *cfg = pdev->dev.platform_data;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100451 const struct platform_device_id *id = pdev->id_entry;
452 unsigned int i;
Laurent Pinchart276bee02014-02-17 11:27:49 +0100453 int ret;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000454
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100455 mtu->pdev = pdev;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100456 mtu->legacy = id->driver_data;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000457
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100458 if (mtu->legacy && !cfg) {
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100459 dev_err(&mtu->pdev->dev, "missing platform data\n");
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100460 return -ENXIO;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000461 }
462
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100463 /* Get hold of clock. */
Laurent Pinchart6dc96932014-03-04 18:09:15 +0100464 mtu->clk = clk_get(&mtu->pdev->dev, mtu->legacy ? "mtu2_fck" : "fck");
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100465 if (IS_ERR(mtu->clk)) {
466 dev_err(&mtu->pdev->dev, "cannot get clock\n");
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100467 return PTR_ERR(mtu->clk);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000468 }
469
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100470 ret = clk_prepare(mtu->clk);
Laurent Pincharta4a5fc32013-11-08 11:07:59 +0100471 if (ret < 0)
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100472 goto err_clk_put;
Laurent Pincharta4a5fc32013-11-08 11:07:59 +0100473
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100474 /* Map the memory resource. */
475 ret = sh_mtu2_map_memory(mtu);
476 if (ret < 0) {
477 dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
478 goto err_clk_unprepare;
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100479 }
480
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100481 /* Allocate and setup the channels. */
482 if (mtu->legacy)
483 mtu->num_channels = 1;
484 else
485 mtu->num_channels = 3;
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100486
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100487 mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels,
488 GFP_KERNEL);
489 if (mtu->channels == NULL) {
490 ret = -ENOMEM;
491 goto err_unmap;
492 }
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100493
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100494 if (mtu->legacy) {
495 ret = sh_mtu2_setup_channel(&mtu->channels[0], 0, mtu);
496 if (ret < 0)
497 goto err_unmap;
498 } else {
499 for (i = 0; i < mtu->num_channels; ++i) {
500 ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
501 if (ret < 0)
502 goto err_unmap;
503 }
504 }
505
506 platform_set_drvdata(pdev, mtu);
Laurent Pincharta4a5fc32013-11-08 11:07:59 +0100507
Laurent Pinchartbd754932013-11-08 11:07:59 +0100508 return 0;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100509
510err_unmap:
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100511 kfree(mtu->channels);
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100512 sh_mtu2_unmap_memory(mtu);
513err_clk_unprepare:
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100514 clk_unprepare(mtu->clk);
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100515err_clk_put:
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100516 clk_put(mtu->clk);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000517 return ret;
518}
519
Greg Kroah-Hartman18505142012-12-21 15:11:38 -0800520static int sh_mtu2_probe(struct platform_device *pdev)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000521{
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100522 struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000523 int ret;
524
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200525 if (!is_early_platform_device(pdev)) {
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200526 pm_runtime_set_active(&pdev->dev);
527 pm_runtime_enable(&pdev->dev);
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200528 }
Rafael J. Wysocki57d13372012-03-13 22:40:14 +0100529
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100530 if (mtu) {
Paul Mundt214a6072010-03-10 16:26:25 +0900531 dev_info(&pdev->dev, "kept as earlytimer\n");
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200532 goto out;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000533 }
534
Laurent Pinchart810c6512014-03-04 14:10:55 +0100535 mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
Jingoo Hanc77a5652014-05-22 14:05:07 +0200536 if (mtu == NULL)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000537 return -ENOMEM;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000538
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100539 ret = sh_mtu2_setup(mtu, pdev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000540 if (ret) {
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100541 kfree(mtu);
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200542 pm_runtime_idle(&pdev->dev);
543 return ret;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000544 }
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200545 if (is_early_platform_device(pdev))
546 return 0;
547
548 out:
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100549 if (mtu->has_clockevent)
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200550 pm_runtime_irq_safe(&pdev->dev);
551 else
552 pm_runtime_idle(&pdev->dev);
553
554 return 0;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000555}
556
Greg Kroah-Hartman18505142012-12-21 15:11:38 -0800557static int sh_mtu2_remove(struct platform_device *pdev)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000558{
559 return -EBUSY; /* cannot unregister clockevent */
560}
561
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100562static const struct platform_device_id sh_mtu2_id_table[] = {
563 { "sh_mtu2", 1 },
564 { "sh-mtu2", 0 },
565 { },
566};
567MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
568
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000569static struct platform_driver sh_mtu2_device_driver = {
570 .probe = sh_mtu2_probe,
Greg Kroah-Hartman18505142012-12-21 15:11:38 -0800571 .remove = sh_mtu2_remove,
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000572 .driver = {
573 .name = "sh_mtu2",
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100574 },
575 .id_table = sh_mtu2_id_table,
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000576};
577
578static int __init sh_mtu2_init(void)
579{
580 return platform_driver_register(&sh_mtu2_device_driver);
581}
582
583static void __exit sh_mtu2_exit(void)
584{
585 platform_driver_unregister(&sh_mtu2_device_driver);
586}
587
588early_platform_init("earlytimer", &sh_mtu2_device_driver);
Simon Horman342896a2013-03-05 15:40:42 +0900589subsys_initcall(sh_mtu2_init);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000590module_exit(sh_mtu2_exit);
591
592MODULE_AUTHOR("Magnus Damm");
593MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
594MODULE_LICENSE("GPL v2");