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Russell Kingf27ecac2005-08-18 21:31:00 +01001/*
Russell Kingf27ecac2005-08-18 21:31:00 +01002 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Interrupt architecture for the GIC:
9 *
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
12 *
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
Catalin Marinasb3a1bde2007-02-14 19:14:56 +010015 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
Russell Kingf27ecac2005-08-18 21:31:00 +010018 *
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
22 */
23#include <linux/init.h>
24#include <linux/kernel.h>
Rob Herringf37a53c2011-10-21 17:14:27 -050025#include <linux/err.h>
Arnd Bergmann7e1efcf2011-11-01 00:28:37 +010026#include <linux/module.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010027#include <linux/list.h>
28#include <linux/smp.h>
Catalin Marinasc0114702013-01-14 18:05:37 +000029#include <linux/cpu.h>
Colin Cross254056f2011-02-10 12:54:10 -080030#include <linux/cpu_pm.h>
Catalin Marinasdcb86e82005-08-31 21:45:14 +010031#include <linux/cpumask.h>
Russell Kingfced80c2008-09-06 12:10:45 +010032#include <linux/io.h>
Rob Herringb3f7ed02011-09-28 21:27:52 -050033#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
Tomasz Nowickid60fc382015-03-24 14:02:49 +000036#include <linux/acpi.h>
Rob Herring4294f8b2011-09-28 21:25:31 -050037#include <linux/irqdomain.h>
Marc Zyngier292b2932011-07-20 16:24:14 +010038#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040041#include <linux/irqchip.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000042#include <linux/irqchip/chained_irq.h>
Rob Herring520f7bd2012-12-27 13:10:24 -060043#include <linux/irqchip/arm-gic.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010044
Tomasz Figa29e697b2014-07-17 17:23:44 +020045#include <asm/cputype.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010046#include <asm/irq.h>
Marc Zyngier562e0022011-09-06 09:56:17 +010047#include <asm/exception.h>
Will Deaconeb504392012-01-20 12:01:12 +010048#include <asm/smp_plat.h>
Marc Zyngier0b996fd2015-08-26 17:00:44 +010049#include <asm/virt.h>
Russell Kingf27ecac2005-08-18 21:31:00 +010050
Marc Zyngierd51d0af2014-06-30 16:01:30 +010051#include "irq-gic-common.h"
Russell Kingf27ecac2005-08-18 21:31:00 +010052
Marc Zyngier76e52dd2015-09-30 12:01:16 +010053#ifdef CONFIG_ARM64
54#include <asm/cpufeature.h>
55
56static void gic_check_cpu_features(void)
57{
Marc Zyngier25fc11a2016-04-22 12:25:33 +010058 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
Marc Zyngier76e52dd2015-09-30 12:01:16 +010059 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
61}
62#else
63#define gic_check_cpu_features() do { } while(0)
64#endif
65
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000066union gic_base {
67 void __iomem *common_base;
Stephen Boyd68593582014-03-04 17:02:01 -080068 void __percpu * __iomem *percpu_base;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000069};
70
71struct gic_chip_data {
Linus Walleij58b89642015-10-24 00:15:53 +020072 struct irq_chip chip;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000073 union gic_base dist_base;
74 union gic_base cpu_base;
Jon Hunterf673b9b2016-05-10 16:14:44 +010075 void __iomem *raw_dist_base;
76 void __iomem *raw_cpu_base;
77 u32 percpu_offset;
Jon Hunter9c8eddd2016-06-07 16:12:34 +010078#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000079 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +000080 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000081 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
83 u32 __percpu *saved_ppi_enable;
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +000084 u32 __percpu *saved_ppi_active;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000085 u32 __percpu *saved_ppi_conf;
86#endif
Grant Likely75294952012-02-14 14:06:57 -070087 struct irq_domain *domain;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +000088 unsigned int gic_irqs;
89#ifdef CONFIG_GIC_NON_BANKED
90 void __iomem *(*get_base)(union gic_base *);
91#endif
92};
93
Marc Zyngier04c8b0f2016-06-27 18:11:43 +010094#ifdef CONFIG_BL_SWITCHER
95
96static DEFINE_RAW_SPINLOCK(cpu_map_lock);
97
98#define gic_lock_irqsave(f) \
99 raw_spin_lock_irqsave(&cpu_map_lock, (f))
100#define gic_unlock_irqrestore(f) \
101 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
102
103#define gic_lock() raw_spin_lock(&cpu_map_lock)
104#define gic_unlock() raw_spin_unlock(&cpu_map_lock)
105
106#else
107
108#define gic_lock_irqsave(f) do { (void)(f); } while(0)
109#define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
110
111#define gic_lock() do { } while(0)
112#define gic_unlock() do { } while(0)
113
114#endif
Russell Kingf27ecac2005-08-18 21:31:00 +0100115
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100116/*
Nicolas Pitre384a2902012-04-11 18:55:48 -0400117 * The GIC mapping of CPU interfaces does not necessarily match
118 * the logical CPU numbering. Let's use a mapping as returned
119 * by the GIC itself.
120 */
121#define NR_GIC_CPU_IF 8
122static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
123
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100124static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
125
Linus Walleija27d21e2015-12-18 10:44:53 +0100126static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100127
Julien Grall502d6df2016-04-11 16:32:54 +0100128static struct gic_kvm_info gic_v2_kvm_info;
129
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000130#ifdef CONFIG_GIC_NON_BANKED
131static void __iomem *gic_get_percpu_base(union gic_base *base)
132{
Christoph Lameter513d1a22014-09-02 10:00:07 -0500133 return raw_cpu_read(*base->percpu_base);
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000134}
135
136static void __iomem *gic_get_common_base(union gic_base *base)
137{
138 return base->common_base;
139}
140
141static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
142{
143 return data->get_base(&data->dist_base);
144}
145
146static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
147{
148 return data->get_base(&data->cpu_base);
149}
150
151static inline void gic_set_base_accessor(struct gic_chip_data *data,
152 void __iomem *(*f)(union gic_base *))
153{
154 data->get_base = f;
155}
156#else
157#define gic_data_dist_base(d) ((d)->dist_base.common_base)
158#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
Sachin Kamat46f101d2013-03-13 15:05:15 +0530159#define gic_set_base_accessor(d, f)
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000160#endif
161
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100162static inline void __iomem *gic_dist_base(struct irq_data *d)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100163{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100164 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000165 return gic_data_dist_base(gic_data);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100166}
167
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100168static inline void __iomem *gic_cpu_base(struct irq_data *d)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100169{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100170 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000171 return gic_data_cpu_base(gic_data);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100172}
173
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100174static inline unsigned int gic_irq(struct irq_data *d)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100175{
Rob Herring4294f8b2011-09-28 21:25:31 -0500176 return d->hwirq;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100177}
178
Marc Zyngier01f779f2015-08-26 17:00:45 +0100179static inline bool cascading_gic_irq(struct irq_data *d)
180{
181 void *data = irq_data_get_irq_handler_data(d);
182
183 /*
Thomas Gleixner714665352015-09-15 12:37:36 +0200184 * If handler_data is set, this is a cascading interrupt, and
185 * it cannot possibly be forwarded.
Marc Zyngier01f779f2015-08-26 17:00:45 +0100186 */
Thomas Gleixner714665352015-09-15 12:37:36 +0200187 return data != NULL;
Marc Zyngier01f779f2015-08-26 17:00:45 +0100188}
189
Russell Kingf27ecac2005-08-18 21:31:00 +0100190/*
191 * Routines to acknowledge, disable and enable interrupts
Russell Kingf27ecac2005-08-18 21:31:00 +0100192 */
Marc Zyngier56717802015-03-18 11:01:23 +0000193static void gic_poke_irq(struct irq_data *d, u32 offset)
Russell Kingf27ecac2005-08-18 21:31:00 +0100194{
Rob Herring4294f8b2011-09-28 21:25:31 -0500195 u32 mask = 1 << (gic_irq(d) % 32);
Marc Zyngier56717802015-03-18 11:01:23 +0000196 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
197}
198
199static int gic_peek_irq(struct irq_data *d, u32 offset)
200{
201 u32 mask = 1 << (gic_irq(d) % 32);
202 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
203}
204
205static void gic_mask_irq(struct irq_data *d)
206{
Marc Zyngier56717802015-03-18 11:01:23 +0000207 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
Russell Kingf27ecac2005-08-18 21:31:00 +0100208}
209
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100210static void gic_eoimode1_mask_irq(struct irq_data *d)
211{
212 gic_mask_irq(d);
Marc Zyngier01f779f2015-08-26 17:00:45 +0100213 /*
214 * When masking a forwarded interrupt, make sure it is
215 * deactivated as well.
216 *
217 * This ensures that an interrupt that is getting
218 * disabled/masked will not get "stuck", because there is
219 * noone to deactivate it (guest is being terminated).
220 */
Thomas Gleixner714665352015-09-15 12:37:36 +0200221 if (irqd_is_forwarded_to_vcpu(d))
Marc Zyngier01f779f2015-08-26 17:00:45 +0100222 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100223}
224
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100225static void gic_unmask_irq(struct irq_data *d)
Russell Kingf27ecac2005-08-18 21:31:00 +0100226{
Marc Zyngier56717802015-03-18 11:01:23 +0000227 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
Russell Kingf27ecac2005-08-18 21:31:00 +0100228}
229
Will Deacon1a017532011-02-09 12:01:12 +0000230static void gic_eoi_irq(struct irq_data *d)
231{
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530232 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
Will Deacon1a017532011-02-09 12:01:12 +0000233}
234
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100235static void gic_eoimode1_eoi_irq(struct irq_data *d)
236{
Marc Zyngier01f779f2015-08-26 17:00:45 +0100237 /* Do not deactivate an IRQ forwarded to a vcpu. */
Thomas Gleixner714665352015-09-15 12:37:36 +0200238 if (irqd_is_forwarded_to_vcpu(d))
Marc Zyngier01f779f2015-08-26 17:00:45 +0100239 return;
240
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100241 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
242}
243
Marc Zyngier56717802015-03-18 11:01:23 +0000244static int gic_irq_set_irqchip_state(struct irq_data *d,
245 enum irqchip_irq_state which, bool val)
246{
247 u32 reg;
248
249 switch (which) {
250 case IRQCHIP_STATE_PENDING:
251 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
252 break;
253
254 case IRQCHIP_STATE_ACTIVE:
255 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
256 break;
257
258 case IRQCHIP_STATE_MASKED:
259 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
260 break;
261
262 default:
263 return -EINVAL;
264 }
265
266 gic_poke_irq(d, reg);
267 return 0;
268}
269
270static int gic_irq_get_irqchip_state(struct irq_data *d,
271 enum irqchip_irq_state which, bool *val)
272{
273 switch (which) {
274 case IRQCHIP_STATE_PENDING:
275 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
276 break;
277
278 case IRQCHIP_STATE_ACTIVE:
279 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
280 break;
281
282 case IRQCHIP_STATE_MASKED:
283 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
284 break;
285
286 default:
287 return -EINVAL;
288 }
289
290 return 0;
291}
292
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100293static int gic_set_type(struct irq_data *d, unsigned int type)
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100294{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100295 void __iomem *base = gic_dist_base(d);
296 unsigned int gicirq = gic_irq(d);
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100297
298 /* Interrupt configuration for SGIs can't be changed */
299 if (gicirq < 16)
300 return -EINVAL;
301
Liviu Dudaufb7e7de2015-01-20 16:52:59 +0000302 /* SPIs have restrictions on the supported types */
303 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
304 type != IRQ_TYPE_EDGE_RISING)
Rabin Vincent5c0c1f02010-05-28 04:37:38 +0100305 return -EINVAL;
306
Marc Zyngier1dcc73d2015-04-22 18:20:04 +0100307 return gic_configure_irq(gicirq, type, base, NULL);
Santosh Shilimkard7ed36a2011-03-02 08:03:22 +0100308}
309
Marc Zyngier01f779f2015-08-26 17:00:45 +0100310static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
311{
312 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
313 if (cascading_gic_irq(d))
314 return -EINVAL;
315
Thomas Gleixner714665352015-09-15 12:37:36 +0200316 if (vcpu)
317 irqd_set_forwarded_to_vcpu(d);
318 else
319 irqd_clr_forwarded_to_vcpu(d);
Marc Zyngier01f779f2015-08-26 17:00:45 +0100320 return 0;
321}
322
Catalin Marinasa06f5462005-09-30 16:07:05 +0100323#ifdef CONFIG_SMP
Russell Kingc1917892011-01-23 12:12:01 +0000324static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
325 bool force)
Russell Kingf27ecac2005-08-18 21:31:00 +0100326{
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100327 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
Thomas Gleixnerffde1de2014-04-16 14:36:44 +0000328 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
Russell Kingc1917892011-01-23 12:12:01 +0000329 u32 val, mask, bit;
Marc Zyngiercf613872015-03-06 16:37:44 +0000330 unsigned long flags;
Russell Kingc1917892011-01-23 12:12:01 +0000331
Thomas Gleixnerffde1de2014-04-16 14:36:44 +0000332 if (!force)
333 cpu = cpumask_any_and(mask_val, cpu_online_mask);
334 else
335 cpu = cpumask_first(mask_val);
336
Nicolas Pitre384a2902012-04-11 18:55:48 -0400337 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
Russell Kingc1917892011-01-23 12:12:01 +0000338 return -EINVAL;
339
Marc Zyngier04c8b0f2016-06-27 18:11:43 +0100340 gic_lock_irqsave(flags);
Russell Kingc1917892011-01-23 12:12:01 +0000341 mask = 0xff << shift;
Nicolas Pitre384a2902012-04-11 18:55:48 -0400342 bit = gic_cpu_map[cpu] << shift;
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530343 val = readl_relaxed(reg) & ~mask;
344 writel_relaxed(val | bit, reg);
Marc Zyngier04c8b0f2016-06-27 18:11:43 +0100345 gic_unlock_irqrestore(flags);
Yinghai Lud5dedd42009-04-27 17:59:21 -0700346
Marc Zyngier0407dac2016-02-19 15:00:29 +0000347 return IRQ_SET_MASK_OK_DONE;
Russell Kingf27ecac2005-08-18 21:31:00 +0100348}
Catalin Marinasa06f5462005-09-30 16:07:05 +0100349#endif
Russell Kingf27ecac2005-08-18 21:31:00 +0100350
Stephen Boyd8783dd32014-03-04 16:40:30 -0800351static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
Marc Zyngier562e0022011-09-06 09:56:17 +0100352{
353 u32 irqstat, irqnr;
354 struct gic_chip_data *gic = &gic_data[0];
355 void __iomem *cpu_base = gic_data_cpu_base(gic);
356
357 do {
358 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
Haojian Zhuangb8802f72014-05-11 16:05:58 +0800359 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
Marc Zyngier562e0022011-09-06 09:56:17 +0100360
Marc Zyngier327ebe12015-12-16 14:11:22 +0000361 if (likely(irqnr > 15 && irqnr < 1020)) {
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100362 if (static_key_true(&supports_deactivate))
363 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
Marc Zyngier60031b42014-08-26 11:03:20 +0100364 handle_domain_irq(gic->domain, irqnr, regs);
Marc Zyngier562e0022011-09-06 09:56:17 +0100365 continue;
366 }
367 if (irqnr < 16) {
368 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100369 if (static_key_true(&supports_deactivate))
370 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
Marc Zyngier562e0022011-09-06 09:56:17 +0100371#ifdef CONFIG_SMP
Will Deaconf86c4fb2016-04-26 12:00:00 +0100372 /*
373 * Ensure any shared data written by the CPU sending
374 * the IPI is read after we've read the ACK register
375 * on the GIC.
376 *
377 * Pairs with the write barrier in gic_raise_softirq
378 */
379 smp_rmb();
Marc Zyngier562e0022011-09-06 09:56:17 +0100380 handle_IPI(irqnr, regs);
381#endif
382 continue;
383 }
384 break;
385 } while (1);
386}
387
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200388static void gic_handle_cascade_irq(struct irq_desc *desc)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100389{
Jiang Liu5b292642015-06-04 12:13:20 +0800390 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
391 struct irq_chip *chip = irq_desc_get_chip(desc);
Russell King0f347bb2007-05-17 10:11:34 +0100392 unsigned int cascade_irq, gic_irq;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100393 unsigned long status;
394
Will Deacon1a017532011-02-09 12:01:12 +0000395 chained_irq_enter(chip, desc);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100396
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000397 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100398
Feng Kane5f81532014-07-30 14:56:58 -0700399 gic_irq = (status & GICC_IAR_INT_ID_MASK);
400 if (gic_irq == GICC_INT_SPURIOUS)
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100401 goto out;
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100402
Grant Likely75294952012-02-14 14:06:57 -0700403 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
404 if (unlikely(gic_irq < 32 || gic_irq > 1020))
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200405 handle_bad_irq(desc);
Russell King0f347bb2007-05-17 10:11:34 +0100406 else
407 generic_handle_irq(cascade_irq);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100408
409 out:
Will Deacon1a017532011-02-09 12:01:12 +0000410 chained_irq_exit(chip, desc);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100411}
412
David Brownell38c677c2006-08-01 22:26:25 +0100413static struct irq_chip gic_chip = {
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100414 .irq_mask = gic_mask_irq,
415 .irq_unmask = gic_unmask_irq,
Will Deacon1a017532011-02-09 12:01:12 +0000416 .irq_eoi = gic_eoi_irq,
Lennert Buytenhek7d1f4282010-11-29 10:18:20 +0100417 .irq_set_type = gic_set_type,
Marc Zyngier56717802015-03-18 11:01:23 +0000418 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
419 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
Sudeep Hollaaec89ef2015-07-15 15:38:28 +0100420 .flags = IRQCHIP_SET_TYPE_MASKED |
421 IRQCHIP_SKIP_SET_WAKE |
422 IRQCHIP_MASK_ON_SUSPEND,
Russell Kingf27ecac2005-08-18 21:31:00 +0100423};
424
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100425void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
426{
Linus Walleija27d21e2015-12-18 10:44:53 +0100427 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
Thomas Gleixner4d83fcf2015-06-21 21:10:53 +0200428 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
429 &gic_data[gic_nr]);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +0100430}
431
Russell King2bb31352013-01-30 23:49:57 +0000432static u8 gic_get_cpumask(struct gic_chip_data *gic)
433{
434 void __iomem *base = gic_data_dist_base(gic);
435 u32 mask, i;
436
437 for (i = mask = 0; i < 32; i += 4) {
438 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
439 mask |= mask >> 16;
440 mask |= mask >> 8;
441 if (mask)
442 break;
443 }
444
Stephen Boyd6e3aca42015-03-11 23:21:31 -0700445 if (!mask && num_possible_cpus() > 1)
Russell King2bb31352013-01-30 23:49:57 +0000446 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
447
448 return mask;
449}
450
Jon Hunter4c2880b2015-07-31 09:44:12 +0100451static void gic_cpu_if_up(struct gic_chip_data *gic)
Feng Kan32289502014-07-30 14:56:59 -0700452{
Jon Hunter4c2880b2015-07-31 09:44:12 +0100453 void __iomem *cpu_base = gic_data_cpu_base(gic);
Feng Kan32289502014-07-30 14:56:59 -0700454 u32 bypass = 0;
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100455 u32 mode = 0;
456
Jon Hunter389a00d2016-02-09 15:24:57 +0000457 if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100458 mode = GIC_CPU_CTRL_EOImodeNS;
Feng Kan32289502014-07-30 14:56:59 -0700459
460 /*
461 * Preserve bypass disable bits to be written back later
462 */
463 bypass = readl(cpu_base + GIC_CPU_CTRL);
464 bypass &= GICC_DIS_BYPASS_MASK;
465
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100466 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
Feng Kan32289502014-07-30 14:56:59 -0700467}
468
469
Jon Huntercdbb8132016-06-07 16:12:32 +0100470static void gic_dist_init(struct gic_chip_data *gic)
Russell Kingf27ecac2005-08-18 21:31:00 +0100471{
Grant Likely75294952012-02-14 14:06:57 -0700472 unsigned int i;
Will Deacon267840f2011-08-23 22:20:03 +0100473 u32 cpumask;
Rob Herring4294f8b2011-09-28 21:25:31 -0500474 unsigned int gic_irqs = gic->gic_irqs;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000475 void __iomem *base = gic_data_dist_base(gic);
Russell Kingf27ecac2005-08-18 21:31:00 +0100476
Feng Kane5f81532014-07-30 14:56:58 -0700477 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
Russell Kingf27ecac2005-08-18 21:31:00 +0100478
479 /*
Russell Kingf27ecac2005-08-18 21:31:00 +0100480 * Set all global interrupts to this CPU only.
481 */
Russell King2bb31352013-01-30 23:49:57 +0000482 cpumask = gic_get_cpumask(gic);
483 cpumask |= cpumask << 8;
484 cpumask |= cpumask << 16;
Pawel Molle6afec92010-11-26 13:45:43 +0100485 for (i = 32; i < gic_irqs; i += 4)
Santosh Shilimkar6ac77e42011-03-28 19:27:46 +0530486 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
Russell Kingf27ecac2005-08-18 21:31:00 +0100487
Marc Zyngierd51d0af2014-06-30 16:01:30 +0100488 gic_dist_config(base, gic_irqs, NULL);
Russell Kingf27ecac2005-08-18 21:31:00 +0100489
Feng Kane5f81532014-07-30 14:56:58 -0700490 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
Russell Kingf27ecac2005-08-18 21:31:00 +0100491}
492
Jon Hunterdc9722c2016-05-10 16:14:42 +0100493static int gic_cpu_init(struct gic_chip_data *gic)
Russell Kingf27ecac2005-08-18 21:31:00 +0100494{
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000495 void __iomem *dist_base = gic_data_dist_base(gic);
496 void __iomem *base = gic_data_cpu_base(gic);
Nicolas Pitre384a2902012-04-11 18:55:48 -0400497 unsigned int cpu_mask, cpu = smp_processor_id();
Russell King9395f6e2010-11-11 23:10:30 +0000498 int i;
499
Russell King9395f6e2010-11-11 23:10:30 +0000500 /*
Jon Hunter567e5a02015-07-31 09:44:11 +0100501 * Setting up the CPU map is only relevant for the primary GIC
502 * because any nested/secondary GICs do not directly interface
503 * with the CPU(s).
Nicolas Pitre384a2902012-04-11 18:55:48 -0400504 */
Jon Hunter567e5a02015-07-31 09:44:11 +0100505 if (gic == &gic_data[0]) {
506 /*
507 * Get what the GIC says our CPU mask is.
508 */
Jon Hunterdc9722c2016-05-10 16:14:42 +0100509 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
510 return -EINVAL;
511
Marc Zyngier25fc11a2016-04-22 12:25:33 +0100512 gic_check_cpu_features();
Jon Hunter567e5a02015-07-31 09:44:11 +0100513 cpu_mask = gic_get_cpumask(gic);
514 gic_cpu_map[cpu] = cpu_mask;
Nicolas Pitre384a2902012-04-11 18:55:48 -0400515
Jon Hunter567e5a02015-07-31 09:44:11 +0100516 /*
517 * Clear our mask from the other map entries in case they're
518 * still undefined.
519 */
520 for (i = 0; i < NR_GIC_CPU_IF; i++)
521 if (i != cpu)
522 gic_cpu_map[i] &= ~cpu_mask;
523 }
Nicolas Pitre384a2902012-04-11 18:55:48 -0400524
Marc Zyngierd51d0af2014-06-30 16:01:30 +0100525 gic_cpu_config(dist_base, NULL);
Russell King9395f6e2010-11-11 23:10:30 +0000526
Feng Kane5f81532014-07-30 14:56:58 -0700527 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
Jon Hunter4c2880b2015-07-31 09:44:12 +0100528 gic_cpu_if_up(gic);
Jon Hunterdc9722c2016-05-10 16:14:42 +0100529
530 return 0;
Russell Kingf27ecac2005-08-18 21:31:00 +0100531}
532
Jon Hunter4c2880b2015-07-31 09:44:12 +0100533int gic_cpu_if_down(unsigned int gic_nr)
Nicolas Pitre10d9eb82013-03-19 23:59:04 -0400534{
Jon Hunter4c2880b2015-07-31 09:44:12 +0100535 void __iomem *cpu_base;
Feng Kan32289502014-07-30 14:56:59 -0700536 u32 val = 0;
537
Linus Walleija27d21e2015-12-18 10:44:53 +0100538 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
Jon Hunter4c2880b2015-07-31 09:44:12 +0100539 return -EINVAL;
540
541 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
Feng Kan32289502014-07-30 14:56:59 -0700542 val = readl(cpu_base + GIC_CPU_CTRL);
543 val &= ~GICC_ENABLE;
544 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
Jon Hunter4c2880b2015-07-31 09:44:12 +0100545
546 return 0;
Nicolas Pitre10d9eb82013-03-19 23:59:04 -0400547}
548
Jon Hunter9c8eddd2016-06-07 16:12:34 +0100549#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
Colin Cross254056f2011-02-10 12:54:10 -0800550/*
551 * Saves the GIC distributor registers during suspend or idle. Must be called
552 * with interrupts disabled but before powering down the GIC. After calling
553 * this function, no interrupts will be delivered by the GIC, and another
554 * platform-specific wakeup source must be enabled.
555 */
Jon Huntercdbb8132016-06-07 16:12:32 +0100556void gic_dist_save(struct gic_chip_data *gic)
Colin Cross254056f2011-02-10 12:54:10 -0800557{
558 unsigned int gic_irqs;
559 void __iomem *dist_base;
560 int i;
561
Jon Hunter6e5b5922016-05-10 16:14:43 +0100562 if (WARN_ON(!gic))
563 return;
Colin Cross254056f2011-02-10 12:54:10 -0800564
Jon Hunter6e5b5922016-05-10 16:14:43 +0100565 gic_irqs = gic->gic_irqs;
566 dist_base = gic_data_dist_base(gic);
Colin Cross254056f2011-02-10 12:54:10 -0800567
568 if (!dist_base)
569 return;
570
571 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
Jon Hunter6e5b5922016-05-10 16:14:43 +0100572 gic->saved_spi_conf[i] =
Colin Cross254056f2011-02-10 12:54:10 -0800573 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
574
575 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
Jon Hunter6e5b5922016-05-10 16:14:43 +0100576 gic->saved_spi_target[i] =
Colin Cross254056f2011-02-10 12:54:10 -0800577 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
578
579 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
Jon Hunter6e5b5922016-05-10 16:14:43 +0100580 gic->saved_spi_enable[i] =
Colin Cross254056f2011-02-10 12:54:10 -0800581 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000582
583 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
Jon Hunter6e5b5922016-05-10 16:14:43 +0100584 gic->saved_spi_active[i] =
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000585 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
Colin Cross254056f2011-02-10 12:54:10 -0800586}
587
588/*
589 * Restores the GIC distributor registers during resume or when coming out of
590 * idle. Must be called before enabling interrupts. If a level interrupt
591 * that occured while the GIC was suspended is still present, it will be
592 * handled normally, but any edge interrupts that occured will not be seen by
593 * the GIC and need to be handled by the platform-specific wakeup source.
594 */
Jon Huntercdbb8132016-06-07 16:12:32 +0100595void gic_dist_restore(struct gic_chip_data *gic)
Colin Cross254056f2011-02-10 12:54:10 -0800596{
597 unsigned int gic_irqs;
598 unsigned int i;
599 void __iomem *dist_base;
600
Jon Hunter6e5b5922016-05-10 16:14:43 +0100601 if (WARN_ON(!gic))
602 return;
Colin Cross254056f2011-02-10 12:54:10 -0800603
Jon Hunter6e5b5922016-05-10 16:14:43 +0100604 gic_irqs = gic->gic_irqs;
605 dist_base = gic_data_dist_base(gic);
Colin Cross254056f2011-02-10 12:54:10 -0800606
607 if (!dist_base)
608 return;
609
Feng Kane5f81532014-07-30 14:56:58 -0700610 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
Colin Cross254056f2011-02-10 12:54:10 -0800611
612 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
Jon Hunter6e5b5922016-05-10 16:14:43 +0100613 writel_relaxed(gic->saved_spi_conf[i],
Colin Cross254056f2011-02-10 12:54:10 -0800614 dist_base + GIC_DIST_CONFIG + i * 4);
615
616 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
Feng Kane5f81532014-07-30 14:56:58 -0700617 writel_relaxed(GICD_INT_DEF_PRI_X4,
Colin Cross254056f2011-02-10 12:54:10 -0800618 dist_base + GIC_DIST_PRI + i * 4);
619
620 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
Jon Hunter6e5b5922016-05-10 16:14:43 +0100621 writel_relaxed(gic->saved_spi_target[i],
Colin Cross254056f2011-02-10 12:54:10 -0800622 dist_base + GIC_DIST_TARGET + i * 4);
623
Marc Zyngier92eda4a2015-11-16 19:13:27 +0000624 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
625 writel_relaxed(GICD_INT_EN_CLR_X32,
626 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
Jon Hunter6e5b5922016-05-10 16:14:43 +0100627 writel_relaxed(gic->saved_spi_enable[i],
Colin Cross254056f2011-02-10 12:54:10 -0800628 dist_base + GIC_DIST_ENABLE_SET + i * 4);
Marc Zyngier92eda4a2015-11-16 19:13:27 +0000629 }
Colin Cross254056f2011-02-10 12:54:10 -0800630
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000631 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
632 writel_relaxed(GICD_INT_EN_CLR_X32,
633 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
Jon Hunter6e5b5922016-05-10 16:14:43 +0100634 writel_relaxed(gic->saved_spi_active[i],
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000635 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
636 }
637
Feng Kane5f81532014-07-30 14:56:58 -0700638 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
Colin Cross254056f2011-02-10 12:54:10 -0800639}
640
Jon Huntercdbb8132016-06-07 16:12:32 +0100641void gic_cpu_save(struct gic_chip_data *gic)
Colin Cross254056f2011-02-10 12:54:10 -0800642{
643 int i;
644 u32 *ptr;
645 void __iomem *dist_base;
646 void __iomem *cpu_base;
647
Jon Hunter6e5b5922016-05-10 16:14:43 +0100648 if (WARN_ON(!gic))
649 return;
Colin Cross254056f2011-02-10 12:54:10 -0800650
Jon Hunter6e5b5922016-05-10 16:14:43 +0100651 dist_base = gic_data_dist_base(gic);
652 cpu_base = gic_data_cpu_base(gic);
Colin Cross254056f2011-02-10 12:54:10 -0800653
654 if (!dist_base || !cpu_base)
655 return;
656
Jon Hunter6e5b5922016-05-10 16:14:43 +0100657 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
Colin Cross254056f2011-02-10 12:54:10 -0800658 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
659 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
660
Jon Hunter6e5b5922016-05-10 16:14:43 +0100661 ptr = raw_cpu_ptr(gic->saved_ppi_active);
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000662 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
663 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
664
Jon Hunter6e5b5922016-05-10 16:14:43 +0100665 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
Colin Cross254056f2011-02-10 12:54:10 -0800666 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
667 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
668
669}
670
Jon Huntercdbb8132016-06-07 16:12:32 +0100671void gic_cpu_restore(struct gic_chip_data *gic)
Colin Cross254056f2011-02-10 12:54:10 -0800672{
673 int i;
674 u32 *ptr;
675 void __iomem *dist_base;
676 void __iomem *cpu_base;
677
Jon Hunter6e5b5922016-05-10 16:14:43 +0100678 if (WARN_ON(!gic))
679 return;
Colin Cross254056f2011-02-10 12:54:10 -0800680
Jon Hunter6e5b5922016-05-10 16:14:43 +0100681 dist_base = gic_data_dist_base(gic);
682 cpu_base = gic_data_cpu_base(gic);
Colin Cross254056f2011-02-10 12:54:10 -0800683
684 if (!dist_base || !cpu_base)
685 return;
686
Jon Hunter6e5b5922016-05-10 16:14:43 +0100687 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
Marc Zyngier92eda4a2015-11-16 19:13:27 +0000688 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
689 writel_relaxed(GICD_INT_EN_CLR_X32,
690 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
Colin Cross254056f2011-02-10 12:54:10 -0800691 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
Marc Zyngier92eda4a2015-11-16 19:13:27 +0000692 }
Colin Cross254056f2011-02-10 12:54:10 -0800693
Jon Hunter6e5b5922016-05-10 16:14:43 +0100694 ptr = raw_cpu_ptr(gic->saved_ppi_active);
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000695 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
696 writel_relaxed(GICD_INT_EN_CLR_X32,
697 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
698 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
699 }
700
Jon Hunter6e5b5922016-05-10 16:14:43 +0100701 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
Colin Cross254056f2011-02-10 12:54:10 -0800702 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
703 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
704
705 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
Feng Kane5f81532014-07-30 14:56:58 -0700706 writel_relaxed(GICD_INT_DEF_PRI_X4,
707 dist_base + GIC_DIST_PRI + i * 4);
Colin Cross254056f2011-02-10 12:54:10 -0800708
Feng Kane5f81532014-07-30 14:56:58 -0700709 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
Jon Hunter6e5b5922016-05-10 16:14:43 +0100710 gic_cpu_if_up(gic);
Colin Cross254056f2011-02-10 12:54:10 -0800711}
712
713static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
714{
715 int i;
716
Linus Walleija27d21e2015-12-18 10:44:53 +0100717 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
Marc Zyngierdb0d4db2011-11-12 16:09:49 +0000718#ifdef CONFIG_GIC_NON_BANKED
719 /* Skip over unused GICs */
720 if (!gic_data[i].get_base)
721 continue;
722#endif
Colin Cross254056f2011-02-10 12:54:10 -0800723 switch (cmd) {
724 case CPU_PM_ENTER:
Jon Hunter6e5b5922016-05-10 16:14:43 +0100725 gic_cpu_save(&gic_data[i]);
Colin Cross254056f2011-02-10 12:54:10 -0800726 break;
727 case CPU_PM_ENTER_FAILED:
728 case CPU_PM_EXIT:
Jon Hunter6e5b5922016-05-10 16:14:43 +0100729 gic_cpu_restore(&gic_data[i]);
Colin Cross254056f2011-02-10 12:54:10 -0800730 break;
731 case CPU_CLUSTER_PM_ENTER:
Jon Hunter6e5b5922016-05-10 16:14:43 +0100732 gic_dist_save(&gic_data[i]);
Colin Cross254056f2011-02-10 12:54:10 -0800733 break;
734 case CPU_CLUSTER_PM_ENTER_FAILED:
735 case CPU_CLUSTER_PM_EXIT:
Jon Hunter6e5b5922016-05-10 16:14:43 +0100736 gic_dist_restore(&gic_data[i]);
Colin Cross254056f2011-02-10 12:54:10 -0800737 break;
738 }
739 }
740
741 return NOTIFY_OK;
742}
743
744static struct notifier_block gic_notifier_block = {
745 .notifier_call = gic_notifier,
746};
747
Jon Huntercdbb8132016-06-07 16:12:32 +0100748static int gic_pm_init(struct gic_chip_data *gic)
Colin Cross254056f2011-02-10 12:54:10 -0800749{
750 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
751 sizeof(u32));
Jon Hunterdc9722c2016-05-10 16:14:42 +0100752 if (WARN_ON(!gic->saved_ppi_enable))
753 return -ENOMEM;
Colin Cross254056f2011-02-10 12:54:10 -0800754
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000755 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
756 sizeof(u32));
Jon Hunterdc9722c2016-05-10 16:14:42 +0100757 if (WARN_ON(!gic->saved_ppi_active))
758 goto free_ppi_enable;
Marc Zyngier1c7d4dd2015-11-16 19:13:28 +0000759
Colin Cross254056f2011-02-10 12:54:10 -0800760 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
761 sizeof(u32));
Jon Hunterdc9722c2016-05-10 16:14:42 +0100762 if (WARN_ON(!gic->saved_ppi_conf))
763 goto free_ppi_active;
Colin Cross254056f2011-02-10 12:54:10 -0800764
Marc Zyngierabdd7b92011-11-25 17:58:19 +0100765 if (gic == &gic_data[0])
766 cpu_pm_register_notifier(&gic_notifier_block);
Jon Hunterdc9722c2016-05-10 16:14:42 +0100767
768 return 0;
769
770free_ppi_active:
771 free_percpu(gic->saved_ppi_active);
772free_ppi_enable:
773 free_percpu(gic->saved_ppi_enable);
774
775 return -ENOMEM;
Colin Cross254056f2011-02-10 12:54:10 -0800776}
777#else
Jon Huntercdbb8132016-06-07 16:12:32 +0100778static int gic_pm_init(struct gic_chip_data *gic)
Colin Cross254056f2011-02-10 12:54:10 -0800779{
Jon Hunterdc9722c2016-05-10 16:14:42 +0100780 return 0;
Colin Cross254056f2011-02-10 12:54:10 -0800781}
782#endif
783
Rob Herringb1cffeb2012-11-26 15:05:48 -0600784#ifdef CONFIG_SMP
Stephen Boyd68593582014-03-04 17:02:01 -0800785static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
Rob Herringb1cffeb2012-11-26 15:05:48 -0600786{
787 int cpu;
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400788 unsigned long flags, map = 0;
789
Marc Zyngier059e2322016-08-09 07:50:44 +0100790 if (unlikely(nr_cpu_ids == 1)) {
791 /* Only one CPU? let's do a self-IPI... */
792 writel_relaxed(2 << 24 | irq,
793 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
794 return;
795 }
796
Marc Zyngier04c8b0f2016-06-27 18:11:43 +0100797 gic_lock_irqsave(flags);
Rob Herringb1cffeb2012-11-26 15:05:48 -0600798
799 /* Convert our logical CPU mask into a physical one. */
800 for_each_cpu(cpu, mask)
Javi Merino91bdf0d2013-02-19 13:52:22 +0000801 map |= gic_cpu_map[cpu];
Rob Herringb1cffeb2012-11-26 15:05:48 -0600802
803 /*
804 * Ensure that stores to Normal memory are visible to the
Will Deacon8adbf572014-02-20 17:42:07 +0000805 * other CPUs before they observe us issuing the IPI.
Rob Herringb1cffeb2012-11-26 15:05:48 -0600806 */
Will Deacon8adbf572014-02-20 17:42:07 +0000807 dmb(ishst);
Rob Herringb1cffeb2012-11-26 15:05:48 -0600808
809 /* this always happens on GIC0 */
810 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400811
Marc Zyngier04c8b0f2016-06-27 18:11:43 +0100812 gic_unlock_irqrestore(flags);
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400813}
814#endif
815
816#ifdef CONFIG_BL_SWITCHER
817/*
Nicolas Pitre14d2ca62012-11-28 18:48:19 -0500818 * gic_send_sgi - send a SGI directly to given CPU interface number
819 *
820 * cpu_id: the ID for the destination CPU interface
821 * irq: the IPI number to send a SGI for
822 */
823void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
824{
825 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
826 cpu_id = 1 << cpu_id;
827 /* this always happens on GIC0 */
828 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
829}
830
831/*
Nicolas Pitreed967622012-07-05 21:33:26 -0400832 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
833 *
834 * @cpu: the logical CPU number to get the GIC ID for.
835 *
836 * Return the CPU interface ID for the given logical CPU number,
837 * or -1 if the CPU number is too large or the interface ID is
838 * unknown (more than one bit set).
839 */
840int gic_get_cpu_id(unsigned int cpu)
841{
842 unsigned int cpu_bit;
843
844 if (cpu >= NR_GIC_CPU_IF)
845 return -1;
846 cpu_bit = gic_cpu_map[cpu];
847 if (cpu_bit & (cpu_bit - 1))
848 return -1;
849 return __ffs(cpu_bit);
850}
851
852/*
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400853 * gic_migrate_target - migrate IRQs to another CPU interface
854 *
855 * @new_cpu_id: the CPU target ID to migrate IRQs to
856 *
857 * Migrate all peripheral interrupts with a target matching the current CPU
858 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
859 * is also updated. Targets to other CPU interfaces are unchanged.
860 * This must be called with IRQs locally disabled.
861 */
862void gic_migrate_target(unsigned int new_cpu_id)
863{
864 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
865 void __iomem *dist_base;
866 int i, ror_val, cpu = smp_processor_id();
867 u32 val, cur_target_mask, active_mask;
868
Linus Walleija27d21e2015-12-18 10:44:53 +0100869 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400870
871 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
872 if (!dist_base)
873 return;
874 gic_irqs = gic_data[gic_nr].gic_irqs;
875
876 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
877 cur_target_mask = 0x01010101 << cur_cpu_id;
878 ror_val = (cur_cpu_id - new_cpu_id) & 31;
879
Marc Zyngier04c8b0f2016-06-27 18:11:43 +0100880 gic_lock();
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400881
882 /* Update the target interface for this logical CPU */
883 gic_cpu_map[cpu] = 1 << new_cpu_id;
884
885 /*
886 * Find all the peripheral interrupts targetting the current
887 * CPU interface and migrate them to the new CPU interface.
888 * We skip DIST_TARGET 0 to 7 as they are read-only.
889 */
890 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
891 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
892 active_mask = val & cur_target_mask;
893 if (active_mask) {
894 val &= ~active_mask;
895 val |= ror32(active_mask, ror_val);
896 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
897 }
898 }
899
Marc Zyngier04c8b0f2016-06-27 18:11:43 +0100900 gic_unlock();
Nicolas Pitre1a6b69b2012-04-12 01:40:31 -0400901
902 /*
903 * Now let's migrate and clear any potential SGIs that might be
904 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
905 * is a banked register, we can only forward the SGI using
906 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
907 * doesn't use that information anyway.
908 *
909 * For the same reason we do not adjust SGI source information
910 * for previously sent SGIs by us to other CPUs either.
911 */
912 for (i = 0; i < 16; i += 4) {
913 int j;
914 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
915 if (!val)
916 continue;
917 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
918 for (j = i; j < i + 4; j++) {
919 if (val & 0xff)
920 writel_relaxed((1 << (new_cpu_id + 16)) | j,
921 dist_base + GIC_DIST_SOFTINT);
922 val >>= 8;
923 }
924 }
Rob Herringb1cffeb2012-11-26 15:05:48 -0600925}
Nicolas Pitreeeb44652012-11-28 18:17:25 -0500926
927/*
928 * gic_get_sgir_physaddr - get the physical address for the SGI register
929 *
930 * REturn the physical address of the SGI register to be used
931 * by some early assembly code when the kernel is not yet available.
932 */
933static unsigned long gic_dist_physaddr;
934
935unsigned long gic_get_sgir_physaddr(void)
936{
937 if (!gic_dist_physaddr)
938 return 0;
939 return gic_dist_physaddr + GIC_DIST_SOFTINT;
940}
941
Baoyou Xie89c59cc2016-09-07 19:26:45 +0800942static void __init gic_init_physaddr(struct device_node *node)
Nicolas Pitreeeb44652012-11-28 18:17:25 -0500943{
944 struct resource res;
945 if (of_address_to_resource(node, 0, &res) == 0) {
946 gic_dist_physaddr = res.start;
947 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
948 }
949}
950
951#else
952#define gic_init_physaddr(node) do { } while (0)
Rob Herringb1cffeb2012-11-26 15:05:48 -0600953#endif
954
Grant Likely75294952012-02-14 14:06:57 -0700955static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
956 irq_hw_number_t hw)
957{
Linus Walleij58b89642015-10-24 00:15:53 +0200958 struct gic_chip_data *gic = d->host_data;
Marc Zyngier0b996fd2015-08-26 17:00:44 +0100959
Grant Likely75294952012-02-14 14:06:57 -0700960 if (hw < 32) {
961 irq_set_percpu_devid(irq);
Linus Walleij58b89642015-10-24 00:15:53 +0200962 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
Yingjoe Chen9a1091e2014-11-25 16:04:19 +0800963 handle_percpu_devid_irq, NULL, NULL);
Rob Herringd17cab42015-08-29 18:01:22 -0500964 irq_set_status_flags(irq, IRQ_NOAUTOEN);
Grant Likely75294952012-02-14 14:06:57 -0700965 } else {
Linus Walleij58b89642015-10-24 00:15:53 +0200966 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
Yingjoe Chen9a1091e2014-11-25 16:04:19 +0800967 handle_fasteoi_irq, NULL, NULL);
Rob Herringd17cab42015-08-29 18:01:22 -0500968 irq_set_probe(irq);
Grant Likely75294952012-02-14 14:06:57 -0700969 }
Grant Likely75294952012-02-14 14:06:57 -0700970 return 0;
971}
972
Sricharan R006e9832013-12-03 15:57:22 +0530973static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
974{
Sricharan R006e9832013-12-03 15:57:22 +0530975}
976
Marc Zyngierf833f572015-10-13 12:51:33 +0100977static int gic_irq_domain_translate(struct irq_domain *d,
978 struct irq_fwspec *fwspec,
979 unsigned long *hwirq,
980 unsigned int *type)
981{
982 if (is_of_node(fwspec->fwnode)) {
983 if (fwspec->param_count < 3)
984 return -EINVAL;
985
986 /* Get the interrupt number and add 16 to skip over SGIs */
987 *hwirq = fwspec->param[1] + 16;
988
989 /*
990 * For SPIs, we need to add 16 more to get the GIC irq
991 * ID number
992 */
993 if (!fwspec->param[0])
994 *hwirq += 16;
995
996 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
997 return 0;
998 }
999
Suravee Suthikulpanit75aba7b2015-12-10 08:55:28 -08001000 if (is_fwnode_irqchip(fwspec->fwnode)) {
Marc Zyngier891ae762015-10-13 12:51:40 +01001001 if(fwspec->param_count != 2)
1002 return -EINVAL;
1003
1004 *hwirq = fwspec->param[0];
1005 *type = fwspec->param[1];
1006 return 0;
1007 }
1008
Marc Zyngierf833f572015-10-13 12:51:33 +01001009 return -EINVAL;
1010}
1011
Richard Cochran93131f72016-07-13 17:16:04 +00001012static int gic_starting_cpu(unsigned int cpu)
Catalin Marinasc0114702013-01-14 18:05:37 +00001013{
Richard Cochran93131f72016-07-13 17:16:04 +00001014 gic_cpu_init(&gic_data[0]);
1015 return 0;
Catalin Marinasc0114702013-01-14 18:05:37 +00001016}
1017
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08001018static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1019 unsigned int nr_irqs, void *arg)
1020{
1021 int i, ret;
1022 irq_hw_number_t hwirq;
1023 unsigned int type = IRQ_TYPE_NONE;
Marc Zyngierf833f572015-10-13 12:51:33 +01001024 struct irq_fwspec *fwspec = arg;
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08001025
Marc Zyngierf833f572015-10-13 12:51:33 +01001026 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08001027 if (ret)
1028 return ret;
1029
1030 for (i = 0; i < nr_irqs; i++)
1031 gic_irq_domain_map(domain, virq + i, hwirq + i);
1032
1033 return 0;
1034}
1035
1036static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
Marc Zyngierf833f572015-10-13 12:51:33 +01001037 .translate = gic_irq_domain_translate,
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08001038 .alloc = gic_irq_domain_alloc,
1039 .free = irq_domain_free_irqs_top,
1040};
1041
Stephen Boyd68593582014-03-04 17:02:01 -08001042static const struct irq_domain_ops gic_irq_domain_ops = {
Grant Likely75294952012-02-14 14:06:57 -07001043 .map = gic_irq_domain_map,
Sricharan R006e9832013-12-03 15:57:22 +05301044 .unmap = gic_irq_domain_unmap,
Rob Herring4294f8b2011-09-28 21:25:31 -05001045};
1046
Jon Hunterfaea6452016-06-07 16:12:31 +01001047static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1048 const char *name, bool use_eoimode1)
Russell Kingb580b892010-12-04 15:55:14 +00001049{
Linus Walleij58b89642015-10-24 00:15:53 +02001050 /* Initialize irq_chip */
Jon Hunterc2baa2f2016-05-10 16:14:41 +01001051 gic->chip = gic_chip;
Jon Hunterfaea6452016-06-07 16:12:31 +01001052 gic->chip.name = name;
1053 gic->chip.parent_device = dev;
Jon Hunterc2baa2f2016-05-10 16:14:41 +01001054
Jon Hunterfaea6452016-06-07 16:12:31 +01001055 if (use_eoimode1) {
Jon Hunterc2baa2f2016-05-10 16:14:41 +01001056 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1057 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1058 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
Linus Walleij58b89642015-10-24 00:15:53 +02001059 }
1060
Jon Hunter7bf29d32016-02-09 15:24:56 +00001061#ifdef CONFIG_SMP
Jon Hunterf673b9b2016-05-10 16:14:44 +01001062 if (gic == &gic_data[0])
Jon Hunter7bf29d32016-02-09 15:24:56 +00001063 gic->chip.irq_set_affinity = gic_set_affinity;
1064#endif
Jon Hunterfaea6452016-06-07 16:12:31 +01001065}
1066
1067static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1068 struct fwnode_handle *handle)
1069{
1070 irq_hw_number_t hwirq_base;
1071 int gic_irqs, irq_base, ret;
Jon Hunter7bf29d32016-02-09 15:24:56 +00001072
Jon Hunterf673b9b2016-05-10 16:14:44 +01001073 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
Jon Hunterdc9722c2016-05-10 16:14:42 +01001074 /* Frankein-GIC without banked registers... */
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001075 unsigned int cpu;
1076
1077 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1078 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1079 if (WARN_ON(!gic->dist_base.percpu_base ||
1080 !gic->cpu_base.percpu_base)) {
Jon Hunterdc9722c2016-05-10 16:14:42 +01001081 ret = -ENOMEM;
1082 goto error;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001083 }
1084
1085 for_each_possible_cpu(cpu) {
Tomasz Figa29e697b2014-07-17 17:23:44 +02001086 u32 mpidr = cpu_logical_map(cpu);
1087 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
Jon Hunterf673b9b2016-05-10 16:14:44 +01001088 unsigned long offset = gic->percpu_offset * core_id;
1089 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1090 gic->raw_dist_base + offset;
1091 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1092 gic->raw_cpu_base + offset;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001093 }
1094
1095 gic_set_base_accessor(gic, gic_get_percpu_base);
Jon Hunterdc9722c2016-05-10 16:14:42 +01001096 } else {
1097 /* Normal, sane GIC... */
Jon Hunterf673b9b2016-05-10 16:14:44 +01001098 WARN(gic->percpu_offset,
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001099 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
Jon Hunterf673b9b2016-05-10 16:14:44 +01001100 gic->percpu_offset);
1101 gic->dist_base.common_base = gic->raw_dist_base;
1102 gic->cpu_base.common_base = gic->raw_cpu_base;
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001103 gic_set_base_accessor(gic, gic_get_common_base);
1104 }
Russell Kingbef8f9e2010-12-04 16:50:58 +00001105
Rob Herring4294f8b2011-09-28 21:25:31 -05001106 /*
Rob Herring4294f8b2011-09-28 21:25:31 -05001107 * Find out how many interrupts are supported.
1108 * The GIC only supports up to 1020 interrupt sources.
1109 */
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001110 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
Rob Herring4294f8b2011-09-28 21:25:31 -05001111 gic_irqs = (gic_irqs + 1) * 32;
1112 if (gic_irqs > 1020)
1113 gic_irqs = 1020;
1114 gic->gic_irqs = gic_irqs;
1115
Marc Zyngier891ae762015-10-13 12:51:40 +01001116 if (handle) { /* DT/ACPI */
1117 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1118 &gic_irq_domain_hierarchy_ops,
1119 gic);
1120 } else { /* Legacy support */
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08001121 /*
1122 * For primary GICs, skip over SGIs.
1123 * For secondary GICs, skip over PPIs, too.
1124 */
Jon Hunterf673b9b2016-05-10 16:14:44 +01001125 if (gic == &gic_data[0] && (irq_start & 31) > 0) {
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08001126 hwirq_base = 16;
1127 if (irq_start != -1)
1128 irq_start = (irq_start & ~31) + 16;
1129 } else {
1130 hwirq_base = 32;
1131 }
1132
1133 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1134
Sricharan R006e9832013-12-03 15:57:22 +05301135 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1136 numa_node_id());
Arnd Bergmann287980e2016-05-27 23:23:25 +02001137 if (irq_base < 0) {
Sricharan R006e9832013-12-03 15:57:22 +05301138 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1139 irq_start);
1140 irq_base = irq_start;
1141 }
1142
Marc Zyngier891ae762015-10-13 12:51:40 +01001143 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
Sricharan R006e9832013-12-03 15:57:22 +05301144 hwirq_base, &gic_irq_domain_ops, gic);
Rob Herringf37a53c2011-10-21 17:14:27 -05001145 }
Sricharan R006e9832013-12-03 15:57:22 +05301146
Jon Hunterdc9722c2016-05-10 16:14:42 +01001147 if (WARN_ON(!gic->domain)) {
1148 ret = -ENODEV;
1149 goto error;
1150 }
Russell Kingbef8f9e2010-12-04 16:50:58 +00001151
Rob Herring4294f8b2011-09-28 21:25:31 -05001152 gic_dist_init(gic);
Jon Hunterdc9722c2016-05-10 16:14:42 +01001153 ret = gic_cpu_init(gic);
1154 if (ret)
1155 goto error;
1156
1157 ret = gic_pm_init(gic);
1158 if (ret)
1159 goto error;
1160
1161 return 0;
1162
1163error:
Jon Hunterf673b9b2016-05-10 16:14:44 +01001164 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
Jon Hunterdc9722c2016-05-10 16:14:42 +01001165 free_percpu(gic->dist_base.percpu_base);
1166 free_percpu(gic->cpu_base.percpu_base);
1167 }
1168
Jon Hunterdc9722c2016-05-10 16:14:42 +01001169 return ret;
Russell Kingb580b892010-12-04 15:55:14 +00001170}
1171
Jon Hunterd6ce5642016-06-07 16:12:30 +01001172static int __init __gic_init_bases(struct gic_chip_data *gic,
1173 int irq_start,
1174 struct fwnode_handle *handle)
1175{
Jon Hunterfaea6452016-06-07 16:12:31 +01001176 char *name;
1177 int i, ret;
Jon Hunterd6ce5642016-06-07 16:12:30 +01001178
1179 if (WARN_ON(!gic || gic->domain))
1180 return -EINVAL;
1181
1182 if (gic == &gic_data[0]) {
1183 /*
1184 * Initialize the CPU interface map to all CPUs.
1185 * It will be refined as each CPU probes its ID.
1186 * This is only necessary for the primary GIC.
1187 */
1188 for (i = 0; i < NR_GIC_CPU_IF; i++)
1189 gic_cpu_map[i] = 0xff;
1190#ifdef CONFIG_SMP
1191 set_smp_cross_call(gic_raise_softirq);
Jon Hunterd6ce5642016-06-07 16:12:30 +01001192#endif
Richard Cochran93131f72016-07-13 17:16:04 +00001193 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
Thomas Gleixner73c1b412016-12-21 20:19:54 +01001194 "irqchip/arm/gic:starting",
Richard Cochran93131f72016-07-13 17:16:04 +00001195 gic_starting_cpu, NULL);
Jon Hunterd6ce5642016-06-07 16:12:30 +01001196 set_handle_irq(gic_handle_irq);
1197 if (static_key_true(&supports_deactivate))
1198 pr_info("GIC: Using split EOI/Deactivate mode\n");
1199 }
1200
Jon Hunterfaea6452016-06-07 16:12:31 +01001201 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1202 name = kasprintf(GFP_KERNEL, "GICv2");
1203 gic_init_chip(gic, NULL, name, true);
1204 } else {
1205 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1206 gic_init_chip(gic, NULL, name, false);
1207 }
1208
1209 ret = gic_init_bases(gic, irq_start, handle);
1210 if (ret)
1211 kfree(name);
1212
1213 return ret;
Jon Hunterd6ce5642016-06-07 16:12:30 +01001214}
1215
Marc Zyngiere81a7cd2015-10-13 12:51:39 +01001216void __init gic_init(unsigned int gic_nr, int irq_start,
1217 void __iomem *dist_base, void __iomem *cpu_base)
Marc Zyngier4a6ac302015-09-01 10:08:53 +01001218{
Jon Hunterf673b9b2016-05-10 16:14:44 +01001219 struct gic_chip_data *gic;
1220
1221 if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
1222 return;
1223
Marc Zyngier4a6ac302015-09-01 10:08:53 +01001224 /*
1225 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1226 * bother with these...
1227 */
1228 static_key_slow_dec(&supports_deactivate);
Jon Hunterf673b9b2016-05-10 16:14:44 +01001229
1230 gic = &gic_data[gic_nr];
1231 gic->raw_dist_base = dist_base;
1232 gic->raw_cpu_base = cpu_base;
1233
1234 __gic_init_bases(gic, irq_start, NULL);
Marc Zyngier4a6ac302015-09-01 10:08:53 +01001235}
1236
Jon Hunterd6490462016-05-10 16:14:45 +01001237static void gic_teardown(struct gic_chip_data *gic)
1238{
1239 if (WARN_ON(!gic))
1240 return;
1241
1242 if (gic->raw_dist_base)
1243 iounmap(gic->raw_dist_base);
1244 if (gic->raw_cpu_base)
1245 iounmap(gic->raw_cpu_base);
Catalin Marinasb3a1bde2007-02-14 19:14:56 +01001246}
1247
Rob Herringb3f7ed02011-09-28 21:27:52 -05001248#ifdef CONFIG_OF
Sachin Kamat46f101d2013-03-13 15:05:15 +05301249static int gic_cnt __initdata;
Rob Herringb3f7ed02011-09-28 21:27:52 -05001250
Marc Zyngier12e14062015-09-13 12:14:31 +01001251static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1252{
1253 struct resource cpuif_res;
1254
1255 of_address_to_resource(node, 1, &cpuif_res);
1256
1257 if (!is_hyp_mode_available())
1258 return false;
1259 if (resource_size(&cpuif_res) < SZ_8K)
1260 return false;
1261 if (resource_size(&cpuif_res) == SZ_128K) {
1262 u32 val_low, val_high;
1263
1264 /*
1265 * Verify that we have the first 4kB of a GIC400
1266 * aliased over the first 64kB by checking the
1267 * GICC_IIDR register on both ends.
1268 */
1269 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1270 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1271 if ((val_low & 0xffff0fff) != 0x0202043B ||
1272 val_low != val_high)
1273 return false;
1274
1275 /*
1276 * Move the base up by 60kB, so that we have a 8kB
1277 * contiguous region, which allows us to use GICC_DIR
1278 * at its normal offset. Please pass me that bucket.
1279 */
1280 *base += 0xf000;
1281 cpuif_res.start += 0xf000;
Marc Zyngierfd5bed42016-10-20 11:21:01 +01001282 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
Marc Zyngier12e14062015-09-13 12:14:31 +01001283 &cpuif_res.start);
1284 }
1285
1286 return true;
1287}
1288
Jon Hunter9c8eddd2016-06-07 16:12:34 +01001289static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
Jon Hunterd6490462016-05-10 16:14:45 +01001290{
1291 if (!gic || !node)
1292 return -EINVAL;
1293
1294 gic->raw_dist_base = of_iomap(node, 0);
1295 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1296 goto error;
1297
1298 gic->raw_cpu_base = of_iomap(node, 1);
1299 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1300 goto error;
1301
1302 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1303 gic->percpu_offset = 0;
1304
1305 return 0;
1306
1307error:
1308 gic_teardown(gic);
1309
1310 return -ENOMEM;
1311}
1312
Jon Hunter9c8eddd2016-06-07 16:12:34 +01001313int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1314{
1315 int ret;
1316
1317 if (!dev || !dev->of_node || !gic || !irq)
1318 return -EINVAL;
1319
1320 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1321 if (!*gic)
1322 return -ENOMEM;
1323
1324 gic_init_chip(*gic, dev, dev->of_node->name, false);
1325
1326 ret = gic_of_setup(*gic, dev->of_node);
1327 if (ret)
1328 return ret;
1329
1330 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1331 if (ret) {
1332 gic_teardown(*gic);
1333 return ret;
1334 }
1335
1336 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1337
1338 return 0;
1339}
1340
Julien Grall502d6df2016-04-11 16:32:54 +01001341static void __init gic_of_setup_kvm_info(struct device_node *node)
1342{
1343 int ret;
1344 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1345 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1346
1347 gic_v2_kvm_info.type = GIC_V2;
1348
1349 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1350 if (!gic_v2_kvm_info.maint_irq)
1351 return;
1352
1353 ret = of_address_to_resource(node, 2, vctrl_res);
1354 if (ret)
1355 return;
1356
1357 ret = of_address_to_resource(node, 3, vcpu_res);
1358 if (ret)
1359 return;
1360
1361 gic_set_kvm_info(&gic_v2_kvm_info);
1362}
1363
Linus Walleij8673c1d2015-10-24 00:15:52 +02001364int __init
Stephen Boyd68593582014-03-04 17:02:01 -08001365gic_of_init(struct device_node *node, struct device_node *parent)
Rob Herringb3f7ed02011-09-28 21:27:52 -05001366{
Jon Hunterf673b9b2016-05-10 16:14:44 +01001367 struct gic_chip_data *gic;
Jon Hunterdc9722c2016-05-10 16:14:42 +01001368 int irq, ret;
Rob Herringb3f7ed02011-09-28 21:27:52 -05001369
1370 if (WARN_ON(!node))
1371 return -ENODEV;
1372
Jon Hunterf673b9b2016-05-10 16:14:44 +01001373 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1374 return -EINVAL;
Rob Herringb3f7ed02011-09-28 21:27:52 -05001375
Jon Hunterf673b9b2016-05-10 16:14:44 +01001376 gic = &gic_data[gic_cnt];
1377
Jon Hunterd6490462016-05-10 16:14:45 +01001378 ret = gic_of_setup(gic, node);
1379 if (ret)
1380 return ret;
Rob Herringb3f7ed02011-09-28 21:27:52 -05001381
Marc Zyngier0b996fd2015-08-26 17:00:44 +01001382 /*
1383 * Disable split EOI/Deactivate if either HYP is not available
1384 * or the CPU interface is too small.
1385 */
Jon Hunterf673b9b2016-05-10 16:14:44 +01001386 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
Marc Zyngier0b996fd2015-08-26 17:00:44 +01001387 static_key_slow_dec(&supports_deactivate);
1388
Jon Hunterf673b9b2016-05-10 16:14:44 +01001389 ret = __gic_init_bases(gic, -1, &node->fwnode);
Jon Hunterdc9722c2016-05-10 16:14:42 +01001390 if (ret) {
Jon Hunterd6490462016-05-10 16:14:45 +01001391 gic_teardown(gic);
Jon Hunterdc9722c2016-05-10 16:14:42 +01001392 return ret;
1393 }
Marc Zyngierdb0d4db2011-11-12 16:09:49 +00001394
Julien Grall502d6df2016-04-11 16:32:54 +01001395 if (!gic_cnt) {
Nicolas Pitreeeb44652012-11-28 18:17:25 -05001396 gic_init_physaddr(node);
Julien Grall502d6df2016-04-11 16:32:54 +01001397 gic_of_setup_kvm_info(node);
1398 }
Rob Herringb3f7ed02011-09-28 21:27:52 -05001399
1400 if (parent) {
1401 irq = irq_of_parse_and_map(node, 0);
1402 gic_cascade_irq(gic_cnt, irq);
1403 }
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +00001404
1405 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
Suravee Suthikulpanit0644b3d2015-12-10 08:55:30 -08001406 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +00001407
Rob Herringb3f7ed02011-09-28 21:27:52 -05001408 gic_cnt++;
1409 return 0;
1410}
Suravee Suthikulpanit144cb082014-07-15 00:03:03 +02001411IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
Linus Walleijfa6e2ee2014-10-01 09:29:22 +02001412IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1413IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
Rob Herring81243e42012-11-20 21:21:40 -06001414IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1415IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
Matthias Bruggera97e80272014-07-03 13:58:52 +02001416IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
Rob Herring81243e42012-11-20 21:21:40 -06001417IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1418IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
Geert Uytterhoeven8709b9e2015-09-14 22:06:43 +02001419IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
Jon Hunter9c8eddd2016-06-07 16:12:34 +01001420#else
1421int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1422{
1423 return -ENOTSUPP;
1424}
Rob Herringb3f7ed02011-09-28 21:27:52 -05001425#endif
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001426
1427#ifdef CONFIG_ACPI
Julien Grallbafa9192016-04-11 16:32:53 +01001428static struct
1429{
1430 phys_addr_t cpu_phys_base;
Julien Grall502d6df2016-04-11 16:32:54 +01001431 u32 maint_irq;
1432 int maint_irq_mode;
1433 phys_addr_t vctrl_base;
1434 phys_addr_t vcpu_base;
Julien Grallbafa9192016-04-11 16:32:53 +01001435} acpi_data __initdata;
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001436
1437static int __init
1438gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1439 const unsigned long end)
1440{
1441 struct acpi_madt_generic_interrupt *processor;
1442 phys_addr_t gic_cpu_base;
1443 static int cpu_base_assigned;
1444
1445 processor = (struct acpi_madt_generic_interrupt *)header;
1446
Al Stone99e3e3a2015-07-06 17:16:48 -06001447 if (BAD_MADT_GICC_ENTRY(processor, end))
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001448 return -EINVAL;
1449
1450 /*
1451 * There is no support for non-banked GICv1/2 register in ACPI spec.
1452 * All CPU interface addresses have to be the same.
1453 */
1454 gic_cpu_base = processor->base_address;
Julien Grallbafa9192016-04-11 16:32:53 +01001455 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001456 return -EINVAL;
1457
Julien Grallbafa9192016-04-11 16:32:53 +01001458 acpi_data.cpu_phys_base = gic_cpu_base;
Julien Grall502d6df2016-04-11 16:32:54 +01001459 acpi_data.maint_irq = processor->vgic_interrupt;
1460 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1461 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1462 acpi_data.vctrl_base = processor->gich_base_address;
1463 acpi_data.vcpu_base = processor->gicv_base_address;
1464
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001465 cpu_base_assigned = 1;
1466 return 0;
1467}
1468
Marc Zyngierf26527b12015-09-28 15:49:14 +01001469/* The things you have to do to just *count* something... */
1470static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1471 const unsigned long end)
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001472{
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001473 return 0;
1474}
1475
Marc Zyngierf26527b12015-09-28 15:49:14 +01001476static bool __init acpi_gic_redist_is_present(void)
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001477{
Marc Zyngierf26527b12015-09-28 15:49:14 +01001478 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1479 acpi_dummy_func, 0) > 0;
1480}
1481
1482static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1483 struct acpi_probe_entry *ape)
1484{
1485 struct acpi_madt_generic_distributor *dist;
1486 dist = (struct acpi_madt_generic_distributor *)header;
1487
1488 return (dist->version == ape->driver_data &&
1489 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1490 !acpi_gic_redist_is_present()));
1491}
1492
1493#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1494#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
Julien Grall502d6df2016-04-11 16:32:54 +01001495#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1496#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1497
1498static void __init gic_acpi_setup_kvm_info(void)
1499{
1500 int irq;
1501 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1502 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1503
1504 gic_v2_kvm_info.type = GIC_V2;
1505
1506 if (!acpi_data.vctrl_base)
1507 return;
1508
1509 vctrl_res->flags = IORESOURCE_MEM;
1510 vctrl_res->start = acpi_data.vctrl_base;
1511 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1512
1513 if (!acpi_data.vcpu_base)
1514 return;
1515
1516 vcpu_res->flags = IORESOURCE_MEM;
1517 vcpu_res->start = acpi_data.vcpu_base;
1518 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1519
1520 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1521 acpi_data.maint_irq_mode,
1522 ACPI_ACTIVE_HIGH);
1523 if (irq <= 0)
1524 return;
1525
1526 gic_v2_kvm_info.maint_irq = irq;
1527
1528 gic_set_kvm_info(&gic_v2_kvm_info);
1529}
Marc Zyngierf26527b12015-09-28 15:49:14 +01001530
1531static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1532 const unsigned long end)
1533{
1534 struct acpi_madt_generic_distributor *dist;
Marc Zyngier891ae762015-10-13 12:51:40 +01001535 struct fwnode_handle *domain_handle;
Jon Hunterf673b9b2016-05-10 16:14:44 +01001536 struct gic_chip_data *gic = &gic_data[0];
Jon Hunterdc9722c2016-05-10 16:14:42 +01001537 int count, ret;
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001538
1539 /* Collect CPU base addresses */
Marc Zyngierf26527b12015-09-28 15:49:14 +01001540 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1541 gic_acpi_parse_madt_cpu, 0);
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001542 if (count <= 0) {
1543 pr_err("No valid GICC entries exist\n");
1544 return -EINVAL;
1545 }
1546
Linus Torvalds7beaa242016-05-19 11:27:09 -07001547 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
Jon Hunterf673b9b2016-05-10 16:14:44 +01001548 if (!gic->raw_cpu_base) {
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001549 pr_err("Unable to map GICC registers\n");
1550 return -ENOMEM;
1551 }
1552
Marc Zyngierf26527b12015-09-28 15:49:14 +01001553 dist = (struct acpi_madt_generic_distributor *)header;
Jon Hunterf673b9b2016-05-10 16:14:44 +01001554 gic->raw_dist_base = ioremap(dist->base_address,
1555 ACPI_GICV2_DIST_MEM_SIZE);
1556 if (!gic->raw_dist_base) {
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001557 pr_err("Unable to map GICD registers\n");
Jon Hunterd6490462016-05-10 16:14:45 +01001558 gic_teardown(gic);
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001559 return -ENOMEM;
1560 }
1561
1562 /*
Marc Zyngier0b996fd2015-08-26 17:00:44 +01001563 * Disable split EOI/Deactivate if HYP is not available. ACPI
1564 * guarantees that we'll always have a GICv2, so the CPU
1565 * interface will always be the right size.
1566 */
1567 if (!is_hyp_mode_available())
1568 static_key_slow_dec(&supports_deactivate);
1569
1570 /*
Marc Zyngier891ae762015-10-13 12:51:40 +01001571 * Initialize GIC instance zero (no multi-GIC support).
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001572 */
Jon Hunterf673b9b2016-05-10 16:14:44 +01001573 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
Marc Zyngier891ae762015-10-13 12:51:40 +01001574 if (!domain_handle) {
1575 pr_err("Unable to allocate domain handle\n");
Jon Hunterd6490462016-05-10 16:14:45 +01001576 gic_teardown(gic);
Marc Zyngier891ae762015-10-13 12:51:40 +01001577 return -ENOMEM;
1578 }
Lorenzo Pieralisid8f4f162015-03-24 17:58:51 +00001579
Jon Hunterf673b9b2016-05-10 16:14:44 +01001580 ret = __gic_init_bases(gic, -1, domain_handle);
Jon Hunterdc9722c2016-05-10 16:14:42 +01001581 if (ret) {
1582 pr_err("Failed to initialise GIC\n");
1583 irq_domain_free_fwnode(domain_handle);
Jon Hunterd6490462016-05-10 16:14:45 +01001584 gic_teardown(gic);
Jon Hunterdc9722c2016-05-10 16:14:42 +01001585 return ret;
1586 }
Marc Zyngier891ae762015-10-13 12:51:40 +01001587
1588 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
Suravee Suthikulpanit0644b3d2015-12-10 08:55:30 -08001589
1590 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1591 gicv2m_init(NULL, gic_data[0].domain);
1592
Julien Grall502d6df2016-04-11 16:32:54 +01001593 gic_acpi_setup_kvm_info();
1594
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001595 return 0;
1596}
Marc Zyngierf26527b12015-09-28 15:49:14 +01001597IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1598 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1599 gic_v2_acpi_init);
1600IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1601 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1602 gic_v2_acpi_init);
Tomasz Nowickid60fc382015-03-24 14:02:49 +00001603#endif