Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Radisys 82600 Embedded chipset Memory Controller kernel module |
| 3 | * (C) 2005 EADS Astrium |
| 4 | * This file may be distributed under the terms of the |
| 5 | * GNU General Public License. |
| 6 | * |
| 7 | * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne |
| 8 | * Harbaugh, Dan Hollis <goemon at anime dot net> and others. |
| 9 | * |
| 10 | * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ |
| 11 | * |
| 12 | * Written with reference to 82600 High Integration Dual PCI System |
| 13 | * Controller Data Book: |
Dave Jiang | c419270 | 2007-07-19 01:49:47 -0700 | [diff] [blame] | 14 | * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 15 | * references to this document given in [] |
| 16 | */ |
| 17 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/init.h> |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 20 | #include <linux/pci.h> |
| 21 | #include <linux/pci_ids.h> |
Hitoshi Mitake | c3c52bc | 2008-04-29 01:03:18 -0700 | [diff] [blame] | 22 | #include <linux/edac.h> |
Mauro Carvalho Chehab | 78d88e8 | 2016-10-29 15:16:34 -0200 | [diff] [blame] | 23 | #include "edac_module.h" |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 24 | |
Michal Marek | 152ba39 | 2011-04-01 12:41:20 +0200 | [diff] [blame] | 25 | #define R82600_REVISION " Ver: 2.0.2" |
Doug Thompson | 929a40e | 2006-07-01 04:35:45 -0700 | [diff] [blame] | 26 | #define EDAC_MOD_STR "r82600_edac" |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 27 | |
Dave Peterson | 537fba2 | 2006-03-26 01:38:40 -0800 | [diff] [blame] | 28 | #define r82600_printk(level, fmt, arg...) \ |
Dave Peterson | e7ecd89 | 2006-03-26 01:38:52 -0800 | [diff] [blame] | 29 | edac_printk(level, "r82600", fmt, ##arg) |
Dave Peterson | 537fba2 | 2006-03-26 01:38:40 -0800 | [diff] [blame] | 30 | |
| 31 | #define r82600_mc_printk(mci, level, fmt, arg...) \ |
Dave Peterson | e7ecd89 | 2006-03-26 01:38:52 -0800 | [diff] [blame] | 32 | edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) |
Dave Peterson | 537fba2 | 2006-03-26 01:38:40 -0800 | [diff] [blame] | 33 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 34 | /* Radisys say "The 82600 integrates a main memory SDRAM controller that |
| 35 | * supports up to four banks of memory. The four banks can support a mix of |
| 36 | * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, |
| 37 | * each of which can be any size from 16MB to 512MB. Both registered (control |
| 38 | * signals buffered) and unbuffered DIMM types are supported. Mixing of |
| 39 | * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs |
| 40 | * is not allowed. The 82600 SDRAM interface operates at the same frequency as |
| 41 | * the CPU bus, 66MHz, 100MHz or 133MHz." |
| 42 | */ |
| 43 | |
| 44 | #define R82600_NR_CSROWS 4 |
| 45 | #define R82600_NR_CHANS 1 |
| 46 | #define R82600_NR_DIMMS 4 |
| 47 | |
| 48 | #define R82600_BRIDGE_ID 0x8200 |
| 49 | |
| 50 | /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ |
| 51 | #define R82600_DRAMC 0x57 /* Various SDRAM related control bits |
| 52 | * all bits are R/W |
| 53 | * |
| 54 | * 7 SDRAM ISA Hole Enable |
| 55 | * 6 Flash Page Mode Enable |
| 56 | * 5 ECC Enable: 1=ECC 0=noECC |
| 57 | * 4 DRAM DIMM Type: 1= |
| 58 | * 3 BIOS Alias Disable |
| 59 | * 2 SDRAM BIOS Flash Write Enable |
| 60 | * 1:0 SDRAM Refresh Rate: 00=Disabled |
| 61 | * 01=7.8usec (256Mbit SDRAMs) |
| 62 | * 10=15.6us 11=125usec |
| 63 | */ |
| 64 | |
| 65 | #define R82600_SDRAMC 0x76 /* "SDRAM Control Register" |
| 66 | * More SDRAM related control bits |
| 67 | * all bits are R/W |
| 68 | * |
| 69 | * 15:8 Reserved. |
| 70 | * |
| 71 | * 7:5 Special SDRAM Mode Select |
| 72 | * |
| 73 | * 4 Force ECC |
| 74 | * |
| 75 | * 1=Drive ECC bits to 0 during |
| 76 | * write cycles (i.e. ECC test mode) |
| 77 | * |
| 78 | * 0=Normal ECC functioning |
| 79 | * |
| 80 | * 3 Enhanced Paging Enable |
| 81 | * |
| 82 | * 2 CAS# Latency 0=3clks 1=2clks |
| 83 | * |
| 84 | * 1 RAS# to CAS# Delay 0=3 1=2 |
| 85 | * |
| 86 | * 0 RAS# Precharge 0=3 1=2 |
| 87 | */ |
| 88 | |
| 89 | #define R82600_EAP 0x80 /* ECC Error Address Pointer Register |
| 90 | * |
| 91 | * 31 Disable Hardware Scrubbing (RW) |
| 92 | * 0=Scrub on corrected read |
| 93 | * 1=Don't scrub on corrected read |
| 94 | * |
| 95 | * 30:12 Error Address Pointer (RO) |
| 96 | * Upper 19 bits of error address |
| 97 | * |
| 98 | * 11:4 Syndrome Bits (RO) |
| 99 | * |
| 100 | * 3 BSERR# on multibit error (RW) |
| 101 | * 1=enable 0=disable |
| 102 | * |
| 103 | * 2 NMI on Single Bit Eror (RW) |
| 104 | * 1=NMI triggered by SBE n.b. other |
| 105 | * prerequeists |
| 106 | * 0=NMI not triggered |
| 107 | * |
| 108 | * 1 MBE (R/WC) |
| 109 | * read 1=MBE at EAP (see above) |
| 110 | * read 0=no MBE, or SBE occurred first |
| 111 | * write 1=Clear MBE status (must also |
| 112 | * clear SBE) |
| 113 | * write 0=NOP |
| 114 | * |
| 115 | * 1 SBE (R/WC) |
| 116 | * read 1=SBE at EAP (see above) |
| 117 | * read 0=no SBE, or MBE occurred first |
| 118 | * write 1=Clear SBE status (must also |
| 119 | * clear MBE) |
| 120 | * write 0=NOP |
| 121 | */ |
| 122 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 123 | #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 124 | * Registers |
| 125 | * |
| 126 | * 7:0 Address lines 30:24 - upper limit of |
| 127 | * each row [p57] |
| 128 | */ |
| 129 | |
| 130 | struct r82600_error_info { |
| 131 | u32 eapr; |
| 132 | }; |
| 133 | |
Rusty Russell | 90ab5ee | 2012-01-13 09:32:20 +1030 | [diff] [blame] | 134 | static bool disable_hardware_scrub; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 135 | |
Dave Jiang | 456a2f9 | 2007-07-19 01:50:10 -0700 | [diff] [blame] | 136 | static struct edac_pci_ctl_info *r82600_pci; |
| 137 | |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 138 | static void r82600_get_error_info(struct mem_ctl_info *mci, |
Douglas Thompson | 052dfb4 | 2007-07-19 01:50:13 -0700 | [diff] [blame] | 139 | struct r82600_error_info *info) |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 140 | { |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 141 | struct pci_dev *pdev; |
| 142 | |
Mauro Carvalho Chehab | fd68750 | 2012-03-16 07:44:18 -0300 | [diff] [blame] | 143 | pdev = to_pci_dev(mci->pdev); |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 144 | pci_read_config_dword(pdev, R82600_EAP, &info->eapr); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 145 | |
| 146 | if (info->eapr & BIT(0)) |
| 147 | /* Clear error to allow next error to be reported [p.62] */ |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 148 | pci_write_bits32(pdev, R82600_EAP, |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 149 | ((u32) BIT(0) & (u32) BIT(1)), |
| 150 | ((u32) BIT(0) & (u32) BIT(1))); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 151 | |
| 152 | if (info->eapr & BIT(1)) |
| 153 | /* Clear error to allow next error to be reported [p.62] */ |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 154 | pci_write_bits32(pdev, R82600_EAP, |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 155 | ((u32) BIT(0) & (u32) BIT(1)), |
| 156 | ((u32) BIT(0) & (u32) BIT(1))); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 157 | } |
| 158 | |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 159 | static int r82600_process_error_info(struct mem_ctl_info *mci, |
Douglas Thompson | 052dfb4 | 2007-07-19 01:50:13 -0700 | [diff] [blame] | 160 | struct r82600_error_info *info, |
| 161 | int handle_errors) |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 162 | { |
| 163 | int error_found; |
| 164 | u32 eapaddr, page; |
| 165 | u32 syndrome; |
| 166 | |
| 167 | error_found = 0; |
| 168 | |
| 169 | /* bits 30:12 store the upper 19 bits of the 32 bit error address */ |
| 170 | eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; |
| 171 | /* Syndrome in bits 11:4 [p.62] */ |
| 172 | syndrome = (info->eapr >> 4) & 0xFF; |
| 173 | |
| 174 | /* the R82600 reports at less than page * |
| 175 | * granularity (upper 19 bits only) */ |
| 176 | page = eapaddr >> PAGE_SHIFT; |
| 177 | |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 178 | if (info->eapr & BIT(0)) { /* CE? */ |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 179 | error_found = 1; |
| 180 | |
| 181 | if (handle_errors) |
Mauro Carvalho Chehab | 9eb07a7 | 2012-06-04 13:27:43 -0300 | [diff] [blame] | 182 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
Mauro Carvalho Chehab | 63b5d1d | 2012-04-16 15:12:13 -0300 | [diff] [blame] | 183 | page, 0, syndrome, |
| 184 | edac_mc_find_csrow_by_page(mci, page), |
| 185 | 0, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 186 | mci->ctl_name, ""); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 187 | } |
| 188 | |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 189 | if (info->eapr & BIT(1)) { /* UE? */ |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 190 | error_found = 1; |
| 191 | |
| 192 | if (handle_errors) |
| 193 | /* 82600 doesn't give enough info */ |
Mauro Carvalho Chehab | 9eb07a7 | 2012-06-04 13:27:43 -0300 | [diff] [blame] | 194 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
Mauro Carvalho Chehab | 63b5d1d | 2012-04-16 15:12:13 -0300 | [diff] [blame] | 195 | page, 0, 0, |
| 196 | edac_mc_find_csrow_by_page(mci, page), |
| 197 | 0, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 198 | mci->ctl_name, ""); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | return error_found; |
| 202 | } |
| 203 | |
| 204 | static void r82600_check(struct mem_ctl_info *mci) |
| 205 | { |
| 206 | struct r82600_error_info info; |
| 207 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 208 | edac_dbg(1, "MC%d\n", mci->mc_idx); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 209 | r82600_get_error_info(mci, &info); |
| 210 | r82600_process_error_info(mci, &info, 1); |
| 211 | } |
| 212 | |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 213 | static inline int ecc_enabled(u8 dramcr) |
| 214 | { |
| 215 | return dramcr & BIT(5); |
| 216 | } |
| 217 | |
| 218 | static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
Douglas Thompson | 052dfb4 | 2007-07-19 01:50:13 -0700 | [diff] [blame] | 219 | u8 dramcr) |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 220 | { |
| 221 | struct csrow_info *csrow; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 222 | struct dimm_info *dimm; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 223 | int index; |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 224 | u8 drbar; /* SDRAM Row Boundary Address Register */ |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 225 | u32 row_high_limit, row_high_limit_last; |
| 226 | u32 reg_sdram, ecc_on, row_base; |
| 227 | |
| 228 | ecc_on = ecc_enabled(dramcr); |
| 229 | reg_sdram = dramcr & BIT(4); |
| 230 | row_high_limit_last = 0; |
| 231 | |
| 232 | for (index = 0; index < mci->nr_csrows; index++) { |
Mauro Carvalho Chehab | de3910eb | 2012-04-24 15:05:43 -0300 | [diff] [blame] | 233 | csrow = mci->csrows[index]; |
| 234 | dimm = csrow->channels[0]->dimm; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 235 | |
| 236 | /* find the DRAM Chip Select Base address and mask */ |
| 237 | pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); |
| 238 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 239 | edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar); |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 240 | |
| 241 | row_high_limit = ((u32) drbar << 24); |
| 242 | /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ |
| 243 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 244 | edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n", |
| 245 | index, row_high_limit, row_high_limit_last); |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 246 | |
| 247 | /* Empty row [p.57] */ |
| 248 | if (row_high_limit == row_high_limit_last) |
| 249 | continue; |
| 250 | |
| 251 | row_base = row_high_limit_last; |
| 252 | |
| 253 | csrow->first_page = row_base >> PAGE_SHIFT; |
| 254 | csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; |
Mauro Carvalho Chehab | a895bf8 | 2012-01-28 09:09:38 -0300 | [diff] [blame] | 255 | |
| 256 | dimm->nr_pages = csrow->last_page - csrow->first_page + 1; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 257 | /* Error address is top 19 bits - so granularity is * |
| 258 | * 14 bits */ |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 259 | dimm->grain = 1 << 14; |
| 260 | dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 261 | /* FIXME - check that this is unknowable with this chipset */ |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 262 | dimm->dtype = DEV_UNKNOWN; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 263 | |
| 264 | /* Mode is global on 82600 */ |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 265 | dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 266 | row_high_limit_last = row_high_limit; |
| 267 | } |
| 268 | } |
| 269 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 270 | static int r82600_probe1(struct pci_dev *pdev, int dev_idx) |
| 271 | { |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 272 | struct mem_ctl_info *mci; |
Mauro Carvalho Chehab | 63b5d1d | 2012-04-16 15:12:13 -0300 | [diff] [blame] | 273 | struct edac_mc_layer layers[2]; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 274 | u8 dramcr; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 275 | u32 eapr; |
| 276 | u32 scrub_disabled; |
| 277 | u32 sdram_refresh_rate; |
Dave Peterson | 749ede5 | 2006-03-26 01:38:45 -0800 | [diff] [blame] | 278 | struct r82600_error_info discard; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 279 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 280 | edac_dbg(0, "\n"); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 281 | pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); |
| 282 | pci_read_config_dword(pdev, R82600_EAP, &eapr); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 283 | scrub_disabled = eapr & BIT(31); |
| 284 | sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 285 | edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate); |
| 286 | edac_dbg(2, "DRAMC register = %#0x\n", dramcr); |
Mauro Carvalho Chehab | 63b5d1d | 2012-04-16 15:12:13 -0300 | [diff] [blame] | 287 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
| 288 | layers[0].size = R82600_NR_CSROWS; |
| 289 | layers[0].is_virt_csrow = true; |
| 290 | layers[1].type = EDAC_MC_LAYER_CHANNEL; |
| 291 | layers[1].size = R82600_NR_CHANS; |
| 292 | layers[1].is_virt_csrow = false; |
Mauro Carvalho Chehab | ca0907b | 2012-05-02 14:37:00 -0300 | [diff] [blame] | 293 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 294 | if (mci == NULL) |
| 295 | return -ENOMEM; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 296 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 297 | edac_dbg(0, "mci = %p\n", mci); |
Mauro Carvalho Chehab | fd68750 | 2012-03-16 07:44:18 -0300 | [diff] [blame] | 298 | mci->pdev = &pdev->dev; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 299 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 300 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
Dave Peterson | e7ecd89 | 2006-03-26 01:38:52 -0800 | [diff] [blame] | 301 | /* FIXME try to work out if the chip leads have been used for COM2 |
| 302 | * instead on this board? [MA6?] MAYBE: |
| 303 | */ |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 304 | |
| 305 | /* On the R82600, the pins for memory bits 72:65 - i.e. the * |
| 306 | * EC bits are shared with the pins for COM2 (!), so if COM2 * |
| 307 | * is enabled, we assume COM2 is wired up, and thus no EDAC * |
| 308 | * is possible. */ |
| 309 | mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
Dave Peterson | e7ecd89 | 2006-03-26 01:38:52 -0800 | [diff] [blame] | 310 | |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 311 | if (ecc_enabled(dramcr)) { |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 312 | if (scrub_disabled) |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 313 | edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n", |
| 314 | mci, eapr); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 315 | } else |
| 316 | mci->edac_cap = EDAC_FLAG_NONE; |
| 317 | |
Dave Peterson | 680cbbb | 2006-03-26 01:38:41 -0800 | [diff] [blame] | 318 | mci->mod_name = EDAC_MOD_STR; |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 319 | mci->mod_ver = R82600_REVISION; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 320 | mci->ctl_name = "R82600"; |
Dave Jiang | c419270 | 2007-07-19 01:49:47 -0700 | [diff] [blame] | 321 | mci->dev_name = pci_name(pdev); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 322 | mci->edac_check = r82600_check; |
| 323 | mci->ctl_page_to_phys = NULL; |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 324 | r82600_init_csrows(mci, pdev, dramcr); |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 325 | r82600_get_error_info(mci, &discard); /* clear counters */ |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 326 | |
Doug Thompson | 2d7bbb9 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 327 | /* Here we assume that we will never see multiple instances of this |
| 328 | * type of memory controller. The ID is therefore hardcoded to 0. |
| 329 | */ |
Doug Thompson | b8f6f97 | 2007-07-19 01:50:26 -0700 | [diff] [blame] | 330 | if (edac_mc_add_mc(mci)) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 331 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 332 | goto fail; |
| 333 | } |
| 334 | |
| 335 | /* get this far and it's successful */ |
| 336 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 337 | if (disable_hardware_scrub) { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 338 | edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n"); |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 339 | pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 340 | } |
| 341 | |
Dave Jiang | 456a2f9 | 2007-07-19 01:50:10 -0700 | [diff] [blame] | 342 | /* allocating generic PCI control info */ |
| 343 | r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); |
| 344 | if (!r82600_pci) { |
| 345 | printk(KERN_WARNING |
| 346 | "%s(): Unable to create PCI control\n", |
| 347 | __func__); |
| 348 | printk(KERN_WARNING |
| 349 | "%s(): PCI error report via EDAC not setup\n", |
| 350 | __func__); |
| 351 | } |
| 352 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 353 | edac_dbg(3, "success\n"); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 354 | return 0; |
| 355 | |
Douglas Thompson | 052dfb4 | 2007-07-19 01:50:13 -0700 | [diff] [blame] | 356 | fail: |
Doug Thompson | 1318952 | 2006-06-30 01:56:08 -0700 | [diff] [blame] | 357 | edac_mc_free(mci); |
| 358 | return -ENODEV; |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | /* returns count (>= 0), or negative on error */ |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 362 | static int r82600_init_one(struct pci_dev *pdev, |
| 363 | const struct pci_device_id *ent) |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 364 | { |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 365 | edac_dbg(0, "\n"); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 366 | |
Roman Fietze | ee6583f | 2010-05-18 14:45:47 +0200 | [diff] [blame] | 367 | /* don't need to call pci_enable_device() */ |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 368 | return r82600_probe1(pdev, ent->driver_data); |
| 369 | } |
| 370 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 371 | static void r82600_remove_one(struct pci_dev *pdev) |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 372 | { |
| 373 | struct mem_ctl_info *mci; |
| 374 | |
Joe Perches | 956b9ba | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 375 | edac_dbg(0, "\n"); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 376 | |
Dave Jiang | 456a2f9 | 2007-07-19 01:50:10 -0700 | [diff] [blame] | 377 | if (r82600_pci) |
| 378 | edac_pci_release_generic_ctl(r82600_pci); |
| 379 | |
Doug Thompson | 37f0458 | 2006-06-30 01:56:07 -0700 | [diff] [blame] | 380 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
Dave Peterson | 18dbc33 | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 381 | return; |
| 382 | |
| 383 | edac_mc_free(mci); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 384 | } |
| 385 | |
Jingoo Han | ba935f4 | 2013-12-06 10:23:08 +0100 | [diff] [blame] | 386 | static const struct pci_device_id r82600_pci_tbl[] = { |
Dave Peterson | e7ecd89 | 2006-03-26 01:38:52 -0800 | [diff] [blame] | 387 | { |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 388 | PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) |
| 389 | }, |
Dave Peterson | e7ecd89 | 2006-03-26 01:38:52 -0800 | [diff] [blame] | 390 | { |
Douglas Thompson | cddbfca | 2007-07-19 01:50:08 -0700 | [diff] [blame] | 391 | 0, |
| 392 | } /* 0 terminated list. */ |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 393 | }; |
| 394 | |
| 395 | MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); |
| 396 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 397 | static struct pci_driver r82600_driver = { |
Dave Peterson | 680cbbb | 2006-03-26 01:38:41 -0800 | [diff] [blame] | 398 | .name = EDAC_MOD_STR, |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 399 | .probe = r82600_init_one, |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 400 | .remove = r82600_remove_one, |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 401 | .id_table = r82600_pci_tbl, |
| 402 | }; |
| 403 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 404 | static int __init r82600_init(void) |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 405 | { |
Hitoshi Mitake | c3c52bc | 2008-04-29 01:03:18 -0700 | [diff] [blame] | 406 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 407 | opstate_init(); |
| 408 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 409 | return pci_register_driver(&r82600_driver); |
| 410 | } |
| 411 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 412 | static void __exit r82600_exit(void) |
| 413 | { |
| 414 | pci_unregister_driver(&r82600_driver); |
| 415 | } |
| 416 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 417 | module_init(r82600_init); |
| 418 | module_exit(r82600_exit); |
| 419 | |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 420 | MODULE_LICENSE("GPL"); |
| 421 | MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. " |
Douglas Thompson | 052dfb4 | 2007-07-19 01:50:13 -0700 | [diff] [blame] | 422 | "on behalf of EADS Astrium"); |
Alan Cox | 2f768af | 2006-01-18 17:44:12 -0800 | [diff] [blame] | 423 | MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); |
| 424 | |
| 425 | module_param(disable_hardware_scrub, bool, 0644); |
| 426 | MODULE_PARM_DESC(disable_hardware_scrub, |
| 427 | "If set, disable the chipset's automatic scrub for CEs"); |
Hitoshi Mitake | c3c52bc | 2008-04-29 01:03:18 -0700 | [diff] [blame] | 428 | |
| 429 | module_param(edac_op_state, int, 0444); |
| 430 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |