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Sonic Zhange9a03ad2013-09-03 16:28:59 +08001/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <linux/bitops.h>
10#include <linux/delay.h>
11#include <linux/module.h>
12#include <linux/err.h>
13#include <linux/debugfs.h>
14#include <linux/seq_file.h>
15#include <linux/irq.h>
16#include <linux/platform_data/pinctrl-adi2.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pinctrl/machine.h>
23#include <linux/syscore_ops.h>
24#include <linux/gpio.h>
25#include <asm/portmux.h>
26#include "pinctrl-adi2.h"
27#include "core.h"
28
29/*
30According to the BF54x HRM, pint means "pin interrupt".
31http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
32
33ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
34nels dedicated to pin interrupt purposes. These channels are managed by
35four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
37pins of port A and port B, PINT2 and PINT3 manage all the pins from port
38C to port J as shown in Figure 9-2.
39
40n BF54x HRM:
41The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
42upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
43plexers shown in Figure 9-3. Lower half units of eight pins can be
44forwarded to either byte 0 or byte 2 of either associated PINTx block.
45Upper half units can be forwarded to either byte 1 or byte 3 of the pin
46interrupt blocks, without further restrictions.
47
48All MMR registers in the pin interrupt module are 32 bits wide. To simply the
49mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
5016 bits of a PINTx block. You can find the Figure 9-3 on page 583.
51
52Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
53to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
54interrupt handler.
55
56The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
57domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
58to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
59the current domain pointer according to whether the interrupt request mask
60is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
61
62A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63port devices can be mapped to the same PINT device.
64
65*/
66
67static LIST_HEAD(adi_pint_list);
68static LIST_HEAD(adi_gpio_port_list);
69
70#define DRIVER_NAME "pinctrl-adi2"
71
72#define PINT_HI_OFFSET 16
73
74/**
75 * struct gpio_port_saved - GPIO port registers that should be saved between
76 * power suspend and resume operations.
77 *
78 * @fer: PORTx_FER register
79 * @data: PORTx_DATA register
80 * @dir: PORTx_DIR register
81 * @inen: PORTx_INEN register
82 * @mux: PORTx_MUX register
83 */
84struct gpio_port_saved {
85 u16 fer;
86 u16 data;
87 u16 dir;
88 u16 inen;
89 u32 mux;
90};
91
Sonic Zhang1e6f8e32014-01-27 18:23:54 +080092/*
93 * struct gpio_pint_saved - PINT registers saved in PM operations
94 *
95 * @assign: ASSIGN register
96 * @edge_set: EDGE_SET register
97 * @invert_set: INVERT_SET register
98 */
99struct gpio_pint_saved {
100 u32 assign;
101 u32 edge_set;
102 u32 invert_set;
103};
104
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800105/**
106 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
107 * banks can be mapped into one Pin interrupt controller.
108 *
109 * @node: All gpio_pint instances are added to a global list.
110 * @base: PINT device register base address
111 * @irq: IRQ of the PINT device, it is the parent IRQ of all
112 * GPIO IRQs mapping to this device.
113 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
114 * mapping to the low 16-bit of the pint registers.
115 * [1] irq domain of the gpio port, whose hardware interrupts are
116 * mapping to the high 16-bit of the pint registers.
117 * @regs: address pointer to the PINT device
118 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
119 * @lock: This lock make sure the irq_chip operations to one PINT device
120 * for different GPIO interrrupts are atomic.
121 * @pint_map_port: Set up the mapping between one PINT device and
122 * multiple GPIO banks.
123 */
124struct gpio_pint {
125 struct list_head node;
126 void __iomem *base;
127 int irq;
128 struct irq_domain *domain[2];
129 struct gpio_pint_regs *regs;
Sonic Zhang1e6f8e32014-01-27 18:23:54 +0800130 struct gpio_pint_saved saved_data;
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800131 int map_count;
132 spinlock_t lock;
133
134 int (*pint_map_port)(struct gpio_pint *pint, bool assign,
135 u8 map, struct irq_domain *domain);
136};
137
138/**
139 * ADI pin controller
140 *
141 * @dev: a pointer back to containing device
142 * @pctl: the pinctrl device
143 * @soc: SoC data for this specific chip
144 */
145struct adi_pinctrl {
146 struct device *dev;
147 struct pinctrl_dev *pctl;
148 const struct adi_pinctrl_soc_data *soc;
149};
150
151/**
152 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
153 * into one pin interrupt controller.
154 *
155 * @node: All gpio_port instances are added to a list.
156 * @base: GPIO bank device register base address
157 * @irq_base: base IRQ of the GPIO bank device
158 * @width: PIN number of the GPIO bank device
159 * @regs: address pointer to the GPIO bank device
160 * @saved_data: registers that should be saved between PM operations.
161 * @dev: device structure of this GPIO bank
162 * @pint: GPIO PINT device that this GPIO bank mapped to
163 * @pint_map: GIOP bank mapping code in PINT device
164 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
165 * GPIO bank can be mapped into either low 16 bits[0] or high 16
166 * bits[1] of each PINT register.
167 * @lock: This lock make sure the irq_chip operations to one PINT device
168 * for different GPIO interrrupts are atomic.
169 * @chip: abstract a GPIO controller
170 * @domain: The irq domain owned by the GPIO port.
171 * @rsvmap: Reservation map array for each pin in the GPIO bank
172 */
173struct gpio_port {
174 struct list_head node;
175 void __iomem *base;
Sonic Zhangb4eef7b2014-01-27 18:23:55 +0800176 int irq_base;
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800177 unsigned int width;
178 struct gpio_port_t *regs;
179 struct gpio_port_saved saved_data;
180 struct device *dev;
181
182 struct gpio_pint *pint;
183 u8 pint_map;
184 bool pint_assign;
185
186 spinlock_t lock;
187 struct gpio_chip chip;
188 struct irq_domain *domain;
189};
190
191static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
192{
193 return pin - range->pin_base;
194}
195
196static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
197{
198 return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
199}
200
201static struct gpio_pint *find_gpio_pint(unsigned id)
202{
203 struct gpio_pint *pint;
204 int i = 0;
205
206 list_for_each_entry(pint, &adi_pint_list, node) {
207 if (id == i)
208 return pint;
209 i++;
210 }
211
212 return NULL;
213}
214
215static inline void port_setup(struct gpio_port *port, unsigned offset,
216 bool use_for_gpio)
217{
218 struct gpio_port_t *regs = port->regs;
219
220 if (use_for_gpio)
221 writew(readw(&regs->port_fer) & ~BIT(offset),
222 &regs->port_fer);
223 else
224 writew(readw(&regs->port_fer) | BIT(offset), &regs->port_fer);
225}
226
227static inline void portmux_setup(struct gpio_port *port, unsigned offset,
228 unsigned short function)
229{
230 struct gpio_port_t *regs = port->regs;
231 u32 pmux;
232
233 pmux = readl(&regs->port_mux);
234
235 /* The function field of each pin has 2 consecutive bits in
236 * the mux register.
237 */
238 pmux &= ~(0x3 << (2 * offset));
239 pmux |= (function & 0x3) << (2 * offset);
240
241 writel(pmux, &regs->port_mux);
242}
243
244static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
245{
246 struct gpio_port_t *regs = port->regs;
247 u32 pmux = readl(&regs->port_mux);
248
249 /* The function field of each pin has 2 consecutive bits in
250 * the mux register.
251 */
252 return pmux >> (2 * offset) & 0x3;
253}
254
255static void adi_gpio_ack_irq(struct irq_data *d)
256{
257 unsigned long flags;
258 struct gpio_port *port = irq_data_get_irq_chip_data(d);
259 struct gpio_pint_regs *regs = port->pint->regs;
260 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
261
262 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800263 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800264
265 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
266 if (readl(&regs->invert_set) & pintbit)
267 writel(pintbit, &regs->invert_clear);
268 else
269 writel(pintbit, &regs->invert_set);
270 }
271
272 writel(pintbit, &regs->request);
273
Sonic Zhang010c51e2013-10-08 15:30:21 +0800274 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800275 spin_unlock_irqrestore(&port->lock, flags);
276}
277
278static void adi_gpio_mask_ack_irq(struct irq_data *d)
279{
280 unsigned long flags;
281 struct gpio_port *port = irq_data_get_irq_chip_data(d);
282 struct gpio_pint_regs *regs = port->pint->regs;
283 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
284
285 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800286 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800287
288 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
289 if (readl(&regs->invert_set) & pintbit)
290 writel(pintbit, &regs->invert_clear);
291 else
292 writel(pintbit, &regs->invert_set);
293 }
294
295 writel(pintbit, &regs->request);
296 writel(pintbit, &regs->mask_clear);
297
Sonic Zhang010c51e2013-10-08 15:30:21 +0800298 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800299 spin_unlock_irqrestore(&port->lock, flags);
300}
301
302static void adi_gpio_mask_irq(struct irq_data *d)
303{
304 unsigned long flags;
305 struct gpio_port *port = irq_data_get_irq_chip_data(d);
306 struct gpio_pint_regs *regs = port->pint->regs;
307
308 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800309 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800310
311 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_clear);
312
Sonic Zhang010c51e2013-10-08 15:30:21 +0800313 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800314 spin_unlock_irqrestore(&port->lock, flags);
315}
316
317static void adi_gpio_unmask_irq(struct irq_data *d)
318{
319 unsigned long flags;
320 struct gpio_port *port = irq_data_get_irq_chip_data(d);
321 struct gpio_pint_regs *regs = port->pint->regs;
322
323 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800324 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800325
326 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_set);
327
Sonic Zhang010c51e2013-10-08 15:30:21 +0800328 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800329 spin_unlock_irqrestore(&port->lock, flags);
330}
331
332static unsigned int adi_gpio_irq_startup(struct irq_data *d)
333{
334 unsigned long flags;
335 struct gpio_port *port = irq_data_get_irq_chip_data(d);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800336 struct gpio_pint_regs *regs;
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800337
338 if (!port) {
Sonic Zhang010c51e2013-10-08 15:30:21 +0800339 pr_err("GPIO IRQ %d :Not exist\n", d->irq);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800340 return -ENODEV;
341 }
342
Sonic Zhang010c51e2013-10-08 15:30:21 +0800343 regs = port->pint->regs;
344
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800345 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800346 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800347
348 port_setup(port, d->hwirq, true);
349 writew(BIT(d->hwirq), &port->regs->dir_clear);
350 writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
351
352 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_set);
353
Sonic Zhang010c51e2013-10-08 15:30:21 +0800354 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800355 spin_unlock_irqrestore(&port->lock, flags);
356
357 return 0;
358}
359
360static void adi_gpio_irq_shutdown(struct irq_data *d)
361{
362 unsigned long flags;
363 struct gpio_port *port = irq_data_get_irq_chip_data(d);
364 struct gpio_pint_regs *regs = port->pint->regs;
365
366 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800367 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800368
369 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_clear);
370
Sonic Zhang010c51e2013-10-08 15:30:21 +0800371 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800372 spin_unlock_irqrestore(&port->lock, flags);
373}
374
375static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
376{
377 unsigned long flags;
378 struct gpio_port *port = irq_data_get_irq_chip_data(d);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800379 struct gpio_pint_regs *pint_regs;
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800380 unsigned pintmask;
381 unsigned int irq = d->irq;
382 int ret = 0;
383 char buf[16];
384
385 if (!port) {
Sonic Zhang010c51e2013-10-08 15:30:21 +0800386 pr_err("GPIO IRQ %d :Not exist\n", d->irq);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800387 return -ENODEV;
388 }
389
Sonic Zhang010c51e2013-10-08 15:30:21 +0800390 pint_regs = port->pint->regs;
391
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800392 pintmask = hwirq_to_pintbit(port, d->hwirq);
393
394 spin_lock_irqsave(&port->lock, flags);
Sonic Zhang010c51e2013-10-08 15:30:21 +0800395 spin_lock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800396
397 /* In case of interrupt autodetect, set irq type to edge sensitive. */
398 if (type == IRQ_TYPE_PROBE)
399 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
400
401 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
402 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
403 snprintf(buf, 16, "gpio-irq%d", irq);
404 port_setup(port, d->hwirq, true);
405 } else
406 goto out;
407
408 /* The GPIO interrupt is triggered only when its input value
409 * transfer from 0 to 1. So, invert the input value if the
410 * irq type is low or falling
411 */
412 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
413 writel(pintmask, &pint_regs->invert_set);
414 else
415 writel(pintmask, &pint_regs->invert_clear);
416
417 /* In edge sensitive case, if the input value of the requested irq
418 * is already 1, invert it.
419 */
420 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
421 if (gpio_get_value(port->chip.base + d->hwirq))
422 writel(pintmask, &pint_regs->invert_set);
423 else
424 writel(pintmask, &pint_regs->invert_clear);
425 }
426
427 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
428 writel(pintmask, &pint_regs->edge_set);
429 __irq_set_handler_locked(irq, handle_edge_irq);
430 } else {
431 writel(pintmask, &pint_regs->edge_clear);
432 __irq_set_handler_locked(irq, handle_level_irq);
433 }
434
435out:
Sonic Zhang010c51e2013-10-08 15:30:21 +0800436 spin_unlock(&port->pint->lock);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800437 spin_unlock_irqrestore(&port->lock, flags);
438
439 return ret;
440}
441
442#ifdef CONFIG_PM
443static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
444{
445 struct gpio_port *port = irq_data_get_irq_chip_data(d);
446
447 if (!port || !port->pint || port->pint->irq != d->irq)
448 return -EINVAL;
449
450#ifndef SEC_GCTL
451 adi_internal_set_wake(port->pint->irq, state);
452#endif
453
454 return 0;
455}
456
457static int adi_pint_suspend(void)
458{
459 struct gpio_pint *pint;
460
461 list_for_each_entry(pint, &adi_pint_list, node) {
462 writel(0xffffffff, &pint->regs->mask_clear);
463 pint->saved_data.assign = readl(&pint->regs->assign);
464 pint->saved_data.edge_set = readl(&pint->regs->edge_set);
465 pint->saved_data.invert_set = readl(&pint->regs->invert_set);
466 }
467
468 return 0;
469}
470
471static void adi_pint_resume(void)
472{
473 struct gpio_pint *pint;
474
475 list_for_each_entry(pint, &adi_pint_list, node) {
476 writel(pint->saved_data.assign, &pint->regs->assign);
477 writel(pint->saved_data.edge_set, &pint->regs->edge_set);
478 writel(pint->saved_data.invert_set, &pint->regs->invert_set);
479 }
480}
481
482static int adi_gpio_suspend(void)
483{
484 struct gpio_port *port;
485
486 list_for_each_entry(port, &adi_gpio_port_list, node) {
487 port->saved_data.fer = readw(&port->regs->port_fer);
488 port->saved_data.mux = readl(&port->regs->port_mux);
489 port->saved_data.data = readw(&port->regs->data);
490 port->saved_data.inen = readw(&port->regs->inen);
491 port->saved_data.dir = readw(&port->regs->dir_set);
492 }
493
494 return adi_pint_suspend();
495}
496
497static void adi_gpio_resume(void)
498{
499 struct gpio_port *port;
500
501 adi_pint_resume();
502
503 list_for_each_entry(port, &adi_gpio_port_list, node) {
504 writel(port->saved_data.mux, &port->regs->port_mux);
505 writew(port->saved_data.fer, &port->regs->port_fer);
506 writew(port->saved_data.inen, &port->regs->inen);
507 writew(port->saved_data.data & port->saved_data.dir,
508 &port->regs->data_set);
509 writew(port->saved_data.dir, &port->regs->dir_set);
510 }
511
512}
513
514static struct syscore_ops gpio_pm_syscore_ops = {
515 .suspend = adi_gpio_suspend,
516 .resume = adi_gpio_resume,
517};
518#else /* CONFIG_PM */
519#define adi_gpio_set_wake NULL
520#endif /* CONFIG_PM */
521
522#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
523static inline void preflow_handler(struct irq_desc *desc)
524{
525 if (desc->preflow_handler)
526 desc->preflow_handler(&desc->irq_data);
527}
528#else
529static inline void preflow_handler(struct irq_desc *desc) { }
530#endif
531
532static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
533 struct irq_desc *desc)
534{
535 u32 request;
536 u32 level_mask, hwirq;
537 bool umask = false;
538 struct gpio_pint *pint = irq_desc_get_handler_data(desc);
539 struct irq_chip *chip = irq_desc_get_chip(desc);
540 struct gpio_pint_regs *regs = pint->regs;
541 struct irq_domain *domain;
542
543 preflow_handler(desc);
544 chained_irq_enter(chip, desc);
545
546 request = readl(&regs->request);
547 level_mask = readl(&regs->edge_set) & request;
548
549 hwirq = 0;
550 domain = pint->domain[0];
551 while (request) {
552 /* domain pointer need to be changed only once at IRQ 16 when
553 * we go through IRQ requests from bit 0 to bit 31.
554 */
555 if (hwirq == PINT_HI_OFFSET)
556 domain = pint->domain[1];
557
558 if (request & 1) {
559 if (level_mask & BIT(hwirq)) {
560 umask = true;
561 chained_irq_exit(chip, desc);
562 }
563 generic_handle_irq(irq_find_mapping(domain,
564 hwirq % PINT_HI_OFFSET));
565 }
566
567 hwirq++;
568 request >>= 1;
569 }
570
571 if (!umask)
572 chained_irq_exit(chip, desc);
573}
574
575static struct irq_chip adi_gpio_irqchip = {
576 .name = "GPIO",
577 .irq_ack = adi_gpio_ack_irq,
578 .irq_mask = adi_gpio_mask_irq,
579 .irq_mask_ack = adi_gpio_mask_ack_irq,
580 .irq_unmask = adi_gpio_unmask_irq,
581 .irq_disable = adi_gpio_mask_irq,
582 .irq_enable = adi_gpio_unmask_irq,
583 .irq_set_type = adi_gpio_irq_type,
584 .irq_startup = adi_gpio_irq_startup,
585 .irq_shutdown = adi_gpio_irq_shutdown,
586 .irq_set_wake = adi_gpio_set_wake,
587};
588
589static int adi_get_groups_count(struct pinctrl_dev *pctldev)
590{
591 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
592
593 return pinctrl->soc->ngroups;
594}
595
596static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
597 unsigned selector)
598{
599 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
600
601 return pinctrl->soc->groups[selector].name;
602}
603
604static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
605 const unsigned **pins,
606 unsigned *num_pins)
607{
608 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
609
610 *pins = pinctrl->soc->groups[selector].pins;
611 *num_pins = pinctrl->soc->groups[selector].num;
612 return 0;
613}
614
615static struct pinctrl_ops adi_pctrl_ops = {
616 .get_groups_count = adi_get_groups_count,
617 .get_group_name = adi_get_group_name,
618 .get_group_pins = adi_get_group_pins,
619};
620
621static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
622 unsigned group)
623{
624 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
625 struct gpio_port *port;
626 struct pinctrl_gpio_range *range;
627 unsigned long flags;
628 unsigned short *mux, pin;
629
630 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
631
632 while (*mux) {
633 pin = P_IDENT(*mux);
634
635 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
636 if (range == NULL) /* should not happen */
637 return -ENODEV;
638
639 port = container_of(range->gc, struct gpio_port, chip);
640
641 spin_lock_irqsave(&port->lock, flags);
642
643 portmux_setup(port, pin_to_offset(range, pin),
644 P_FUNCT2MUX(*mux));
645 port_setup(port, pin_to_offset(range, pin), false);
646 mux++;
647
648 spin_unlock_irqrestore(&port->lock, flags);
649 }
650
651 return 0;
652}
653
654static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
655 unsigned group)
656{
657 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
658 struct gpio_port *port;
659 struct pinctrl_gpio_range *range;
660 unsigned long flags;
661 unsigned short *mux, pin;
662
663 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
664
665 while (*mux) {
666 pin = P_IDENT(*mux);
667
668 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
669 if (range == NULL) /* should not happen */
670 return;
671
672 port = container_of(range->gc, struct gpio_port, chip);
673
674 spin_lock_irqsave(&port->lock, flags);
675
676 port_setup(port, pin_to_offset(range, pin), true);
677 mux++;
678
679 spin_unlock_irqrestore(&port->lock, flags);
680 }
681}
682
683static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
684{
685 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
686
687 return pinctrl->soc->nfunctions;
688}
689
690static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
691 unsigned selector)
692{
693 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
694
695 return pinctrl->soc->functions[selector].name;
696}
697
698static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
699 const char * const **groups,
700 unsigned * const num_groups)
701{
702 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
703
704 *groups = pinctrl->soc->functions[selector].groups;
705 *num_groups = pinctrl->soc->functions[selector].num_groups;
706 return 0;
707}
708
709static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
710 struct pinctrl_gpio_range *range, unsigned pin)
711{
712 struct gpio_port *port;
713 unsigned long flags;
714 u8 offset;
715
716 port = container_of(range->gc, struct gpio_port, chip);
717 offset = pin_to_offset(range, pin);
718
719 spin_lock_irqsave(&port->lock, flags);
720
721 port_setup(port, offset, true);
722
723 spin_unlock_irqrestore(&port->lock, flags);
724
725 return 0;
726}
727
728static struct pinmux_ops adi_pinmux_ops = {
729 .enable = adi_pinmux_enable,
730 .disable = adi_pinmux_disable,
731 .get_functions_count = adi_pinmux_get_funcs_count,
732 .get_function_name = adi_pinmux_get_func_name,
733 .get_function_groups = adi_pinmux_get_groups,
734 .gpio_request_enable = adi_pinmux_request_gpio,
735};
736
737
738static struct pinctrl_desc adi_pinmux_desc = {
739 .name = DRIVER_NAME,
740 .pctlops = &adi_pctrl_ops,
741 .pmxops = &adi_pinmux_ops,
742 .owner = THIS_MODULE,
743};
744
745static int adi_gpio_request(struct gpio_chip *chip, unsigned offset)
746{
747 return pinctrl_request_gpio(chip->base + offset);
748}
749
750static void adi_gpio_free(struct gpio_chip *chip, unsigned offset)
751{
752 pinctrl_free_gpio(chip->base + offset);
753}
754
755static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
756{
757 struct gpio_port *port;
758 unsigned long flags;
759
760 port = container_of(chip, struct gpio_port, chip);
761
762 spin_lock_irqsave(&port->lock, flags);
763
764 writew(BIT(offset), &port->regs->dir_clear);
765 writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
766
767 spin_unlock_irqrestore(&port->lock, flags);
768
769 return 0;
770}
771
772static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
773 int value)
774{
775 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
776 struct gpio_port_t *regs = port->regs;
777 unsigned long flags;
778
779 spin_lock_irqsave(&port->lock, flags);
780
781 if (value)
Sonic Zhangd3224ed2013-10-08 15:31:21 +0800782 writew(BIT(offset), &regs->data_set);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800783 else
Sonic Zhangd3224ed2013-10-08 15:31:21 +0800784 writew(BIT(offset), &regs->data_clear);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800785
786 spin_unlock_irqrestore(&port->lock, flags);
787}
788
789static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
790 int value)
791{
792 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
793 struct gpio_port_t *regs = port->regs;
794 unsigned long flags;
795
796 spin_lock_irqsave(&port->lock, flags);
797
Sonic Zhangd3224ed2013-10-08 15:31:21 +0800798 writew(readw(&regs->inen) & ~BIT(offset), &regs->inen);
799 if (value)
800 writew(BIT(offset), &regs->data_set);
801 else
802 writew(BIT(offset), &regs->data_clear);
803 writew(BIT(offset), &regs->dir_set);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800804
805 spin_unlock_irqrestore(&port->lock, flags);
806
807 return 0;
808}
809
810static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
811{
812 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
813 struct gpio_port_t *regs = port->regs;
814 unsigned long flags;
815 int ret;
816
817 spin_lock_irqsave(&port->lock, flags);
818
819 ret = !!(readw(&regs->data) & BIT(offset));
820
821 spin_unlock_irqrestore(&port->lock, flags);
822
823 return ret;
824}
825
826static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
827{
828 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
829
830 if (port->irq_base >= 0)
831 return irq_find_mapping(port->domain, offset);
832 else
833 return irq_create_mapping(port->domain, offset);
834}
835
836static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
837 struct irq_domain *domain)
838{
839 struct gpio_pint_regs *regs = pint->regs;
840 u32 map_mask;
841
842 if (pint->map_count > 1)
843 return -EINVAL;
844
845 pint->map_count++;
846
847 /* The map_mask of each gpio port is a 16-bit duplicate
848 * of the 8-bit map. It can be set to either high 16 bits or low
849 * 16 bits of the pint assignment register.
850 */
851 map_mask = (map << 8) | map;
852 if (assign) {
853 map_mask <<= PINT_HI_OFFSET;
854 writel((readl(&regs->assign) & 0xFFFF) | map_mask,
855 &regs->assign);
856 } else
857 writel((readl(&regs->assign) & 0xFFFF0000) | map_mask,
858 &regs->assign);
859
860 pint->domain[assign] = domain;
861
862 return 0;
863}
864
865static int adi_gpio_pint_probe(struct platform_device *pdev)
866{
867 struct device *dev = &pdev->dev;
868 struct resource *res;
869 struct gpio_pint *pint;
870
871 pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL);
872 if (!pint) {
873 dev_err(dev, "Memory alloc failed\n");
874 return -ENOMEM;
875 }
876
877 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Axel Linc8690d62013-09-24 15:46:11 +0800878 pint->base = devm_ioremap_resource(dev, res);
879 if (IS_ERR(pint->base))
880 return PTR_ERR(pint->base);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800881
882 pint->regs = (struct gpio_pint_regs *)pint->base;
883
884 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
885 if (!res) {
886 dev_err(dev, "Invalid IRQ resource\n");
887 return -ENODEV;
888 }
889
890 spin_lock_init(&pint->lock);
891
892 pint->irq = res->start;
893 pint->pint_map_port = adi_pint_map_port;
894 platform_set_drvdata(pdev, pint);
895
896 irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq);
897 irq_set_handler_data(pint->irq, pint);
898
899 list_add_tail(&pint->node, &adi_pint_list);
900
901 return 0;
902}
903
904static int adi_gpio_pint_remove(struct platform_device *pdev)
905{
906 struct gpio_pint *pint = platform_get_drvdata(pdev);
907
908 list_del(&pint->node);
909 irq_set_handler(pint->irq, handle_simple_irq);
910
911 return 0;
912}
913
914static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
915 irq_hw_number_t hwirq)
916{
917 struct gpio_port *port = d->host_data;
918
919 if (!port)
920 return -EINVAL;
921
922 irq_set_chip_data(irq, port);
923 irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
924 handle_level_irq);
925
926 return 0;
927}
928
929const struct irq_domain_ops adi_gpio_irq_domain_ops = {
930 .map = adi_gpio_irq_map,
931 .xlate = irq_domain_xlate_onecell,
932};
933
934static int adi_gpio_init_int(struct gpio_port *port)
935{
936 struct device_node *node = port->dev->of_node;
937 struct gpio_pint *pint = port->pint;
938 int ret;
939
940 port->domain = irq_domain_add_linear(node, port->width,
941 &adi_gpio_irq_domain_ops, port);
942 if (!port->domain) {
943 dev_err(port->dev, "Failed to create irqdomain\n");
944 return -ENOSYS;
945 }
946
947 /* According to BF54x and BF60x HRM, pin interrupt devices are not
948 * part of the GPIO port device. in GPIO interrupt mode, the GPIO
949 * pins of multiple port devices can be routed into one pin interrupt
950 * device. The mapping can be configured by setting pint assignment
951 * register with the mapping value of different GPIO port. This is
952 * done via function pint_map_port().
953 */
954 ret = pint->pint_map_port(port->pint, port->pint_assign,
955 port->pint_map, port->domain);
956 if (ret)
957 return ret;
958
959 if (port->irq_base >= 0) {
960 ret = irq_create_strict_mappings(port->domain, port->irq_base,
961 0, port->width);
962 if (ret) {
963 dev_err(port->dev, "Couldn't associate to domain\n");
964 return ret;
965 }
966 }
967
968 return 0;
969}
970
971#define DEVNAME_SIZE 16
972
973static int adi_gpio_probe(struct platform_device *pdev)
974{
975 struct device *dev = &pdev->dev;
976 const struct adi_pinctrl_gpio_platform_data *pdata;
977 struct resource *res;
978 struct gpio_port *port;
979 char pinctrl_devname[DEVNAME_SIZE];
980 static int gpio;
981 int ret = 0, ret1;
982
983 pdata = dev->platform_data;
984 if (!pdata)
985 return -EINVAL;
986
987 port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL);
988 if (!port) {
989 dev_err(dev, "Memory alloc failed\n");
990 return -ENOMEM;
991 }
992
993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Axel Linc8690d62013-09-24 15:46:11 +0800994 port->base = devm_ioremap_resource(dev, res);
995 if (IS_ERR(port->base))
996 return PTR_ERR(port->base);
Sonic Zhange9a03ad2013-09-03 16:28:59 +0800997
998 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
999 if (!res)
1000 port->irq_base = -1;
1001 else
1002 port->irq_base = res->start;
1003
1004 port->width = pdata->port_width;
1005 port->dev = dev;
1006 port->regs = (struct gpio_port_t *)port->base;
1007 port->pint_assign = pdata->pint_assign;
1008 port->pint_map = pdata->pint_map;
1009
1010 port->pint = find_gpio_pint(pdata->pint_id);
1011 if (port->pint) {
1012 ret = adi_gpio_init_int(port);
1013 if (ret)
1014 return ret;
1015 }
1016
1017 spin_lock_init(&port->lock);
1018
1019 platform_set_drvdata(pdev, port);
1020
1021 port->chip.label = "adi-gpio";
1022 port->chip.direction_input = adi_gpio_direction_input;
1023 port->chip.get = adi_gpio_get_value;
1024 port->chip.direction_output = adi_gpio_direction_output;
1025 port->chip.set = adi_gpio_set_value;
1026 port->chip.request = adi_gpio_request;
1027 port->chip.free = adi_gpio_free;
1028 port->chip.to_irq = adi_gpio_to_irq;
1029 if (pdata->port_gpio_base > 0)
1030 port->chip.base = pdata->port_gpio_base;
1031 else
1032 port->chip.base = gpio;
1033 port->chip.ngpio = port->width;
1034 gpio = port->chip.base + port->width;
1035
1036 ret = gpiochip_add(&port->chip);
1037 if (ret) {
1038 dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
1039 goto out_remove_domain;
1040 }
1041
1042 /* Add gpio pin range */
1043 snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
1044 pdata->pinctrl_id);
1045 pinctrl_devname[DEVNAME_SIZE - 1] = 0;
1046 ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
1047 0, pdata->port_pin_base, port->width);
1048 if (ret) {
1049 dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
1050 pinctrl_devname);
1051 goto out_remove_gpiochip;
1052 }
1053
1054 list_add_tail(&port->node, &adi_gpio_port_list);
1055
1056 return 0;
1057
1058out_remove_gpiochip:
1059 ret1 = gpiochip_remove(&port->chip);
1060out_remove_domain:
1061 if (port->pint)
1062 irq_domain_remove(port->domain);
1063
1064 return ret;
1065}
1066
1067static int adi_gpio_remove(struct platform_device *pdev)
1068{
1069 struct gpio_port *port = platform_get_drvdata(pdev);
1070 int ret;
1071 u8 offset;
1072
1073 list_del(&port->node);
1074 gpiochip_remove_pin_ranges(&port->chip);
1075 ret = gpiochip_remove(&port->chip);
1076 if (port->pint) {
1077 for (offset = 0; offset < port->width; offset++)
1078 irq_dispose_mapping(irq_find_mapping(port->domain,
1079 offset));
1080 irq_domain_remove(port->domain);
1081 }
1082
1083 return ret;
1084}
1085
1086static int adi_pinctrl_probe(struct platform_device *pdev)
1087{
1088 struct adi_pinctrl *pinctrl;
1089
1090 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1091 if (!pinctrl)
1092 return -ENOMEM;
1093
1094 pinctrl->dev = &pdev->dev;
1095
1096 adi_pinctrl_soc_init(&pinctrl->soc);
1097
1098 adi_pinmux_desc.pins = pinctrl->soc->pins;
1099 adi_pinmux_desc.npins = pinctrl->soc->npins;
1100
1101 /* Now register the pin controller and all pins it handles */
1102 pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
1103 if (!pinctrl->pctl) {
1104 dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
1105 return -EINVAL;
1106 }
1107
1108 platform_set_drvdata(pdev, pinctrl);
1109
1110 return 0;
1111}
1112
1113static int adi_pinctrl_remove(struct platform_device *pdev)
1114{
1115 struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev);
1116
1117 pinctrl_unregister(pinctrl->pctl);
1118
1119 return 0;
1120}
1121
1122static struct platform_driver adi_pinctrl_driver = {
1123 .probe = adi_pinctrl_probe,
1124 .remove = adi_pinctrl_remove,
1125 .driver = {
1126 .name = DRIVER_NAME,
1127 },
1128};
1129
1130static struct platform_driver adi_gpio_pint_driver = {
1131 .probe = adi_gpio_pint_probe,
1132 .remove = adi_gpio_pint_remove,
1133 .driver = {
1134 .name = "adi-gpio-pint",
1135 },
1136};
1137
1138static struct platform_driver adi_gpio_driver = {
1139 .probe = adi_gpio_probe,
1140 .remove = adi_gpio_remove,
1141 .driver = {
1142 .name = "adi-gpio",
1143 },
1144};
1145
1146static int __init adi_pinctrl_setup(void)
1147{
1148 int ret;
1149
1150 ret = platform_driver_register(&adi_pinctrl_driver);
1151 if (ret)
1152 return ret;
1153
1154 ret = platform_driver_register(&adi_gpio_pint_driver);
1155 if (ret)
1156 goto pint_error;
1157
1158 ret = platform_driver_register(&adi_gpio_driver);
1159 if (ret)
1160 goto gpio_error;
1161
1162#ifdef CONFIG_PM
1163 register_syscore_ops(&gpio_pm_syscore_ops);
1164#endif
1165 return ret;
1166gpio_error:
1167 platform_driver_unregister(&adi_gpio_pint_driver);
1168pint_error:
1169 platform_driver_unregister(&adi_pinctrl_driver);
1170
1171 return ret;
1172}
1173arch_initcall(adi_pinctrl_setup);
1174
1175MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1176MODULE_DESCRIPTION("ADI gpio2 pin control driver");
1177MODULE_LICENSE("GPL");