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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17** J5000/J7000/N-class/L-class machines and their successors.
18**
19** FIXME: add DMA hint support programming in both sba and lba modules.
20*/
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/init.h>
27
28#include <linux/mm.h>
29#include <linux/string.h>
30#include <linux/pci.h>
FUJITA Tomonorib61e8f42007-10-23 09:30:28 +020031#include <linux/scatterlist.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032
33#include <asm/byteorder.h>
34#include <asm/io.h>
35#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
36
37#include <asm/hardware.h> /* for register_parisc_driver() stuff */
38
39#include <linux/proc_fs.h>
Kyle McMartin7ec14e42006-02-06 10:10:15 -070040#include <linux/seq_file.h>
41
Kyle McMartin1790cf92006-08-24 21:32:49 -040042#include <asm/ropes.h>
Kyle McMartin6f034952006-08-13 22:18:57 -040043#include <asm/mckinley.h> /* for proc_mckinley_root */
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <asm/runway.h> /* for proc_runway_root */
45#include <asm/pdc.h> /* for PDC_MODEL_* */
46#include <asm/pdcpat.h> /* for is_pdc_pat() */
47#include <asm/parisc-device.h>
48
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#define MODULE_NAME "SBA"
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051/*
52** The number of debug flags is a clue - this code is fragile.
53** Don't even think about messing with it unless you have
54** plenty of 710's to sacrifice to the computer gods. :^)
55*/
56#undef DEBUG_SBA_INIT
57#undef DEBUG_SBA_RUN
58#undef DEBUG_SBA_RUN_SG
59#undef DEBUG_SBA_RESOURCE
60#undef ASSERT_PDIR_SANITY
61#undef DEBUG_LARGE_SG_ENTRIES
62#undef DEBUG_DMB_TRAP
63
64#ifdef DEBUG_SBA_INIT
65#define DBG_INIT(x...) printk(x)
66#else
67#define DBG_INIT(x...)
68#endif
69
70#ifdef DEBUG_SBA_RUN
71#define DBG_RUN(x...) printk(x)
72#else
73#define DBG_RUN(x...)
74#endif
75
76#ifdef DEBUG_SBA_RUN_SG
77#define DBG_RUN_SG(x...) printk(x)
78#else
79#define DBG_RUN_SG(x...)
80#endif
81
82
83#ifdef DEBUG_SBA_RESOURCE
84#define DBG_RES(x...) printk(x)
85#else
86#define DBG_RES(x...)
87#endif
88
Linus Torvalds1da177e2005-04-16 15:20:36 -070089#define SBA_INLINE __inline__
90
Linus Torvalds1da177e2005-04-16 15:20:36 -070091#define DEFAULT_DMA_HINT_REG 0
92
Kyle McMartin08a64362006-08-24 21:33:40 -040093struct sba_device *sba_list;
94EXPORT_SYMBOL_GPL(sba_list);
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
96static unsigned long ioc_needs_fdc = 0;
97
98/* global count of IOMMUs in the system */
99static unsigned int global_ioc_cnt = 0;
100
101/* PA8700 (Piranha 2.2) bug workaround */
102static unsigned long piranha_bad_128k = 0;
103
104/* Looks nice and keeps the compiler happy */
105#define SBA_DEV(d) ((struct sba_device *) (d))
106
Kyle McMartin08a64362006-08-24 21:33:40 -0400107#ifdef CONFIG_AGP_PARISC
108#define SBA_AGP_SUPPORT
109#endif /*CONFIG_AGP_PARISC*/
110
Grant Grundler64908ad2005-10-21 22:37:20 -0400111#ifdef SBA_AGP_SUPPORT
Kyle McMartin08a64362006-08-24 21:33:40 -0400112static int sba_reserve_agpgart = 1;
Randy Dunlap29a1e1d2007-02-05 16:33:59 -0800113module_param(sba_reserve_agpgart, int, 0444);
Kyle McMartin08a64362006-08-24 21:33:40 -0400114MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115#endif
116
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
118/************************************
119** SBA register read and write support
120**
121** BE WARNED: register writes are posted.
122** (ie follow writes which must reach HW with a read)
123**
124** Superdome (in particular, REO) allows only 64-bit CSR accesses.
125*/
Grant Grundler40d78de2006-05-11 00:31:31 -0600126#define READ_REG32(addr) readl(addr)
127#define READ_REG64(addr) readq(addr)
128#define WRITE_REG32(val, addr) writel((val), (addr))
129#define WRITE_REG64(val, addr) writeq((val), (addr))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
Grant Grundler64908ad2005-10-21 22:37:20 -0400131#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132#define READ_REG(addr) READ_REG64(addr)
133#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
134#else
135#define READ_REG(addr) READ_REG32(addr)
136#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
137#endif
138
139#ifdef DEBUG_SBA_INIT
140
Grant Grundler64908ad2005-10-21 22:37:20 -0400141/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142
143/**
144 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
145 * @hpa: base address of the sba
146 *
147 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
148 * IO Adapter (aka Bus Converter).
149 */
150static void
151sba_dump_ranges(void __iomem *hpa)
152{
153 DBG_INIT("SBA at 0x%p\n", hpa);
154 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
155 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
156 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
157 DBG_INIT("\n");
158 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
159 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
160 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
161}
162
163/**
164 * sba_dump_tlb - debugging only - print IOMMU operating parameters
165 * @hpa: base address of the IOMMU
166 *
167 * Print the size/location of the IO MMU PDIR.
168 */
169static void sba_dump_tlb(void __iomem *hpa)
170{
171 DBG_INIT("IO TLB at 0x%p\n", hpa);
172 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
173 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
174 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
175 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
176 DBG_INIT("\n");
177}
178#else
179#define sba_dump_ranges(x)
180#define sba_dump_tlb(x)
Grant Grundler64908ad2005-10-21 22:37:20 -0400181#endif /* DEBUG_SBA_INIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182
183
184#ifdef ASSERT_PDIR_SANITY
185
186/**
187 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
188 * @ioc: IO MMU structure which owns the pdir we are interested in.
189 * @msg: text to print ont the output line.
190 * @pide: pdir index.
191 *
192 * Print one entry of the IO MMU PDIR in human readable form.
193 */
194static void
195sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
196{
197 /* start printing from lowest pde in rval */
198 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
199 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
200 uint rcnt;
201
202 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
203 msg,
204 rptr, pide & (BITS_PER_LONG - 1), *rptr);
205
206 rcnt = 0;
207 while (rcnt < BITS_PER_LONG) {
208 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
209 (rcnt == (pide & (BITS_PER_LONG - 1)))
210 ? " -->" : " ",
211 rcnt, ptr, *ptr );
212 rcnt++;
213 ptr++;
214 }
215 printk(KERN_DEBUG "%s", msg);
216}
217
218
219/**
220 * sba_check_pdir - debugging only - consistency checker
221 * @ioc: IO MMU structure which owns the pdir we are interested in.
222 * @msg: text to print ont the output line.
223 *
224 * Verify the resource map and pdir state is consistent
225 */
226static int
227sba_check_pdir(struct ioc *ioc, char *msg)
228{
229 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
230 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
231 u64 *pptr = ioc->pdir_base; /* pdir ptr */
232 uint pide = 0;
233
234 while (rptr < rptr_end) {
235 u32 rval = *rptr;
236 int rcnt = 32; /* number of bits we might check */
237
238 while (rcnt) {
239 /* Get last byte and highest bit from that */
240 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
241 if ((rval ^ pde) & 0x80000000)
242 {
243 /*
244 ** BUMMER! -- res_map != pdir --
245 ** Dump rval and matching pdir entries
246 */
247 sba_dump_pdir_entry(ioc, msg, pide);
248 return(1);
249 }
250 rcnt--;
251 rval <<= 1; /* try the next bit */
252 pptr++;
253 pide++;
254 }
255 rptr++; /* look at next word of res_map */
256 }
257 /* It'd be nice if we always got here :^) */
258 return 0;
259}
260
261
262/**
263 * sba_dump_sg - debugging only - print Scatter-Gather list
264 * @ioc: IO MMU structure which owns the pdir we are interested in.
265 * @startsg: head of the SG list
266 * @nents: number of entries in SG list
267 *
268 * print the SG list so we can verify it's correct by hand.
269 */
270static void
271sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
272{
273 while (nents-- > 0) {
274 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
275 nents,
276 (unsigned long) sg_dma_address(startsg),
277 sg_dma_len(startsg),
278 sg_virt_addr(startsg), startsg->length);
279 startsg++;
280 }
281}
282
283#endif /* ASSERT_PDIR_SANITY */
284
285
286
287
288/**************************************************************
289*
290* I/O Pdir Resource Management
291*
292* Bits set in the resource map are in use.
293* Each bit can represent a number of pages.
294* LSbs represent lower addresses (IOVA's).
295*
296***************************************************************/
297#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
298
299/* Convert from IOVP to IOVA and vice versa. */
300
301#ifdef ZX1_SUPPORT
302/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
303#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
304#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
305#else
306/* only support Astro and ancestors. Saves a few cycles in key places */
307#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
308#define SBA_IOVP(ioc,iova) (iova)
309#endif
310
311#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
312
313#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
314#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
315
316
317/**
318 * sba_search_bitmap - find free space in IO PDIR resource bitmap
319 * @ioc: IO MMU structure which owns the pdir we are interested in.
320 * @bits_wanted: number of entries we need.
321 *
322 * Find consecutive free bits in resource bitmap.
323 * Each bit represents one entry in the IO Pdir.
324 * Cool perf optimization: search for log2(size) bits at a time.
325 */
326static SBA_INLINE unsigned long
327sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
328{
329 unsigned long *res_ptr = ioc->res_hint;
330 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
331 unsigned long pide = ~0UL;
332
333 if (bits_wanted > (BITS_PER_LONG/2)) {
334 /* Search word at a time - no mask needed */
335 for(; res_ptr < res_end; ++res_ptr) {
336 if (*res_ptr == 0) {
337 *res_ptr = RESMAP_MASK(bits_wanted);
338 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
339 pide <<= 3; /* convert to bit address */
340 break;
341 }
342 }
343 /* point to the next word on next pass */
344 res_ptr++;
345 ioc->res_bitshift = 0;
346 } else {
347 /*
348 ** Search the resource bit map on well-aligned values.
349 ** "o" is the alignment.
350 ** We need the alignment to invalidate I/O TLB using
351 ** SBA HW features in the unmap path.
352 */
353 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
Milind Arun Choudhary3cb1d952007-03-06 02:44:13 -0800354 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355 unsigned long mask;
356
357 if (bitshiftcnt >= BITS_PER_LONG) {
358 bitshiftcnt = 0;
359 res_ptr++;
360 }
361 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
362
363 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
364 while(res_ptr < res_end)
365 {
366 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
367 WARN_ON(mask == 0);
368 if(((*res_ptr) & mask) == 0) {
369 *res_ptr |= mask; /* mark resources busy! */
370 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
371 pide <<= 3; /* convert to bit address */
372 pide += bitshiftcnt;
373 break;
374 }
375 mask >>= o;
376 bitshiftcnt += o;
377 if (mask == 0) {
378 mask = RESMAP_MASK(bits_wanted);
379 bitshiftcnt=0;
380 res_ptr++;
381 }
382 }
383 /* look in the same word on the next pass */
384 ioc->res_bitshift = bitshiftcnt + bits_wanted;
385 }
386
387 /* wrapped ? */
388 if (res_end <= res_ptr) {
389 ioc->res_hint = (unsigned long *) ioc->res_map;
390 ioc->res_bitshift = 0;
391 } else {
392 ioc->res_hint = res_ptr;
393 }
394 return (pide);
395}
396
397
398/**
399 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
400 * @ioc: IO MMU structure which owns the pdir we are interested in.
401 * @size: number of bytes to create a mapping for
402 *
403 * Given a size, find consecutive unmarked and then mark those bits in the
404 * resource bit map.
405 */
406static int
407sba_alloc_range(struct ioc *ioc, size_t size)
408{
409 unsigned int pages_needed = size >> IOVP_SHIFT;
410#ifdef SBA_COLLECT_STATS
411 unsigned long cr_start = mfctl(16);
412#endif
413 unsigned long pide;
414
415 pide = sba_search_bitmap(ioc, pages_needed);
416 if (pide >= (ioc->res_size << 3)) {
417 pide = sba_search_bitmap(ioc, pages_needed);
418 if (pide >= (ioc->res_size << 3))
419 panic("%s: I/O MMU @ %p is out of mapping resources\n",
420 __FILE__, ioc->ioc_hpa);
421 }
422
423#ifdef ASSERT_PDIR_SANITY
424 /* verify the first enable bit is clear */
425 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
426 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
427 }
428#endif
429
430 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
431 __FUNCTION__, size, pages_needed, pide,
432 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
433 ioc->res_bitshift );
434
435#ifdef SBA_COLLECT_STATS
436 {
437 unsigned long cr_end = mfctl(16);
438 unsigned long tmp = cr_end - cr_start;
439 /* check for roll over */
440 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
441 }
442 ioc->avg_search[ioc->avg_idx++] = cr_start;
443 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
444
445 ioc->used_pages += pages_needed;
446#endif
447
448 return (pide);
449}
450
451
452/**
453 * sba_free_range - unmark bits in IO PDIR resource bitmap
454 * @ioc: IO MMU structure which owns the pdir we are interested in.
455 * @iova: IO virtual address which was previously allocated.
456 * @size: number of bytes to create a mapping for
457 *
458 * clear bits in the ioc's resource map
459 */
460static SBA_INLINE void
461sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
462{
463 unsigned long iovp = SBA_IOVP(ioc, iova);
464 unsigned int pide = PDIR_INDEX(iovp);
465 unsigned int ridx = pide >> 3; /* convert bit to byte address */
466 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
467
468 int bits_not_wanted = size >> IOVP_SHIFT;
469
470 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
471 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
472
473 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
474 __FUNCTION__, (uint) iova, size,
475 bits_not_wanted, m, pide, res_ptr, *res_ptr);
476
477#ifdef SBA_COLLECT_STATS
478 ioc->used_pages -= bits_not_wanted;
479#endif
480
481 *res_ptr &= ~m;
482}
483
484
485/**************************************************************
486*
487* "Dynamic DMA Mapping" support (aka "Coherent I/O")
488*
489***************************************************************/
490
Grant Grundler64908ad2005-10-21 22:37:20 -0400491#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
493#endif
494
495typedef unsigned long space_t;
496#define KERNEL_SPACE 0
497
498/**
499 * sba_io_pdir_entry - fill in one IO PDIR entry
500 * @pdir_ptr: pointer to IO PDIR entry
501 * @sid: process Space ID - currently only support KERNEL_SPACE
502 * @vba: Virtual CPU address of buffer to map
503 * @hint: DMA hint set to use for this mapping
504 *
505 * SBA Mapping Routine
506 *
507 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
508 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
509 * pdir_ptr (arg0).
510 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
511 * for Astro/Ike looks like:
512 *
513 *
514 * 0 19 51 55 63
515 * +-+---------------------+----------------------------------+----+--------+
516 * |V| U | PPN[43:12] | U | VI |
517 * +-+---------------------+----------------------------------+----+--------+
518 *
519 * Pluto is basically identical, supports fewer physical address bits:
520 *
521 * 0 23 51 55 63
522 * +-+------------------------+-------------------------------+----+--------+
523 * |V| U | PPN[39:12] | U | VI |
524 * +-+------------------------+-------------------------------+----+--------+
525 *
526 * V == Valid Bit (Most Significant Bit is bit 0)
527 * U == Unused
528 * PPN == Physical Page Number
529 * VI == Virtual Index (aka Coherent Index)
530 *
531 * LPA instruction output is put into PPN field.
532 * LCI (Load Coherence Index) instruction provides the "VI" bits.
533 *
534 * We pre-swap the bytes since PCX-W is Big Endian and the
535 * IOMMU uses little endian for the pdir.
536 */
537
538void SBA_INLINE
539sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
540 unsigned long hint)
541{
542 u64 pa; /* physical address */
543 register unsigned ci; /* coherent index */
544
545 pa = virt_to_phys(vba);
546 pa &= IOVP_MASK;
547
548 mtsp(sid,1);
549 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
550 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
551
Kyle McMartin983daee2006-08-25 12:28:24 -0400552 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
554
555 /*
556 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
557 * (bit #61, big endian), we have to flush and sync every time
558 * IO-PDIR is changed in Ike/Astro.
559 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400560 if (ioc_needs_fdc)
561 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562}
563
564
565/**
566 * sba_mark_invalid - invalidate one or more IO PDIR entries
567 * @ioc: IO MMU structure which owns the pdir we are interested in.
568 * @iova: IO Virtual Address mapped earlier
569 * @byte_cnt: number of bytes this mapping covers.
570 *
571 * Marking the IO PDIR entry(ies) as Invalid and invalidate
572 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
573 * is to purge stale entries in the IO TLB when unmapping entries.
574 *
575 * The PCOM register supports purging of multiple pages, with a minium
576 * of 1 page and a maximum of 2GB. Hardware requires the address be
577 * aligned to the size of the range being purged. The size of the range
578 * must be a power of 2. The "Cool perf optimization" in the
579 * allocation routine helps keep that true.
580 */
581static SBA_INLINE void
582sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
583{
584 u32 iovp = (u32) SBA_IOVP(ioc,iova);
Grant Grundler64908ad2005-10-21 22:37:20 -0400585 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586
587#ifdef ASSERT_PDIR_SANITY
Grant Grundler64908ad2005-10-21 22:37:20 -0400588 /* Assert first pdir entry is set.
589 **
590 ** Even though this is a big-endian machine, the entries
591 ** in the iopdir are little endian. That's why we look at
592 ** the byte at +7 instead of at +0.
593 */
594 if (0x80 != (((u8 *) pdir_ptr)[7])) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
596 }
597#endif
598
Grant Grundler64908ad2005-10-21 22:37:20 -0400599 if (byte_cnt > IOVP_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600 {
Grant Grundler64908ad2005-10-21 22:37:20 -0400601#if 0
602 unsigned long entries_per_cacheline = ioc_needs_fdc ?
603 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
604 - (unsigned long) pdir_ptr;
605 : 262144;
606#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607
Grant Grundler64908ad2005-10-21 22:37:20 -0400608 /* set "size" field for PCOM */
609 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 do {
612 /* clear I/O Pdir entry "valid" bit first */
Grant Grundler64908ad2005-10-21 22:37:20 -0400613 ((u8 *) pdir_ptr)[7] = 0;
614 if (ioc_needs_fdc) {
615 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
616#if 0
617 entries_per_cacheline = L1_CACHE_SHIFT - 3;
618#endif
619 }
620 pdir_ptr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 byte_cnt -= IOVP_SIZE;
Grant Grundler64908ad2005-10-21 22:37:20 -0400622 } while (byte_cnt > IOVP_SIZE);
623 } else
624 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
625
626 /*
627 ** clear I/O PDIR entry "valid" bit.
628 ** We have to R/M/W the cacheline regardless how much of the
629 ** pdir entry that we clobber.
630 ** The rest of the entry would be useful for debugging if we
631 ** could dump core on HPMC.
632 */
633 ((u8 *) pdir_ptr)[7] = 0;
634 if (ioc_needs_fdc)
635 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636
637 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
638}
639
640/**
641 * sba_dma_supported - PCI driver can query DMA support
642 * @dev: instance of PCI owned by the driver that's asking
643 * @mask: number of address bits this PCI device can handle
644 *
645 * See Documentation/DMA-mapping.txt
646 */
647static int sba_dma_supported( struct device *dev, u64 mask)
648{
649 struct ioc *ioc;
Grant Grundler64908ad2005-10-21 22:37:20 -0400650
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 if (dev == NULL) {
652 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
653 BUG();
654 return(0);
655 }
656
Grant Grundler64908ad2005-10-21 22:37:20 -0400657 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
658 * then fall back to 32-bit if that fails.
659 * We are just "encouraging" 32-bit DMA masks here since we can
660 * never allow IOMMU bypass unless we add special support for ZX1.
661 */
662 if (mask > ~0U)
663 return 0;
664
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 ioc = GET_IOC(dev);
666
Grant Grundler64908ad2005-10-21 22:37:20 -0400667 /*
668 * check if mask is >= than the current max IO Virt Address
669 * The max IO Virt address will *always* < 30 bits.
670 */
671 return((int)(mask >= (ioc->ibase - 1 +
672 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673}
674
675
676/**
677 * sba_map_single - map one buffer and return IOVA for DMA
678 * @dev: instance of PCI owned by the driver that's asking.
679 * @addr: driver buffer to map.
680 * @size: number of bytes to map in driver buffer.
681 * @direction: R/W or both.
682 *
683 * See Documentation/DMA-mapping.txt
684 */
685static dma_addr_t
686sba_map_single(struct device *dev, void *addr, size_t size,
687 enum dma_data_direction direction)
688{
689 struct ioc *ioc;
690 unsigned long flags;
691 dma_addr_t iovp;
692 dma_addr_t offset;
693 u64 *pdir_start;
694 int pide;
695
696 ioc = GET_IOC(dev);
697
698 /* save offset bits */
699 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
700
701 /* round up to nearest IOVP_SIZE */
702 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
703
704 spin_lock_irqsave(&ioc->res_lock, flags);
705#ifdef ASSERT_PDIR_SANITY
706 sba_check_pdir(ioc,"Check before sba_map_single()");
707#endif
708
709#ifdef SBA_COLLECT_STATS
710 ioc->msingle_calls++;
711 ioc->msingle_pages += size >> IOVP_SHIFT;
712#endif
713 pide = sba_alloc_range(ioc, size);
714 iovp = (dma_addr_t) pide << IOVP_SHIFT;
715
716 DBG_RUN("%s() 0x%p -> 0x%lx\n",
717 __FUNCTION__, addr, (long) iovp | offset);
718
719 pdir_start = &(ioc->pdir_base[pide]);
720
721 while (size > 0) {
722 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
723
724 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
725 pdir_start,
726 (u8) (((u8 *) pdir_start)[7]),
727 (u8) (((u8 *) pdir_start)[6]),
728 (u8) (((u8 *) pdir_start)[5]),
729 (u8) (((u8 *) pdir_start)[4]),
730 (u8) (((u8 *) pdir_start)[3]),
731 (u8) (((u8 *) pdir_start)[2]),
732 (u8) (((u8 *) pdir_start)[1]),
733 (u8) (((u8 *) pdir_start)[0])
734 );
735
736 addr += IOVP_SIZE;
737 size -= IOVP_SIZE;
738 pdir_start++;
739 }
Grant Grundler64908ad2005-10-21 22:37:20 -0400740
741 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
742 if (ioc_needs_fdc)
743 asm volatile("sync" : : );
744
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745#ifdef ASSERT_PDIR_SANITY
746 sba_check_pdir(ioc,"Check after sba_map_single()");
747#endif
748 spin_unlock_irqrestore(&ioc->res_lock, flags);
Grant Grundler64908ad2005-10-21 22:37:20 -0400749
750 /* form complete address */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
752}
753
754
755/**
756 * sba_unmap_single - unmap one IOVA and free resources
757 * @dev: instance of PCI owned by the driver that's asking.
758 * @iova: IOVA of driver buffer previously mapped.
759 * @size: number of bytes mapped in driver buffer.
760 * @direction: R/W or both.
761 *
762 * See Documentation/DMA-mapping.txt
763 */
764static void
765sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
766 enum dma_data_direction direction)
767{
768 struct ioc *ioc;
769#if DELAYED_RESOURCE_CNT > 0
770 struct sba_dma_pair *d;
771#endif
772 unsigned long flags;
773 dma_addr_t offset;
774
775 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
776
777 ioc = GET_IOC(dev);
778 offset = iova & ~IOVP_MASK;
779 iova ^= offset; /* clear offset bits */
780 size += offset;
Milind Arun Choudhary3cb1d952007-03-06 02:44:13 -0800781 size = ALIGN(size, IOVP_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782
783 spin_lock_irqsave(&ioc->res_lock, flags);
784
785#ifdef SBA_COLLECT_STATS
786 ioc->usingle_calls++;
787 ioc->usingle_pages += size >> IOVP_SHIFT;
788#endif
789
790 sba_mark_invalid(ioc, iova, size);
791
792#if DELAYED_RESOURCE_CNT > 0
793 /* Delaying when we re-use a IO Pdir entry reduces the number
794 * of MMIO reads needed to flush writes to the PCOM register.
795 */
796 d = &(ioc->saved[ioc->saved_cnt]);
797 d->iova = iova;
798 d->size = size;
799 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
800 int cnt = ioc->saved_cnt;
801 while (cnt--) {
802 sba_free_range(ioc, d->iova, d->size);
803 d--;
804 }
805 ioc->saved_cnt = 0;
Grant Grundler64908ad2005-10-21 22:37:20 -0400806
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
808 }
809#else /* DELAYED_RESOURCE_CNT == 0 */
810 sba_free_range(ioc, iova, size);
Grant Grundler64908ad2005-10-21 22:37:20 -0400811
812 /* If fdc's were issued, force fdc's to be visible now */
813 if (ioc_needs_fdc)
814 asm volatile("sync" : : );
815
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
817#endif /* DELAYED_RESOURCE_CNT == 0 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400818
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 spin_unlock_irqrestore(&ioc->res_lock, flags);
820
821 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
822 ** For Astro based systems this isn't a big deal WRT performance.
823 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
824 ** we don't need the syncdma. The issue here is I/O MMU cachelines
825 ** are *not* coherent in all cases. May be hwrev dependent.
826 ** Need to investigate more.
827 asm volatile("syncdma");
828 */
829}
830
831
832/**
833 * sba_alloc_consistent - allocate/map shared mem for DMA
834 * @hwdev: instance of PCI owned by the driver that's asking.
835 * @size: number of bytes mapped in driver buffer.
836 * @dma_handle: IOVA of new buffer.
837 *
838 * See Documentation/DMA-mapping.txt
839 */
840static void *sba_alloc_consistent(struct device *hwdev, size_t size,
Al Viro5c1fb412005-10-21 03:21:28 -0400841 dma_addr_t *dma_handle, gfp_t gfp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842{
843 void *ret;
844
845 if (!hwdev) {
846 /* only support PCI */
847 *dma_handle = 0;
Matthew Wilcoxc2c47982006-10-26 10:06:07 -0600848 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 }
850
851 ret = (void *) __get_free_pages(gfp, get_order(size));
852
853 if (ret) {
854 memset(ret, 0, size);
855 *dma_handle = sba_map_single(hwdev, ret, size, 0);
856 }
857
858 return ret;
859}
860
861
862/**
863 * sba_free_consistent - free/unmap shared mem for DMA
864 * @hwdev: instance of PCI owned by the driver that's asking.
865 * @size: number of bytes mapped in driver buffer.
866 * @vaddr: virtual address IOVA of "consistent" buffer.
867 * @dma_handler: IO virtual address of "consistent" buffer.
868 *
869 * See Documentation/DMA-mapping.txt
870 */
871static void
872sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
873 dma_addr_t dma_handle)
874{
875 sba_unmap_single(hwdev, dma_handle, size, 0);
876 free_pages((unsigned long) vaddr, get_order(size));
877}
878
879
880/*
881** Since 0 is a valid pdir_base index value, can't use that
882** to determine if a value is valid or not. Use a flag to indicate
883** the SG list entry contains a valid pdir index.
884*/
885#define PIDE_FLAG 0x80000000UL
886
887#ifdef SBA_COLLECT_STATS
888#define IOMMU_MAP_STATS
889#endif
890#include "iommu-helpers.h"
891
892#ifdef DEBUG_LARGE_SG_ENTRIES
893int dump_run_sg = 0;
894#endif
895
896
897/**
898 * sba_map_sg - map Scatter/Gather list
899 * @dev: instance of PCI owned by the driver that's asking.
900 * @sglist: array of buffer/length pairs
901 * @nents: number of entries in list
902 * @direction: R/W or both.
903 *
904 * See Documentation/DMA-mapping.txt
905 */
906static int
907sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
908 enum dma_data_direction direction)
909{
910 struct ioc *ioc;
911 int coalesced, filled = 0;
912 unsigned long flags;
913
914 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
915
916 ioc = GET_IOC(dev);
917
918 /* Fast path single entry scatterlists. */
919 if (nents == 1) {
920 sg_dma_address(sglist) = sba_map_single(dev,
921 (void *)sg_virt_addr(sglist),
922 sglist->length, direction);
923 sg_dma_len(sglist) = sglist->length;
924 return 1;
925 }
926
927 spin_lock_irqsave(&ioc->res_lock, flags);
928
929#ifdef ASSERT_PDIR_SANITY
930 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
931 {
932 sba_dump_sg(ioc, sglist, nents);
933 panic("Check before sba_map_sg()");
934 }
935#endif
936
937#ifdef SBA_COLLECT_STATS
938 ioc->msg_calls++;
939#endif
940
941 /*
942 ** First coalesce the chunks and allocate I/O pdir space
943 **
944 ** If this is one DMA stream, we can properly map using the
945 ** correct virtual address associated with each DMA page.
946 ** w/o this association, we wouldn't have coherent DMA!
947 ** Access to the virtual address is what forces a two pass algorithm.
948 */
949 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
950
951 /*
952 ** Program the I/O Pdir
953 **
954 ** map the virtual addresses to the I/O Pdir
955 ** o dma_address will contain the pdir index
956 ** o dma_len will contain the number of bytes to map
957 ** o address contains the virtual address.
958 */
959 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
960
Grant Grundler64908ad2005-10-21 22:37:20 -0400961 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
962 if (ioc_needs_fdc)
963 asm volatile("sync" : : );
964
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965#ifdef ASSERT_PDIR_SANITY
966 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
967 {
968 sba_dump_sg(ioc, sglist, nents);
969 panic("Check after sba_map_sg()\n");
970 }
971#endif
972
973 spin_unlock_irqrestore(&ioc->res_lock, flags);
974
975 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
976
977 return filled;
978}
979
980
981/**
982 * sba_unmap_sg - unmap Scatter/Gather list
983 * @dev: instance of PCI owned by the driver that's asking.
984 * @sglist: array of buffer/length pairs
985 * @nents: number of entries in list
986 * @direction: R/W or both.
987 *
988 * See Documentation/DMA-mapping.txt
989 */
990static void
991sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
992 enum dma_data_direction direction)
993{
994 struct ioc *ioc;
995#ifdef ASSERT_PDIR_SANITY
996 unsigned long flags;
997#endif
998
999 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1000 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1001
1002 ioc = GET_IOC(dev);
1003
1004#ifdef SBA_COLLECT_STATS
1005 ioc->usg_calls++;
1006#endif
1007
1008#ifdef ASSERT_PDIR_SANITY
1009 spin_lock_irqsave(&ioc->res_lock, flags);
1010 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1011 spin_unlock_irqrestore(&ioc->res_lock, flags);
1012#endif
1013
1014 while (sg_dma_len(sglist) && nents--) {
1015
1016 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1017#ifdef SBA_COLLECT_STATS
1018 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1019 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1020#endif
1021 ++sglist;
1022 }
1023
1024 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1025
1026#ifdef ASSERT_PDIR_SANITY
1027 spin_lock_irqsave(&ioc->res_lock, flags);
1028 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1029 spin_unlock_irqrestore(&ioc->res_lock, flags);
1030#endif
1031
1032}
1033
1034static struct hppa_dma_ops sba_ops = {
1035 .dma_supported = sba_dma_supported,
1036 .alloc_consistent = sba_alloc_consistent,
1037 .alloc_noncoherent = sba_alloc_consistent,
1038 .free_consistent = sba_free_consistent,
1039 .map_single = sba_map_single,
1040 .unmap_single = sba_unmap_single,
1041 .map_sg = sba_map_sg,
1042 .unmap_sg = sba_unmap_sg,
1043 .dma_sync_single_for_cpu = NULL,
1044 .dma_sync_single_for_device = NULL,
1045 .dma_sync_sg_for_cpu = NULL,
1046 .dma_sync_sg_for_device = NULL,
1047};
1048
1049
1050/**************************************************************************
1051**
1052** SBA PAT PDC support
1053**
1054** o call pdc_pat_cell_module()
1055** o store ranges in PCI "resource" structures
1056**
1057**************************************************************************/
1058
1059static void
1060sba_get_pat_resources(struct sba_device *sba_dev)
1061{
1062#if 0
1063/*
1064** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1065** PAT PDC to program the SBA/LBA directed range registers...this
1066** burden may fall on the LBA code since it directly supports the
1067** PCI subsystem. It's not clear yet. - ggg
1068*/
1069PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1070 FIXME : ???
1071PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1072 Tells where the dvi bits are located in the address.
1073PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1074 FIXME : ???
1075#endif
1076}
1077
1078
1079/**************************************************************
1080*
1081* Initialization and claim
1082*
1083***************************************************************/
1084#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1085#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1086static void *
1087sba_alloc_pdir(unsigned int pdir_size)
1088{
1089 unsigned long pdir_base;
1090 unsigned long pdir_order = get_order(pdir_size);
1091
1092 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
Grant Grundler64908ad2005-10-21 22:37:20 -04001093 if (NULL == (void *) pdir_base) {
1094 panic("%s() could not allocate I/O Page Table\n",
1095 __FUNCTION__);
1096 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097
1098 /* If this is not PA8700 (PCX-W2)
1099 ** OR newer than ver 2.2
1100 ** OR in a system that doesn't need VINDEX bits from SBA,
1101 **
1102 ** then we aren't exposed to the HW bug.
1103 */
1104 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1105 || (boot_cpu_data.pdc.versions > 0x202)
1106 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1107 return (void *) pdir_base;
1108
1109 /*
1110 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1111 *
1112 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1113 * Ike/Astro can cause silent data corruption. This is only
1114 * a problem if the I/O PDIR is located in memory such that
1115 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1116 *
1117 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1118 * right physical address, we can either avoid (IOPDIR <= 1MB)
1119 * or minimize (2MB IO Pdir) the problem if we restrict the
1120 * IO Pdir to a maximum size of 2MB-128K (1902K).
1121 *
1122 * Because we always allocate 2^N sized IO pdirs, either of the
1123 * "bad" regions will be the last 128K if at all. That's easy
1124 * to test for.
1125 *
1126 */
1127 if (pdir_order <= (19-12)) {
1128 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1129 /* allocate a new one on 512k alignment */
1130 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1131 /* release original */
1132 free_pages(pdir_base, pdir_order);
1133
1134 pdir_base = new_pdir;
1135
1136 /* release excess */
1137 while (pdir_order < (19-12)) {
1138 new_pdir += pdir_size;
1139 free_pages(new_pdir, pdir_order);
1140 pdir_order +=1;
1141 pdir_size <<=1;
1142 }
1143 }
1144 } else {
1145 /*
1146 ** 1MB or 2MB Pdir
1147 ** Needs to be aligned on an "odd" 1MB boundary.
1148 */
1149 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1150
1151 /* release original */
1152 free_pages( pdir_base, pdir_order);
1153
1154 /* release first 1MB */
1155 free_pages(new_pdir, 20-12);
1156
1157 pdir_base = new_pdir + 1024*1024;
1158
1159 if (pdir_order > (20-12)) {
1160 /*
1161 ** 2MB Pdir.
1162 **
1163 ** Flag tells init_bitmap() to mark bad 128k as used
1164 ** and to reduce the size by 128k.
1165 */
1166 piranha_bad_128k = 1;
1167
1168 new_pdir += 3*1024*1024;
1169 /* release last 1MB */
1170 free_pages(new_pdir, 20-12);
1171
1172 /* release unusable 128KB */
1173 free_pages(new_pdir - 128*1024 , 17-12);
1174
1175 pdir_size -= 128*1024;
1176 }
1177 }
1178
1179 memset((void *) pdir_base, 0, pdir_size);
1180 return (void *) pdir_base;
1181}
1182
Matthew Wilcox56583742005-10-21 22:33:38 -04001183static struct device *next_device(struct klist_iter *i)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184{
Matthew Wilcox56583742005-10-21 22:33:38 -04001185 struct klist_node * n = klist_next(i);
1186 return n ? container_of(n, struct device, knode_parent) : NULL;
1187}
1188
1189/* setup Mercury or Elroy IBASE/IMASK registers. */
1190static void
1191setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1192{
1193 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1195 struct device *dev;
Matthew Wilcox56583742005-10-21 22:33:38 -04001196 struct klist_iter i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197
Matthew Wilcox56583742005-10-21 22:33:38 -04001198 klist_iter_init(&sba->dev.klist_children, &i);
1199 while ((dev = next_device(&i))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200 struct parisc_device *lba = to_parisc_device(dev);
Matthew Wilcox56583742005-10-21 22:33:38 -04001201 int rope_num = (lba->hpa.start >> 13) & 0xf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001202 if (rope_num >> 3 == ioc_num)
1203 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1204 }
Matthew Wilcox56583742005-10-21 22:33:38 -04001205 klist_iter_exit(&i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001206}
1207
1208static void
1209sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1210{
1211 u32 iova_space_mask;
1212 u32 iova_space_size;
1213 int iov_order, tcnfg;
Grant Grundler64908ad2005-10-21 22:37:20 -04001214#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215 int agp_found = 0;
1216#endif
1217 /*
1218 ** Firmware programs the base and size of a "safe IOVA space"
1219 ** (one that doesn't overlap memory or LMMIO space) in the
1220 ** IBASE and IMASK registers.
1221 */
1222 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1223 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1224
1225 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1226 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1227 iova_space_size /= 2;
1228 }
1229
1230 /*
1231 ** iov_order is always based on a 1GB IOVA space since we want to
1232 ** turn on the other half for AGP GART.
1233 */
1234 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1235 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1236
Grant Grundler40d78de2006-05-11 00:31:31 -06001237 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
1239 iov_order + PAGE_SHIFT);
1240
1241 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1242 get_order(ioc->pdir_size));
1243 if (!ioc->pdir_base)
1244 panic("Couldn't allocate I/O Page Table\n");
1245
1246 memset(ioc->pdir_base, 0, ioc->pdir_size);
1247
1248 DBG_INIT("%s() pdir %p size %x\n",
1249 __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
1250
Grant Grundler64908ad2005-10-21 22:37:20 -04001251#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1253 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1254
1255 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1256 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1257#endif
1258
1259 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1260 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1261
1262 /* build IMASK for IOC and Elroy */
1263 iova_space_mask = 0xffffffff;
1264 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1265 ioc->imask = iova_space_mask;
1266#ifdef ZX1_SUPPORT
1267 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1268#endif
1269 sba_dump_tlb(ioc->ioc_hpa);
1270
1271 setup_ibase_imask(sba, ioc, ioc_num);
1272
1273 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1274
Grant Grundler64908ad2005-10-21 22:37:20 -04001275#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276 /*
1277 ** Setting the upper bits makes checking for bypass addresses
1278 ** a little faster later on.
1279 */
1280 ioc->imask |= 0xFFFFFFFF00000000UL;
1281#endif
1282
1283 /* Set I/O PDIR Page size to system page size */
1284 switch (PAGE_SHIFT) {
1285 case 12: tcnfg = 0; break; /* 4K */
1286 case 13: tcnfg = 1; break; /* 8K */
1287 case 14: tcnfg = 2; break; /* 16K */
1288 case 16: tcnfg = 3; break; /* 64K */
1289 default:
1290 panic(__FILE__ "Unsupported system page size %d",
1291 1 << PAGE_SHIFT);
1292 break;
1293 }
1294 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1295
1296 /*
1297 ** Program the IOC's ibase and enable IOVA translation
1298 ** Bit zero == enable bit.
1299 */
1300 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1301
1302 /*
1303 ** Clear I/O TLB of any possible entries.
1304 ** (Yes. This is a bit paranoid...but so what)
1305 */
1306 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1307
Grant Grundler64908ad2005-10-21 22:37:20 -04001308#ifdef SBA_AGP_SUPPORT
Kyle McMartin08a64362006-08-24 21:33:40 -04001309{
1310 struct klist_iter i;
1311 struct device *dev = NULL;
1312
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313 /*
1314 ** If an AGP device is present, only use half of the IOV space
1315 ** for PCI DMA. Unfortunately we can't know ahead of time
1316 ** whether GART support will actually be used, for now we
1317 ** can just key on any AGP device found in the system.
1318 ** We program the next pdir index after we stop w/ a key for
1319 ** the GART code to handshake on.
1320 */
Kyle McMartin08a64362006-08-24 21:33:40 -04001321 klist_iter_init(&sba->dev.klist_children, &i);
Matthew Wilcoxee9f4b52006-10-04 13:08:33 -06001322 while ((dev = next_device(&i))) {
Kyle McMartin08a64362006-08-24 21:33:40 -04001323 struct parisc_device *lba = to_parisc_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324 if (IS_QUICKSILVER(lba))
Kyle McMartin08a64362006-08-24 21:33:40 -04001325 agp_found = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326 }
Matthew Wilcoxee9f4b52006-10-04 13:08:33 -06001327 klist_iter_exit(&i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328
Kyle McMartin08a64362006-08-24 21:33:40 -04001329 if (agp_found && sba_reserve_agpgart) {
1330 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1331 __FUNCTION__, (iova_space_size/2) >> 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 ioc->pdir_size /= 2;
Kyle McMartin08a64362006-08-24 21:33:40 -04001333 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334 }
Kyle McMartin08a64362006-08-24 21:33:40 -04001335}
1336#endif /*SBA_AGP_SUPPORT*/
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337
1338}
1339
1340static void
1341sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1342{
1343 u32 iova_space_size, iova_space_mask;
1344 unsigned int pdir_size, iov_order;
1345
1346 /*
1347 ** Determine IOVA Space size from memory size.
1348 **
1349 ** Ideally, PCI drivers would register the maximum number
1350 ** of DMA they can have outstanding for each device they
1351 ** own. Next best thing would be to guess how much DMA
1352 ** can be outstanding based on PCI Class/sub-class. Both
1353 ** methods still require some "extra" to support PCI
1354 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1355 **
1356 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1357 ** for DMA hints - ergo only 30 bits max.
1358 */
1359
1360 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1361
1362 /* limit IOVA space size to 1MB-1GB */
1363 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1364 iova_space_size = 1 << (20 - PAGE_SHIFT);
1365 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1367 iova_space_size = 1 << (30 - PAGE_SHIFT);
1368 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369
1370 /*
1371 ** iova space must be log2() in size.
1372 ** thus, pdir/res_map will also be log2().
1373 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1374 */
1375 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1376
1377 /* iova_space_size is now bytes, not pages */
1378 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1379
1380 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1381
1382 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1383 __FUNCTION__,
1384 ioc->ioc_hpa,
1385 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1386 iova_space_size>>20,
1387 iov_order + PAGE_SHIFT);
1388
1389 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1390
1391 DBG_INIT("%s() pdir %p size %x\n",
1392 __FUNCTION__, ioc->pdir_base, pdir_size);
1393
Grant Grundler64908ad2005-10-21 22:37:20 -04001394#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395 /* FIXME : DMA HINTs not used */
1396 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1397 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1398
1399 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1400 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1401#endif
1402
1403 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1404
1405 /* build IMASK for IOC and Elroy */
1406 iova_space_mask = 0xffffffff;
1407 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1408
1409 /*
1410 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1411 ** ibase=0, imask=0xFE000000, size=0x2000000.
1412 */
1413 ioc->ibase = 0;
1414 ioc->imask = iova_space_mask; /* save it */
1415#ifdef ZX1_SUPPORT
1416 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1417#endif
1418
1419 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1420 __FUNCTION__, ioc->ibase, ioc->imask);
1421
1422 /*
1423 ** FIXME: Hint registers are programmed with default hint
1424 ** values during boot, so hints should be sane even if we
1425 ** can't reprogram them the way drivers want.
1426 */
1427
1428 setup_ibase_imask(sba, ioc, ioc_num);
1429
1430 /*
1431 ** Program the IOC's ibase and enable IOVA translation
1432 */
1433 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1434 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1435
1436 /* Set I/O PDIR Page size to 4K */
1437 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1438
1439 /*
1440 ** Clear I/O TLB of any possible entries.
1441 ** (Yes. This is a bit paranoid...but so what)
1442 */
1443 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1444
1445 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1446
1447 DBG_INIT("%s() DONE\n", __FUNCTION__);
1448}
1449
1450
1451
1452/**************************************************************************
1453**
1454** SBA initialization code (HW and SW)
1455**
1456** o identify SBA chip itself
1457** o initialize SBA chip modes (HardFail)
1458** o initialize SBA chip modes (HardFail)
1459** o FIXME: initialize DMA hints for reasonable defaults
1460**
1461**************************************************************************/
1462
Helge Deller5076c152006-03-27 12:52:15 -07001463static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464{
Helge Deller5076c152006-03-27 12:52:15 -07001465 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466}
1467
1468static void sba_hw_init(struct sba_device *sba_dev)
1469{
1470 int i;
1471 int num_ioc;
1472 u64 ioc_ctl;
1473
1474 if (!is_pdc_pat()) {
1475 /* Shutdown the USB controller on Astro-based workstations.
1476 ** Once we reprogram the IOMMU, the next DMA performed by
1477 ** USB will HPMC the box. USB is only enabled if a
1478 ** keyboard is present and found.
1479 **
1480 ** With serial console, j6k v5.0 firmware says:
1481 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1482 **
1483 ** FIXME: Using GFX+USB console at power up but direct
1484 ** linux to serial console is still broken.
1485 ** USB could generate DMA so we must reset USB.
1486 ** The proper sequence would be:
1487 ** o block console output
1488 ** o reset USB device
1489 ** o reprogram serial port
1490 ** o unblock console output
1491 */
1492 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1493 pdc_io_reset_devices();
1494 }
1495
1496 }
1497
1498
1499#if 0
1500printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1501 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1502
1503 /*
1504 ** Need to deal with DMA from LAN.
1505 ** Maybe use page zero boot device as a handle to talk
1506 ** to PDC about which device to shutdown.
1507 **
1508 ** Netbooting, j6k v5.0 firmware says:
1509 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1510 ** ARGH! invalid class.
1511 */
1512 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1513 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1514 pdc_io_reset();
1515 }
1516#endif
1517
Kyle McMartin1b240f42006-08-24 21:30:19 -04001518 if (!IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1520 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1521 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1522 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1523 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1524 /* j6700 v1.6 firmware sets 0x294f */
1525 /* A500 firmware sets 0x4d */
1526
1527 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1528
1529#ifdef DEBUG_SBA_INIT
1530 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1531 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1532#endif
1533 } /* if !PLUTO */
1534
Kyle McMartin1b240f42006-08-24 21:30:19 -04001535 if (IS_ASTRO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1538 num_ioc = 1;
1539
1540 sba_dev->chip_resv.name = "Astro Intr Ack";
1541 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1542 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1543 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
Eric Sesterhennb7494552006-03-24 18:52:10 +01001544 BUG_ON(err < 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545
Kyle McMartin1b240f42006-08-24 21:30:19 -04001546 } else if (IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547 int err;
1548
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1550 num_ioc = 1;
1551
1552 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1553 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1554 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1555 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1556 WARN_ON(err < 0);
1557
1558 sba_dev->iommu_resv.name = "IOVA Space";
1559 sba_dev->iommu_resv.start = 0x40000000UL;
1560 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1561 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1562 WARN_ON(err < 0);
1563 } else {
Matthew Wilcox78860892006-09-12 05:19:15 -06001564 /* IKE, REO */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1566 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1567 num_ioc = 2;
1568
1569 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1570 }
Matthew Wilcox78860892006-09-12 05:19:15 -06001571 /* XXX: What about Reo Grande? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001572
1573 sba_dev->num_ioc = num_ioc;
1574 for (i = 0; i < num_ioc; i++) {
Grant Grundler40d78de2006-05-11 00:31:31 -06001575 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
Grant Grundlerb312c332006-03-30 07:13:21 +00001576 unsigned int j;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577
Grant Grundlerb312c332006-03-30 07:13:21 +00001578 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1579
1580 /*
1581 * Clear ROPE(N)_CONFIG AO bit.
1582 * Disables "NT Ordering" (~= !"Relaxed Ordering")
1583 * Overrides bit 1 in DMA Hint Sets.
1584 * Improves netperf UDP_STREAM by ~10% for bcm5701.
1585 */
Kyle McMartin1b240f42006-08-24 21:30:19 -04001586 if (IS_PLUTO(sba_dev->dev)) {
Grant Grundler40d78de2006-05-11 00:31:31 -06001587 void __iomem *rope_cfg;
1588 unsigned long cfg_val;
Grant Grundlerb312c332006-03-30 07:13:21 +00001589
1590 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1591 cfg_val = READ_REG(rope_cfg);
1592 cfg_val &= ~IOC_ROPE_AO;
1593 WRITE_REG(cfg_val, rope_cfg);
1594 }
1595
1596 /*
1597 ** Make sure the box crashes on rope errors.
1598 */
1599 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1600 }
1601
1602 /* flush out the last writes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1604
1605 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1606 i,
1607 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1608 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1609 );
1610 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1611 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1612 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1613 );
1614
Kyle McMartin1b240f42006-08-24 21:30:19 -04001615 if (IS_PLUTO(sba_dev->dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1617 } else {
1618 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1619 }
1620 }
1621}
1622
1623static void
1624sba_common_init(struct sba_device *sba_dev)
1625{
1626 int i;
1627
1628 /* add this one to the head of the list (order doesn't matter)
1629 ** This will be useful for debugging - especially if we get coredumps
1630 */
1631 sba_dev->next = sba_list;
1632 sba_list = sba_dev;
1633
1634 for(i=0; i< sba_dev->num_ioc; i++) {
1635 int res_size;
1636#ifdef DEBUG_DMB_TRAP
1637 extern void iterate_pages(unsigned long , unsigned long ,
1638 void (*)(pte_t * , unsigned long),
1639 unsigned long );
1640 void set_data_memory_break(pte_t * , unsigned long);
1641#endif
1642 /* resource map size dictated by pdir_size */
1643 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1644
1645 /* Second part of PIRANHA BUG */
1646 if (piranha_bad_128k) {
1647 res_size -= (128*1024)/sizeof(u64);
1648 }
1649
1650 res_size >>= 3; /* convert bit count to byte count */
1651 DBG_INIT("%s() res_size 0x%x\n",
1652 __FUNCTION__, res_size);
1653
1654 sba_dev->ioc[i].res_size = res_size;
1655 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1656
1657#ifdef DEBUG_DMB_TRAP
1658 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1659 set_data_memory_break, 0);
1660#endif
1661
1662 if (NULL == sba_dev->ioc[i].res_map)
1663 {
1664 panic("%s:%s() could not allocate resource map\n",
1665 __FILE__, __FUNCTION__ );
1666 }
1667
1668 memset(sba_dev->ioc[i].res_map, 0, res_size);
1669 /* next available IOVP - circular search */
1670 sba_dev->ioc[i].res_hint = (unsigned long *)
1671 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1672
1673#ifdef ASSERT_PDIR_SANITY
1674 /* Mark first bit busy - ie no IOVA 0 */
1675 sba_dev->ioc[i].res_map[0] = 0x80;
1676 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1677#endif
1678
1679 /* Third (and last) part of PIRANHA BUG */
1680 if (piranha_bad_128k) {
1681 /* region from +1408K to +1536 is un-usable. */
1682
1683 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1684 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1685 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1686 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1687
1688 /* mark that part of the io pdir busy */
1689 while (p_start < p_end)
1690 *p_start++ = -1;
1691
1692 }
1693
1694#ifdef DEBUG_DMB_TRAP
1695 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1696 set_data_memory_break, 0);
1697 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1698 set_data_memory_break, 0);
1699#endif
1700
1701 DBG_INIT("%s() %d res_map %x %p\n",
1702 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1703 }
1704
1705 spin_lock_init(&sba_dev->sba_lock);
1706 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1707
1708#ifdef DEBUG_SBA_INIT
1709 /*
1710 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1711 * (bit #61, big endian), we have to flush and sync every time
1712 * IO-PDIR is changed in Ike/Astro.
1713 */
Kyle McMartin692086e2006-05-30 17:50:29 +00001714 if (ioc_needs_fdc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001715 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1716 } else {
1717 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1718 }
1719#endif
1720}
1721
1722#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001723static int sba_proc_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724{
1725 struct sba_device *sba_dev = sba_list;
1726 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1727 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728#ifdef SBA_COLLECT_STATS
1729 unsigned long avg = 0, min, max;
1730#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001731 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001733 len += seq_printf(m, "%s rev %d.%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734 sba_dev->name,
1735 (sba_dev->hw_rev & 0x7) + 1,
1736 (sba_dev->hw_rev & 0x18) >> 3
1737 );
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001738 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1740 total_pages);
1741
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001742 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1743 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001745 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1747 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1748 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1749 );
1750
1751 for (i=0; i<4; i++)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001752 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001753 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1754 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1755 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1756 );
1757
1758#ifdef SBA_COLLECT_STATS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001759 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760 total_pages - ioc->used_pages, ioc->used_pages,
1761 (int) (ioc->used_pages * 100 / total_pages));
1762
1763 min = max = ioc->avg_search[0];
1764 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1765 avg += ioc->avg_search[i];
1766 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1767 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1768 }
1769 avg /= SBA_SEARCH_SAMPLE;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001770 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1771 min, avg, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001773 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1774 ioc->msingle_calls, ioc->msingle_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1776
1777 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1778 min = ioc->usingle_calls;
1779 max = ioc->usingle_pages - ioc->usg_pages;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001780 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1781 min, max, (int) ((max * 1000)/min));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001782
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001783 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1784 ioc->msg_calls, ioc->msg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1786
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001787 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1788 ioc->usg_calls, ioc->usg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1790#endif
1791
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001792 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001793}
1794
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795static int
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001796sba_proc_open(struct inode *i, struct file *f)
1797{
1798 return single_open(f, &sba_proc_info, NULL);
1799}
1800
Arjan van de Vend54b1fd2007-02-12 00:55:34 -08001801static const struct file_operations sba_proc_fops = {
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001802 .owner = THIS_MODULE,
1803 .open = sba_proc_open,
1804 .read = seq_read,
1805 .llseek = seq_lseek,
1806 .release = single_release,
1807};
1808
1809static int
1810sba_proc_bitmap_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811{
1812 struct sba_device *sba_dev = sba_list;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001813 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001815 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001817 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001818 if ((i & 7) == 0)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001819 len += seq_printf(m, "\n ");
1820 len += seq_printf(m, " %08x", *res_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001822 len += seq_printf(m, "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001824 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825}
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001826
1827static int
1828sba_proc_bitmap_open(struct inode *i, struct file *f)
1829{
1830 return single_open(f, &sba_proc_bitmap_info, NULL);
1831}
1832
Arjan van de Vend54b1fd2007-02-12 00:55:34 -08001833static const struct file_operations sba_proc_bitmap_fops = {
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001834 .owner = THIS_MODULE,
1835 .open = sba_proc_bitmap_open,
1836 .read = seq_read,
1837 .llseek = seq_lseek,
1838 .release = single_release,
1839};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840#endif /* CONFIG_PROC_FS */
1841
1842static struct parisc_device_id sba_tbl[] = {
1843 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1844 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1845 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1846 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1847 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1848 { 0, }
1849};
1850
1851int sba_driver_callback(struct parisc_device *);
1852
1853static struct parisc_driver sba_driver = {
1854 .name = MODULE_NAME,
1855 .id_table = sba_tbl,
1856 .probe = sba_driver_callback,
1857};
1858
1859/*
1860** Determine if sba should claim this chip (return 0) or not (return 1).
1861** If so, initialize the chip and tell other partners in crime they
1862** have work to do.
1863*/
1864int
1865sba_driver_callback(struct parisc_device *dev)
1866{
1867 struct sba_device *sba_dev;
1868 u32 func_class;
1869 int i;
1870 char *version;
Helge Deller5076c152006-03-27 12:52:15 -07001871 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001872 struct proc_dir_entry *info_entry, *bitmap_entry, *root;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001873
1874 sba_dump_ranges(sba_addr);
1875
1876 /* Read HW Rev First */
1877 func_class = READ_REG(sba_addr + SBA_FCLASS);
1878
Kyle McMartin1b240f42006-08-24 21:30:19 -04001879 if (IS_ASTRO(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 unsigned long fclass;
1881 static char astro_rev[]="Astro ?.?";
1882
1883 /* Astro is broken...Read HW Rev First */
1884 fclass = READ_REG(sba_addr);
1885
1886 astro_rev[6] = '1' + (char) (fclass & 0x7);
1887 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1888 version = astro_rev;
1889
Kyle McMartin1b240f42006-08-24 21:30:19 -04001890 } else if (IS_IKE(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 static char ike_rev[] = "Ike rev ?";
1892 ike_rev[8] = '0' + (char) (func_class & 0xff);
1893 version = ike_rev;
Kyle McMartin1b240f42006-08-24 21:30:19 -04001894 } else if (IS_PLUTO(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 static char pluto_rev[]="Pluto ?.?";
1896 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1897 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1898 version = pluto_rev;
1899 } else {
1900 static char reo_rev[] = "REO rev ?";
1901 reo_rev[8] = '0' + (char) (func_class & 0xff);
1902 version = reo_rev;
1903 }
1904
1905 if (!global_ioc_cnt) {
1906 global_ioc_cnt = count_parisc_driver(&sba_driver);
1907
1908 /* Astro and Pluto have one IOC per SBA */
Kyle McMartin1b240f42006-08-24 21:30:19 -04001909 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910 global_ioc_cnt *= 2;
1911 }
1912
Kyle McMartine9a03992007-10-18 00:04:00 -07001913 printk(KERN_INFO "%s found %s at 0x%llx\n",
1914 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915
Helge Dellercb6fc182006-01-17 12:40:40 -07001916 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917 if (!sba_dev) {
1918 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1919 return -ENOMEM;
1920 }
1921
1922 parisc_set_drvdata(dev, sba_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001923
1924 for(i=0; i<MAX_IOC; i++)
1925 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1926
1927 sba_dev->dev = dev;
1928 sba_dev->hw_rev = func_class;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 sba_dev->name = dev->name;
1930 sba_dev->sba_hpa = sba_addr;
1931
1932 sba_get_pat_resources(sba_dev);
1933 sba_hw_init(sba_dev);
1934 sba_common_init(sba_dev);
1935
1936 hppa_dma_ops = &sba_ops;
1937
1938#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001939 switch (dev->id.hversion) {
1940 case PLUTO_MCKINLEY_PORT:
1941 root = proc_mckinley_root;
1942 break;
1943 case ASTRO_RUNWAY_PORT:
1944 case IKE_MERCED_PORT:
1945 default:
1946 root = proc_runway_root;
1947 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001948 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001949
1950 info_entry = create_proc_entry("sba_iommu", 0, root);
1951 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root);
1952
1953 if (info_entry)
1954 info_entry->proc_fops = &sba_proc_fops;
1955
1956 if (bitmap_entry)
1957 bitmap_entry->proc_fops = &sba_proc_bitmap_fops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001959
Linus Torvalds1da177e2005-04-16 15:20:36 -07001960 parisc_vmerge_boundary = IOVP_SIZE;
1961 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
1962 parisc_has_iommu();
1963 return 0;
1964}
1965
1966/*
1967** One time initialization to let the world know the SBA was found.
1968** This is the only routine which is NOT static.
1969** Must be called exactly once before pci_init().
1970*/
1971void __init sba_init(void)
1972{
1973 register_parisc_driver(&sba_driver);
1974}
1975
1976
1977/**
1978 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
1979 * @dev: The parisc device.
1980 *
1981 * Returns the appropriate IOMMU data for the given parisc PCI controller.
1982 * This is cached and used later for PCI DMA Mapping.
1983 */
1984void * sba_get_iommu(struct parisc_device *pci_hba)
1985{
1986 struct parisc_device *sba_dev = parisc_parent(pci_hba);
1987 struct sba_device *sba = sba_dev->dev.driver_data;
1988 char t = sba_dev->id.hw_type;
1989 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
1990
1991 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
1992
1993 return &(sba->ioc[iocnum]);
1994}
1995
1996
1997/**
1998 * sba_directed_lmmio - return first directed LMMIO range routed to rope
1999 * @pa_dev: The parisc device.
2000 * @r: resource PCI host controller wants start/end fields assigned.
2001 *
2002 * For the given parisc PCI controller, determine if any direct ranges
2003 * are routed down the corresponding rope.
2004 */
2005void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2006{
2007 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2008 struct sba_device *sba = sba_dev->dev.driver_data;
2009 char t = sba_dev->id.hw_type;
2010 int i;
2011 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2012
Eric Sesterhennb7494552006-03-24 18:52:10 +01002013 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014
2015 r->start = r->end = 0;
2016
2017 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2018 for (i=0; i<4; i++) {
2019 int base, size;
2020 void __iomem *reg = sba->sba_hpa + i*0x18;
2021
2022 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2023 if ((base & 1) == 0)
2024 continue; /* not enabled */
2025
2026 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2027
2028 if ((size & (ROPES_PER_IOC-1)) != rope)
2029 continue; /* directed down different rope */
2030
2031 r->start = (base & ~1UL) | PCI_F_EXTEND;
2032 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2033 r->end = r->start + size;
2034 }
2035}
2036
2037
2038/**
2039 * sba_distributed_lmmio - return portion of distributed LMMIO range
2040 * @pa_dev: The parisc device.
2041 * @r: resource PCI host controller wants start/end fields assigned.
2042 *
2043 * For the given parisc PCI controller, return portion of distributed LMMIO
2044 * range. The distributed LMMIO is always present and it's just a question
2045 * of the base address and size of the range.
2046 */
2047void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2048{
2049 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2050 struct sba_device *sba = sba_dev->dev.driver_data;
2051 char t = sba_dev->id.hw_type;
2052 int base, size;
2053 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2054
Eric Sesterhennb7494552006-03-24 18:52:10 +01002055 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056
2057 r->start = r->end = 0;
2058
2059 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2060 if ((base & 1) == 0) {
2061 BUG(); /* Gah! Distr Range wasn't enabled! */
2062 return;
2063 }
2064
2065 r->start = (base & ~1UL) | PCI_F_EXTEND;
2066
2067 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2068 r->start += rope * (size + 1); /* adjust base for this rope */
2069 r->end = r->start + size;
2070}