Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 1 | #ifndef _DMA_REMAPPING_H |
| 2 | #define _DMA_REMAPPING_H |
| 3 | |
| 4 | /* |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 5 | * VT-d hardware uses 4KiB page size regardless of host page size. |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 6 | */ |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 7 | #define VTD_PAGE_SHIFT (12) |
| 8 | #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) |
| 9 | #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) |
| 10 | #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 11 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 12 | #define VTD_STRIDE_SHIFT (9) |
| 13 | #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) |
| 14 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 15 | #define DMA_PTE_READ (1) |
| 16 | #define DMA_PTE_WRITE (2) |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 17 | #define DMA_PTE_LARGE_PAGE (1 << 7) |
Sheng Yang | 9cf0669 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 18 | #define DMA_PTE_SNP (1 << 11) |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 19 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 20 | #define CONTEXT_TT_MULTI_LEVEL 0 |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 21 | #define CONTEXT_TT_DEV_IOTLB 1 |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 22 | #define CONTEXT_TT_PASS_THROUGH 2 |
David Woodhouse | 2f26e0a | 2015-09-09 11:40:47 +0100 | [diff] [blame] | 23 | /* Extended context entry types */ |
| 24 | #define CONTEXT_TT_PT_PASID 4 |
| 25 | #define CONTEXT_TT_PT_PASID_DEV_IOTLB 5 |
| 26 | #define CONTEXT_TT_MASK (7ULL << 2) |
| 27 | |
David Woodhouse | 907fea3 | 2015-10-13 14:11:13 +0100 | [diff] [blame] | 28 | #define CONTEXT_DINVE (1ULL << 8) |
David Woodhouse | 2f26e0a | 2015-09-09 11:40:47 +0100 | [diff] [blame] | 29 | #define CONTEXT_PRS (1ULL << 9) |
| 30 | #define CONTEXT_PASIDE (1ULL << 11) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 31 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 32 | struct intel_iommu; |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 33 | struct dmar_domain; |
| 34 | struct root_entry; |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 35 | |
Ingo Molnar | c66b990 | 2009-01-04 10:55:02 +0100 | [diff] [blame] | 36 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 37 | #ifdef CONFIG_INTEL_IOMMU |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 38 | extern int iommu_calculate_agaw(struct intel_iommu *iommu); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 39 | extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu); |
Suresh Siddha | f5d1b97 | 2011-08-23 17:05:22 -0700 | [diff] [blame] | 40 | extern int dmar_disabled; |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 41 | extern int intel_iommu_enabled; |
Shaohua Li | bfd20f1 | 2017-04-26 09:18:35 -0700 | [diff] [blame] | 42 | extern int intel_iommu_tboot_noforce; |
Ingo Molnar | c66b990 | 2009-01-04 10:55:02 +0100 | [diff] [blame] | 43 | #else |
| 44 | static inline int iommu_calculate_agaw(struct intel_iommu *iommu) |
| 45 | { |
| 46 | return 0; |
| 47 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 48 | static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) |
| 49 | { |
| 50 | return 0; |
| 51 | } |
Suresh Siddha | f5d1b97 | 2011-08-23 17:05:22 -0700 | [diff] [blame] | 52 | #define dmar_disabled (1) |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 53 | #define intel_iommu_enabled (0) |
Ingo Molnar | c66b990 | 2009-01-04 10:55:02 +0100 | [diff] [blame] | 54 | #endif |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 55 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 56 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 57 | #endif |