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Suresh Siddhae61d98d2008-07-10 11:16:35 -07001#ifndef _DMA_REMAPPING_H
2#define _DMA_REMAPPING_H
3
4/*
Fenghua Yu5b6985c2008-10-16 18:02:32 -07005 * VT-d hardware uses 4KiB page size regardless of host page size.
Suresh Siddhae61d98d2008-07-10 11:16:35 -07006 */
Fenghua Yu5b6985c2008-10-16 18:02:32 -07007#define VTD_PAGE_SHIFT (12)
8#define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
9#define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
10#define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
Suresh Siddhae61d98d2008-07-10 11:16:35 -070011
Youquan Song6dd9a7c2011-05-25 19:13:49 +010012#define VTD_STRIDE_SHIFT (9)
13#define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
14
Suresh Siddhae61d98d2008-07-10 11:16:35 -070015#define DMA_PTE_READ (1)
16#define DMA_PTE_WRITE (2)
Youquan Song6dd9a7c2011-05-25 19:13:49 +010017#define DMA_PTE_LARGE_PAGE (1 << 7)
Sheng Yang9cf06692009-03-18 15:33:07 +080018#define DMA_PTE_SNP (1 << 11)
Suresh Siddhae61d98d2008-07-10 11:16:35 -070019
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -070020#define CONTEXT_TT_MULTI_LEVEL 0
Yu Zhao93a23a72009-05-18 13:51:37 +080021#define CONTEXT_TT_DEV_IOTLB 1
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -070022#define CONTEXT_TT_PASS_THROUGH 2
David Woodhouse2f26e0a2015-09-09 11:40:47 +010023/* Extended context entry types */
24#define CONTEXT_TT_PT_PASID 4
25#define CONTEXT_TT_PT_PASID_DEV_IOTLB 5
26#define CONTEXT_TT_MASK (7ULL << 2)
27
David Woodhouse907fea32015-10-13 14:11:13 +010028#define CONTEXT_DINVE (1ULL << 8)
David Woodhouse2f26e0a2015-09-09 11:40:47 +010029#define CONTEXT_PRS (1ULL << 9)
30#define CONTEXT_PASIDE (1ULL << 11)
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -070031
Suresh Siddhae61d98d2008-07-10 11:16:35 -070032struct intel_iommu;
Mark McLoughlin99126f72008-11-20 15:49:47 +000033struct dmar_domain;
34struct root_entry;
Suresh Siddhae61d98d2008-07-10 11:16:35 -070035
Ingo Molnarc66b9902009-01-04 10:55:02 +010036
Suresh Siddhad3f13812011-08-23 17:05:25 -070037#ifdef CONFIG_INTEL_IOMMU
Weidong Han1b573682008-12-08 15:34:06 +080038extern int iommu_calculate_agaw(struct intel_iommu *iommu);
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -070039extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
Suresh Siddhaf5d1b972011-08-23 17:05:22 -070040extern int dmar_disabled;
Eugeni Dodonov8bc1f852011-11-23 16:42:14 -020041extern int intel_iommu_enabled;
Shaohua Libfd20f12017-04-26 09:18:35 -070042extern int intel_iommu_tboot_noforce;
Ingo Molnarc66b9902009-01-04 10:55:02 +010043#else
44static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
45{
46 return 0;
47}
Fenghua Yu4ed0d3e2009-04-24 17:30:20 -070048static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
49{
50 return 0;
51}
Suresh Siddhaf5d1b972011-08-23 17:05:22 -070052#define dmar_disabled (1)
Eugeni Dodonov8bc1f852011-11-23 16:42:14 -020053#define intel_iommu_enabled (0)
Ingo Molnarc66b9902009-01-04 10:55:02 +010054#endif
Suresh Siddhae61d98d2008-07-10 11:16:35 -070055
Suresh Siddha2ae21012008-07-10 11:16:43 -070056
Suresh Siddhae61d98d2008-07-10 11:16:35 -070057#endif