David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 1 | /* |
| 2 | * arch/powerpc/sysdev/uic.c |
| 3 | * |
| 4 | * IBM PowerPC 4xx Universal Interrupt Controller |
| 5 | * |
| 6 | * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | */ |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/errno.h> |
| 16 | #include <linux/reboot.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/stddef.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/signal.h> |
| 21 | #include <linux/sysdev.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/bootmem.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/interrupt.h> |
David Gibson | 868afce | 2007-08-14 13:52:42 +1000 | [diff] [blame] | 27 | #include <linux/kernel_stat.h> |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 28 | #include <asm/irq.h> |
| 29 | #include <asm/io.h> |
| 30 | #include <asm/prom.h> |
| 31 | #include <asm/dcr.h> |
| 32 | |
| 33 | #define NR_UIC_INTS 32 |
| 34 | |
| 35 | #define UIC_SR 0x0 |
| 36 | #define UIC_ER 0x2 |
| 37 | #define UIC_CR 0x3 |
| 38 | #define UIC_PR 0x4 |
| 39 | #define UIC_TR 0x5 |
| 40 | #define UIC_MSR 0x6 |
| 41 | #define UIC_VR 0x7 |
| 42 | #define UIC_VCR 0x8 |
| 43 | |
| 44 | #define uic_irq_to_hw(virq) (irq_map[virq].hwirq) |
| 45 | |
| 46 | struct uic *primary_uic; |
| 47 | |
| 48 | struct uic { |
| 49 | int index; |
| 50 | int dcrbase; |
| 51 | |
| 52 | spinlock_t lock; |
| 53 | |
| 54 | /* The remapper for this UIC */ |
| 55 | struct irq_host *irqhost; |
| 56 | |
| 57 | /* For secondary UICs, the cascade interrupt's irqaction */ |
| 58 | struct irqaction cascade; |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | static void uic_unmask_irq(unsigned int virq) |
| 62 | { |
| 63 | struct uic *uic = get_irq_chip_data(virq); |
| 64 | unsigned int src = uic_irq_to_hw(virq); |
| 65 | unsigned long flags; |
| 66 | u32 er; |
| 67 | |
| 68 | spin_lock_irqsave(&uic->lock, flags); |
| 69 | er = mfdcr(uic->dcrbase + UIC_ER); |
| 70 | er |= 1 << (31 - src); |
| 71 | mtdcr(uic->dcrbase + UIC_ER, er); |
| 72 | spin_unlock_irqrestore(&uic->lock, flags); |
| 73 | } |
| 74 | |
| 75 | static void uic_mask_irq(unsigned int virq) |
| 76 | { |
| 77 | struct uic *uic = get_irq_chip_data(virq); |
| 78 | unsigned int src = uic_irq_to_hw(virq); |
| 79 | unsigned long flags; |
| 80 | u32 er; |
| 81 | |
| 82 | spin_lock_irqsave(&uic->lock, flags); |
| 83 | er = mfdcr(uic->dcrbase + UIC_ER); |
| 84 | er &= ~(1 << (31 - src)); |
| 85 | mtdcr(uic->dcrbase + UIC_ER, er); |
| 86 | spin_unlock_irqrestore(&uic->lock, flags); |
| 87 | } |
| 88 | |
| 89 | static void uic_ack_irq(unsigned int virq) |
| 90 | { |
| 91 | struct uic *uic = get_irq_chip_data(virq); |
| 92 | unsigned int src = uic_irq_to_hw(virq); |
| 93 | unsigned long flags; |
| 94 | |
| 95 | spin_lock_irqsave(&uic->lock, flags); |
| 96 | mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); |
| 97 | spin_unlock_irqrestore(&uic->lock, flags); |
| 98 | } |
| 99 | |
| 100 | static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) |
| 101 | { |
| 102 | struct uic *uic = get_irq_chip_data(virq); |
| 103 | unsigned int src = uic_irq_to_hw(virq); |
| 104 | struct irq_desc *desc = get_irq_desc(virq); |
| 105 | unsigned long flags; |
| 106 | int trigger, polarity; |
| 107 | u32 tr, pr, mask; |
| 108 | |
| 109 | switch (flow_type & IRQ_TYPE_SENSE_MASK) { |
| 110 | case IRQ_TYPE_NONE: |
| 111 | uic_mask_irq(virq); |
| 112 | return 0; |
| 113 | |
| 114 | case IRQ_TYPE_EDGE_RISING: |
| 115 | trigger = 1; polarity = 1; |
| 116 | break; |
| 117 | case IRQ_TYPE_EDGE_FALLING: |
| 118 | trigger = 1; polarity = 0; |
| 119 | break; |
| 120 | case IRQ_TYPE_LEVEL_HIGH: |
| 121 | trigger = 0; polarity = 1; |
| 122 | break; |
| 123 | case IRQ_TYPE_LEVEL_LOW: |
| 124 | trigger = 0; polarity = 0; |
| 125 | break; |
| 126 | default: |
| 127 | return -EINVAL; |
| 128 | } |
| 129 | |
| 130 | mask = ~(1 << (31 - src)); |
| 131 | |
| 132 | spin_lock_irqsave(&uic->lock, flags); |
| 133 | tr = mfdcr(uic->dcrbase + UIC_TR); |
| 134 | pr = mfdcr(uic->dcrbase + UIC_PR); |
| 135 | tr = (tr & mask) | (trigger << (31-src)); |
| 136 | pr = (pr & mask) | (polarity << (31-src)); |
| 137 | |
| 138 | mtdcr(uic->dcrbase + UIC_PR, pr); |
| 139 | mtdcr(uic->dcrbase + UIC_TR, tr); |
| 140 | |
| 141 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); |
| 142 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; |
David Gibson | 4dc7b4b | 2007-08-14 13:52:42 +1000 | [diff] [blame] | 143 | if (!trigger) |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 144 | desc->status |= IRQ_LEVEL; |
| 145 | |
| 146 | spin_unlock_irqrestore(&uic->lock, flags); |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | static struct irq_chip uic_irq_chip = { |
| 152 | .typename = " UIC ", |
| 153 | .unmask = uic_unmask_irq, |
| 154 | .mask = uic_mask_irq, |
| 155 | /* .mask_ack = uic_mask_irq_and_ack, */ |
| 156 | .ack = uic_ack_irq, |
| 157 | .set_type = uic_set_irq_type, |
| 158 | }; |
| 159 | |
David Gibson | 868afce | 2007-08-14 13:52:42 +1000 | [diff] [blame] | 160 | /** |
| 161 | * handle_uic_irq - irq flow handler for UIC |
| 162 | * @irq: the interrupt number |
| 163 | * @desc: the interrupt description structure for this irq |
| 164 | * |
| 165 | * This is modified version of the generic handle_level_irq() suitable |
| 166 | * for the UIC. On the UIC, acking (i.e. clearing the SR bit) a level |
| 167 | * irq will have no effect if the interrupt is still asserted by the |
| 168 | * device, even if the interrupt is already masked. Therefore, unlike |
| 169 | * the standard handle_level_irq(), we must ack the interrupt *after* |
| 170 | * invoking the ISR (which should have de-asserted the interrupt in |
| 171 | * the external source). For edge interrupts we ack at the beginning |
| 172 | * instead of the end, to keep the window in which we can miss an |
| 173 | * interrupt as small as possible. |
| 174 | */ |
| 175 | void fastcall handle_uic_irq(unsigned int irq, struct irq_desc *desc) |
| 176 | { |
| 177 | unsigned int cpu = smp_processor_id(); |
| 178 | struct irqaction *action; |
| 179 | irqreturn_t action_ret; |
| 180 | |
| 181 | spin_lock(&desc->lock); |
| 182 | if (desc->status & IRQ_LEVEL) |
| 183 | desc->chip->mask(irq); |
| 184 | else |
| 185 | desc->chip->mask_ack(irq); |
| 186 | |
| 187 | if (unlikely(desc->status & IRQ_INPROGRESS)) |
| 188 | goto out_unlock; |
| 189 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
| 190 | kstat_cpu(cpu).irqs[irq]++; |
| 191 | |
| 192 | /* |
| 193 | * If its disabled or no action available |
| 194 | * keep it masked and get out of here |
| 195 | */ |
| 196 | action = desc->action; |
| 197 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
| 198 | desc->status |= IRQ_PENDING; |
| 199 | goto out_unlock; |
| 200 | } |
| 201 | |
| 202 | desc->status |= IRQ_INPROGRESS; |
| 203 | desc->status &= ~IRQ_PENDING; |
| 204 | spin_unlock(&desc->lock); |
| 205 | |
| 206 | action_ret = handle_IRQ_event(irq, action); |
| 207 | |
| 208 | spin_lock(&desc->lock); |
| 209 | desc->status &= ~IRQ_INPROGRESS; |
| 210 | if (desc->status & IRQ_LEVEL) |
| 211 | desc->chip->ack(irq); |
| 212 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
| 213 | desc->chip->unmask(irq); |
| 214 | out_unlock: |
| 215 | spin_unlock(&desc->lock); |
| 216 | } |
| 217 | |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 218 | static int uic_host_map(struct irq_host *h, unsigned int virq, |
| 219 | irq_hw_number_t hw) |
| 220 | { |
| 221 | struct uic *uic = h->host_data; |
| 222 | |
| 223 | set_irq_chip_data(virq, uic); |
| 224 | /* Despite the name, handle_level_irq() works for both level |
| 225 | * and edge irqs on UIC. FIXME: check this is correct */ |
David Gibson | 868afce | 2007-08-14 13:52:42 +1000 | [diff] [blame] | 226 | set_irq_chip_and_handler(virq, &uic_irq_chip, handle_uic_irq); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 227 | |
| 228 | /* Set default irq type */ |
| 229 | set_irq_type(virq, IRQ_TYPE_NONE); |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
| 234 | static int uic_host_xlate(struct irq_host *h, struct device_node *ct, |
| 235 | u32 *intspec, unsigned int intsize, |
| 236 | irq_hw_number_t *out_hwirq, unsigned int *out_type) |
| 237 | |
| 238 | { |
| 239 | /* UIC intspecs must have 2 cells */ |
| 240 | BUG_ON(intsize != 2); |
| 241 | *out_hwirq = intspec[0]; |
| 242 | *out_type = intspec[1]; |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static struct irq_host_ops uic_host_ops = { |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 247 | .map = uic_host_map, |
| 248 | .xlate = uic_host_xlate, |
| 249 | }; |
| 250 | |
| 251 | irqreturn_t uic_cascade(int virq, void *data) |
| 252 | { |
| 253 | struct uic *uic = data; |
| 254 | u32 msr; |
| 255 | int src; |
| 256 | int subvirq; |
| 257 | |
| 258 | msr = mfdcr(uic->dcrbase + UIC_MSR); |
David Gibson | 553fdff | 2007-08-14 13:52:42 +1000 | [diff] [blame] | 259 | if (!msr) /* spurious interrupt */ |
| 260 | return IRQ_HANDLED; |
| 261 | |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 262 | src = 32 - ffs(msr); |
| 263 | |
| 264 | subvirq = irq_linear_revmap(uic->irqhost, src); |
| 265 | generic_handle_irq(subvirq); |
| 266 | |
| 267 | return IRQ_HANDLED; |
| 268 | } |
| 269 | |
| 270 | static struct uic * __init uic_init_one(struct device_node *node) |
| 271 | { |
| 272 | struct uic *uic; |
| 273 | const u32 *indexp, *dcrreg; |
| 274 | int len; |
| 275 | |
Stephen Rothwell | 55b61fe | 2007-05-03 17:26:52 +1000 | [diff] [blame] | 276 | BUG_ON(! of_device_is_compatible(node, "ibm,uic")); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 277 | |
| 278 | uic = alloc_bootmem(sizeof(*uic)); |
| 279 | if (! uic) |
| 280 | return NULL; /* FIXME: panic? */ |
| 281 | |
| 282 | memset(uic, 0, sizeof(*uic)); |
| 283 | spin_lock_init(&uic->lock); |
Stephen Rothwell | 12d371a | 2007-04-29 16:29:08 +1000 | [diff] [blame] | 284 | indexp = of_get_property(node, "cell-index", &len); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 285 | if (!indexp || (len != sizeof(u32))) { |
| 286 | printk(KERN_ERR "uic: Device node %s has missing or invalid " |
| 287 | "cell-index property\n", node->full_name); |
| 288 | return NULL; |
| 289 | } |
| 290 | uic->index = *indexp; |
| 291 | |
Stephen Rothwell | 12d371a | 2007-04-29 16:29:08 +1000 | [diff] [blame] | 292 | dcrreg = of_get_property(node, "dcr-reg", &len); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 293 | if (!dcrreg || (len != 2*sizeof(u32))) { |
| 294 | printk(KERN_ERR "uic: Device node %s has missing or invalid " |
| 295 | "dcr-reg property\n", node->full_name); |
| 296 | return NULL; |
| 297 | } |
| 298 | uic->dcrbase = *dcrreg; |
| 299 | |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 300 | uic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR, |
| 301 | NR_UIC_INTS, &uic_host_ops, -1); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 302 | if (! uic->irqhost) { |
| 303 | of_node_put(node); |
| 304 | return NULL; /* FIXME: panic? */ |
| 305 | } |
| 306 | |
| 307 | uic->irqhost->host_data = uic; |
| 308 | |
| 309 | /* Start with all interrupts disabled, level and non-critical */ |
| 310 | mtdcr(uic->dcrbase + UIC_ER, 0); |
| 311 | mtdcr(uic->dcrbase + UIC_CR, 0); |
| 312 | mtdcr(uic->dcrbase + UIC_TR, 0); |
| 313 | /* Clear any pending interrupts, in case the firmware left some */ |
| 314 | mtdcr(uic->dcrbase + UIC_SR, 0xffffffff); |
| 315 | |
| 316 | printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index, |
| 317 | NR_UIC_INTS, uic->dcrbase); |
| 318 | |
| 319 | return uic; |
| 320 | } |
| 321 | |
| 322 | void __init uic_init_tree(void) |
| 323 | { |
| 324 | struct device_node *np; |
| 325 | struct uic *uic; |
| 326 | const u32 *interrupts; |
| 327 | |
| 328 | /* First locate and initialize the top-level UIC */ |
| 329 | |
| 330 | np = of_find_compatible_node(NULL, NULL, "ibm,uic"); |
| 331 | while (np) { |
Stephen Rothwell | 12d371a | 2007-04-29 16:29:08 +1000 | [diff] [blame] | 332 | interrupts = of_get_property(np, "interrupts", NULL); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 333 | if (! interrupts) |
| 334 | break; |
| 335 | |
| 336 | np = of_find_compatible_node(np, NULL, "ibm,uic"); |
| 337 | } |
| 338 | |
| 339 | BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the |
| 340 | * top-level interrupt controller */ |
| 341 | primary_uic = uic_init_one(np); |
| 342 | if (! primary_uic) |
| 343 | panic("Unable to initialize primary UIC %s\n", np->full_name); |
| 344 | |
| 345 | irq_set_default_host(primary_uic->irqhost); |
| 346 | of_node_put(np); |
| 347 | |
| 348 | /* The scan again for cascaded UICs */ |
| 349 | np = of_find_compatible_node(NULL, NULL, "ibm,uic"); |
| 350 | while (np) { |
Stephen Rothwell | 12d371a | 2007-04-29 16:29:08 +1000 | [diff] [blame] | 351 | interrupts = of_get_property(np, "interrupts", NULL); |
David Gibson | e58923e | 2007-04-18 16:36:26 +1000 | [diff] [blame] | 352 | if (interrupts) { |
| 353 | /* Secondary UIC */ |
| 354 | int cascade_virq; |
| 355 | int ret; |
| 356 | |
| 357 | uic = uic_init_one(np); |
| 358 | if (! uic) |
| 359 | panic("Unable to initialize a secondary UIC %s\n", |
| 360 | np->full_name); |
| 361 | |
| 362 | cascade_virq = irq_of_parse_and_map(np, 0); |
| 363 | |
| 364 | uic->cascade.handler = uic_cascade; |
| 365 | uic->cascade.name = "UIC cascade"; |
| 366 | uic->cascade.dev_id = uic; |
| 367 | |
| 368 | ret = setup_irq(cascade_virq, &uic->cascade); |
| 369 | if (ret) |
| 370 | printk(KERN_ERR "Failed to setup_irq(%d) for " |
| 371 | "UIC%d cascade\n", cascade_virq, |
| 372 | uic->index); |
| 373 | |
| 374 | /* FIXME: setup critical cascade?? */ |
| 375 | } |
| 376 | |
| 377 | np = of_find_compatible_node(np, NULL, "ibm,uic"); |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ |
| 382 | unsigned int uic_get_irq(void) |
| 383 | { |
| 384 | u32 msr; |
| 385 | int src; |
| 386 | |
| 387 | BUG_ON(! primary_uic); |
| 388 | |
| 389 | msr = mfdcr(primary_uic->dcrbase + UIC_MSR); |
| 390 | src = 32 - ffs(msr); |
| 391 | |
| 392 | return irq_linear_revmap(primary_uic->irqhost, src); |
| 393 | } |