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Paul Mackerras047ea782005-11-19 20:17:32 +11001#ifndef _ASM_POWERPC_MMU_H_
2#define _ASM_POWERPC_MMU_H_
Arnd Bergmann88ced032005-12-16 22:43:46 +01003#ifdef __KERNEL__
Paul Mackerras047ea782005-11-19 20:17:32 +11004
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -07005#include <linux/types.h>
6
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +00007#include <asm/asm-compat.h>
8#include <asm/feature-fixups.h>
9
10/*
11 * MMU features bit definitions
12 */
13
14/*
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100015 * MMU families
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000016 */
17#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
18#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
19#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
Michael Ellermancd680982014-07-08 17:10:45 +100022#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000023
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100024/* Radix page table supported and enabled */
25#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
26
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000027/*
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100028 * Individual features below.
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000029 */
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +100030
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +053031/*
32 * We need to clear top 16bits of va (from the remaining 64 bits )in
33 * tlbie* instructions
34 */
35#define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000036
37/* Enable use of high BAT registers */
38#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
39
40/* Enable >32-bit physical addresses on 32-bit processor, only used
41 * by CONFIG_6xx currently as BookE supports that from day 1
42 */
43#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
44
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +000045/* Enable use of broadcast TLB invalidations. We don't always set it
46 * on processors that support it due to other constraints with the
47 * use of such invalidations
48 */
49#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
50
Kumar Galac3071952009-02-10 22:26:06 -060051/* Enable use of tlbilx invalidate instructions.
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +000052 */
Kumar Galac3071952009-02-10 22:26:06 -060053#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
Benjamin Herrenschmidtf048aac2008-12-18 19:13:38 +000054
55/* This indicates that the processor cannot handle multiple outstanding
56 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
57 * around such invalidate forms.
58 */
59#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
60
Kumar Gala2319f122009-03-19 03:55:41 +000061/* This indicates that the processor doesn't handle way selection
62 * properly and needs SW to track and update the LRU state. This
63 * is specific to an errata on e300c2/c3/c4 class parts
64 */
65#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
66
Kumar Galadf5d6ec2009-08-24 15:52:48 +000067/* Enable use of TLB reservation. Processor should support tlbsrx.
68 * instruction and MAS0[WQ].
69 */
70#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
71
72/* Use paired MAS registers (MAS7||MAS3, etc.)
73 */
74#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
75
Michael Ellerman13b3d132014-07-10 12:29:20 +100076/* Doesn't support the B bit (1T segment) in SLBIE
Matt Evans44ae3ab2011-04-06 19:48:50 +000077 */
Michael Ellerman13b3d132014-07-10 12:29:20 +100078#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
Matt Evans44ae3ab2011-04-06 19:48:50 +000079
80/* Support 16M large pages
81 */
82#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
83
84/* Supports TLBIEL variant
85 */
86#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
87
88/* Supports tlbies w/o locking
89 */
90#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
91
92/* Large pages can be marked CI
93 */
94#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
95
96/* 1T segments available
97 */
98#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
99
Matt Evans44ae3ab2011-04-06 19:48:50 +0000100/* MMU feature bit sets for various CPUs */
101#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
102 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
103#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +0530104#define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
Matt Evans44ae3ab2011-04-06 19:48:50 +0000105#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
106#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
Michael Neulinga32e2522011-04-06 18:23:29 +0000107#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
Michael Neuling71e18492012-10-30 19:34:15 +0000108#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
Michael Neulingc3ab3002016-02-19 11:16:24 +1100109#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
Matt Evans44ae3ab2011-04-06 19:48:50 +0000110#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
111 MMU_FTR_CI_LARGE_PAGE
112#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
113 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000114#ifndef __ASSEMBLY__
115#include <asm/cputable.h>
116
Becky Bruce3160b092011-06-28 14:54:47 -0500117#ifdef CONFIG_PPC_FSL_BOOK3E
118#include <asm/percpu.h>
119DECLARE_PER_CPU(int, next_tlbcam_idx);
120#endif
121
Michael Ellerman773edea2016-05-11 15:30:47 +1000122enum {
123 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
124 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
125 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
126 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
127 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
128 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
129 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
130 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
Aneesh Kumar K.Vaccfad72016-07-13 15:05:24 +0530131 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
Aneesh Kumar K.Va8ed87c2016-04-29 23:26:06 +1000132#ifdef CONFIG_PPC_RADIX_MMU
Aneesh Kumar K.V5a25b6f2016-07-27 13:19:01 +1000133 MMU_FTR_TYPE_RADIX |
Aneesh Kumar K.Va8ed87c2016-04-29 23:26:06 +1000134#endif
135 0,
Michael Ellerman773edea2016-05-11 15:30:47 +1000136};
137
Michael Ellermana81dc9d2016-07-27 13:39:42 +1000138static inline bool mmu_has_feature(unsigned long feature)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000139{
Michael Ellermana81dc9d2016-07-27 13:39:42 +1000140 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000141}
142
Dave Kleikamp91b191c2011-07-04 18:38:03 +0000143static inline void mmu_clear_feature(unsigned long feature)
144{
145 cur_cpu_spec->mmu_features &= ~feature;
146}
147
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000148extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
149
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -0700150#ifdef CONFIG_PPC64
151/* This is our real memory area size on ppc64 server, on embedded, we
152 * make it match the size our of bolted TLB area
153 */
154extern u64 ppc64_rma_size;
155#endif /* CONFIG_PPC64 */
156
Aneesh Kumar K.V78f1dbd2012-09-10 02:52:57 +0000157struct mm_struct;
158#ifdef CONFIG_DEBUG_VM
159extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
160#else /* CONFIG_DEBUG_VM */
161static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
162{
163}
164#endif /* !CONFIG_DEBUG_VM */
165
Michael Ellermanbab4c8d2016-07-27 13:37:58 +1000166#ifdef CONFIG_PPC_RADIX_MMU
167static inline bool radix_enabled(void)
168{
169 return mmu_has_feature(MMU_FTR_TYPE_RADIX);
170}
171#else
172static inline bool radix_enabled(void)
173{
174 return false;
175}
176#endif
177
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000178#endif /* !__ASSEMBLY__ */
179
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +1000180/* The kernel use the constants below to index in the page sizes array.
181 * The use of fixed constants for this purpose is better for performances
182 * of the low level hash refill handlers.
183 *
184 * A non supported page size has a "shift" field set to 0
185 *
186 * Any new page size being implemented can get a new entry in here. Whether
187 * the kernel will use it or not is a different matter though. The actual page
188 * size used by hugetlbfs is not defined here and may be made variable
189 *
190 * Note: This array ended up being a false good idea as it's growing to the
191 * point where I wonder if we should replace it with something different,
192 * to think about, feedback welcome. --BenH.
193 */
194
Scott Wooda8b91e42012-06-14 13:40:55 +0000195/* These are #defines as they have to be used in assembly */
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +1000196#define MMU_PAGE_4K 0
197#define MMU_PAGE_16K 1
198#define MMU_PAGE_64K 2
199#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
200#define MMU_PAGE_256K 4
201#define MMU_PAGE_1M 5
Scott Wood28efc352013-10-11 19:22:38 -0500202#define MMU_PAGE_2M 6
203#define MMU_PAGE_4M 7
204#define MMU_PAGE_8M 8
205#define MMU_PAGE_16M 9
206#define MMU_PAGE_64M 10
207#define MMU_PAGE_256M 11
208#define MMU_PAGE_1G 12
209#define MMU_PAGE_16G 13
210#define MMU_PAGE_64G 14
Benjamin Herrenschmidt57e2a992009-07-28 11:59:34 +1000211
Scott Wood28efc352013-10-11 19:22:38 -0500212#define MMU_PAGE_COUNT 15
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000213
Aneesh Kumar K.V11a6f6a2016-04-29 23:25:41 +1000214#ifdef CONFIG_PPC_BOOK3S_64
215#include <asm/book3s/64/mmu.h>
216#else /* CONFIG_PPC_BOOK3S_64 */
217
Aneesh Kumar K.V756d08d2016-04-29 23:25:57 +1000218#ifndef __ASSEMBLY__
219/* MMU initialization */
220extern void early_init_mmu(void);
221extern void early_init_mmu_secondary(void);
222extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
223 phys_addr_t first_memblock_size);
Michael Ellerman1a01dc82016-07-26 20:09:30 +1000224static inline void mmu_early_init_devtree(void) { }
Aneesh Kumar K.V756d08d2016-04-29 23:25:57 +1000225#endif /* __ASSEMBLY__ */
Aneesh Kumar K.V11a6f6a2016-04-29 23:25:41 +1000226#endif
227
228#if defined(CONFIG_PPC_STD_MMU_32)
David Gibson4db68bf2007-06-13 14:52:54 +1000229/* 32-bit classic hash table MMU */
Aneesh Kumar K.Vf64e8082016-03-01 12:59:20 +0530230#include <asm/book3s/32/mmu-hash.h>
Josh Boyer4d922c82007-08-20 07:28:48 -0500231#elif defined(CONFIG_40x)
232/* 40x-style software loaded TLB */
233# include <asm/mmu-40x.h>
David Gibson57d79092007-04-30 14:06:25 +1000234#elif defined(CONFIG_44x)
235/* 44x-style software loaded TLB */
236# include <asm/mmu-44x.h>
Kumar Gala70fe3af2009-02-12 16:12:40 -0600237#elif defined(CONFIG_PPC_BOOK3E_MMU)
238/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
239# include <asm/mmu-book3e.h>
David Gibson31202342007-06-22 14:58:55 +1000240#elif defined (CONFIG_PPC_8xx)
241/* Motorola/Freescale 8xx software loaded TLB */
242# include <asm/mmu-8xx.h>
David Gibson1f8d4192005-05-05 16:15:13 -0700243#endif
David Gibson1f8d4192005-05-05 16:15:13 -0700244
Arnd Bergmann88ced032005-12-16 22:43:46 +0100245#endif /* __KERNEL__ */
Paul Mackerras047ea782005-11-19 20:17:32 +1100246#endif /* _ASM_POWERPC_MMU_H_ */